1 /* $OpenBSD: glkgpio.c,v 1.6 2022/10/20 20:40:57 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2016 Mark Kettenis 4 * Copyright (c) 2019 James Hastings 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/param.h> 20 #include <sys/malloc.h> 21 #include <sys/systm.h> 22 23 #include <dev/acpi/acpireg.h> 24 #include <dev/acpi/acpivar.h> 25 #include <dev/acpi/acpidev.h> 26 #include <dev/acpi/amltypes.h> 27 #include <dev/acpi/dsdt.h> 28 29 #define GLKGPIO_CONF_TXSTATE 0x00000001 30 #define GLKGPIO_CONF_RXSTATE 0x00000002 31 #define GLKGPIO_CONF_RXINV 0x00800000 32 #define GLKGPIO_CONF_RXEV_EDGE 0x02000000 33 #define GLKGPIO_CONF_RXEV_ZERO 0x04000000 34 #define GLKGPIO_CONF_RXEV_MASK 0x06000000 35 36 #define GLKGPIO_IRQ_STS 0x100 37 #define GLKGPIO_IRQ_EN 0x110 38 #define GLKGPIO_PAD_CFG0 0x600 39 40 struct glkgpio_intrhand { 41 int (*ih_func)(void *); 42 void *ih_arg; 43 }; 44 45 struct glkgpio_softc { 46 struct device sc_dev; 47 struct acpi_softc *sc_acpi; 48 struct aml_node *sc_node; 49 50 bus_space_tag_t sc_memt; 51 bus_space_handle_t sc_memh; 52 void *sc_ih; 53 54 int sc_npins; 55 struct glkgpio_intrhand *sc_pin_ih; 56 57 struct acpi_gpio sc_gpio; 58 }; 59 60 int glkgpio_match(struct device *, void *, void *); 61 void glkgpio_attach(struct device *, struct device *, void *); 62 63 const struct cfattach glkgpio_ca = { 64 sizeof(struct glkgpio_softc), glkgpio_match, glkgpio_attach 65 }; 66 67 struct cfdriver glkgpio_cd = { 68 NULL, "glkgpio", DV_DULL 69 }; 70 71 const char *glkgpio_hids[] = { 72 "INT3453", 73 NULL 74 }; 75 76 int glkgpio_parse_resources(int, union acpi_resource *, void *); 77 int glkgpio_read_pin(void *, int); 78 void glkgpio_write_pin(void *, int, int); 79 void glkgpio_intr_establish(void *, int, int, int (*)(void *), void *); 80 void glkgpio_intr_enable(void *, int); 81 void glkgpio_intr_disable(void *, int); 82 int glkgpio_intr(void *); 83 84 int 85 glkgpio_match(struct device *parent, void *match, void *aux) 86 { 87 struct acpi_attach_args *aaa = aux; 88 struct cfdata *cf = match; 89 90 if (aaa->aaa_naddr < 1 || aaa->aaa_nirq < 1) 91 return 0; 92 return acpi_matchhids(aaa, glkgpio_hids, cf->cf_driver->cd_name); 93 } 94 95 void 96 glkgpio_attach(struct device *parent, struct device *self, void *aux) 97 { 98 struct glkgpio_softc *sc = (struct glkgpio_softc *)self; 99 struct acpi_attach_args *aaa = aux; 100 int64_t uid; 101 int i; 102 103 sc->sc_acpi = (struct acpi_softc *)parent; 104 sc->sc_node = aaa->aaa_node; 105 printf(" %s", sc->sc_node->name); 106 107 if (aml_evalinteger(sc->sc_acpi, sc->sc_node, "_UID", 0, NULL, &uid)) { 108 printf(": can't find uid\n"); 109 return; 110 } 111 112 printf(" uid %lld", uid); 113 114 switch (uid) { 115 case 1: 116 sc->sc_npins = 80; 117 break; 118 case 2: 119 sc->sc_npins = 80; 120 break; 121 case 3: 122 sc->sc_npins = 20; 123 break; 124 case 4: 125 sc->sc_npins = 35; 126 break; 127 default: 128 printf("\n"); 129 return; 130 } 131 132 printf(" addr 0x%llx/0x%llx", aaa->aaa_addr[0], aaa->aaa_size[0]); 133 printf(" irq %d", aaa->aaa_irq[0]); 134 135 sc->sc_memt = aaa->aaa_bst[0]; 136 if (bus_space_map(sc->sc_memt, aaa->aaa_addr[0], aaa->aaa_size[0], 137 0, &sc->sc_memh)) { 138 printf(": can't map registers\n"); 139 return; 140 } 141 142 sc->sc_pin_ih = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_ih), 143 M_DEVBUF, M_WAITOK | M_ZERO); 144 145 sc->sc_ih = acpi_intr_establish(aaa->aaa_irq[0], aaa->aaa_irq_flags[0], 146 IPL_BIO, glkgpio_intr, sc, sc->sc_dev.dv_xname); 147 if (sc->sc_ih == NULL) { 148 printf(": can't establish interrupt\n"); 149 goto unmap; 150 } 151 152 sc->sc_gpio.cookie = sc; 153 sc->sc_gpio.read_pin = glkgpio_read_pin; 154 sc->sc_gpio.write_pin = glkgpio_write_pin; 155 sc->sc_gpio.intr_establish = glkgpio_intr_establish; 156 sc->sc_gpio.intr_enable = glkgpio_intr_enable; 157 sc->sc_gpio.intr_disable = glkgpio_intr_disable; 158 sc->sc_node->gpio = &sc->sc_gpio; 159 160 /* Mask and clear all interrupts. */ 161 for (i = 0; i < sc->sc_npins; i++) { 162 if (i % 32 == 0) { 163 bus_space_write_4(sc->sc_memt, sc->sc_memh, 164 GLKGPIO_IRQ_EN + (i / 32) * 4, 0x00000000); 165 bus_space_write_4(sc->sc_memt, sc->sc_memh, 166 GLKGPIO_IRQ_STS + (i / 32) * 4, 0xffffffff); 167 } 168 } 169 170 printf(", %d pins\n", sc->sc_npins); 171 172 acpi_register_gpio(sc->sc_acpi, sc->sc_node); 173 return; 174 175 unmap: 176 free(sc->sc_pin_ih, M_DEVBUF, sc->sc_npins * sizeof(*sc->sc_pin_ih)); 177 bus_space_unmap(sc->sc_memt, sc->sc_memh, aaa->aaa_size[0]); 178 } 179 180 int 181 glkgpio_read_pin(void *cookie, int pin) 182 { 183 struct glkgpio_softc *sc = cookie; 184 uint32_t reg; 185 186 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 187 GLKGPIO_PAD_CFG0 + pin * 16); 188 189 return !!(reg & GLKGPIO_CONF_RXSTATE); 190 } 191 192 void 193 glkgpio_write_pin(void *cookie, int pin, int value) 194 { 195 struct glkgpio_softc *sc = cookie; 196 uint32_t reg; 197 198 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 199 GLKGPIO_PAD_CFG0 + pin * 16); 200 if (value) 201 reg |= GLKGPIO_CONF_TXSTATE; 202 else 203 reg &= ~GLKGPIO_CONF_TXSTATE; 204 bus_space_write_4(sc->sc_memt, sc->sc_memh, 205 GLKGPIO_PAD_CFG0 + pin * 16, reg); 206 } 207 208 void 209 glkgpio_intr_establish(void *cookie, int pin, int flags, 210 int (*func)(void *), void *arg) 211 { 212 struct glkgpio_softc *sc = cookie; 213 uint32_t reg; 214 215 KASSERT(pin >= 0 && pin < sc->sc_npins); 216 217 sc->sc_pin_ih[pin].ih_func = func; 218 sc->sc_pin_ih[pin].ih_arg = arg; 219 220 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 221 GLKGPIO_PAD_CFG0 + pin * 16); 222 reg &= ~(GLKGPIO_CONF_RXEV_MASK | GLKGPIO_CONF_RXINV); 223 if ((flags & LR_GPIO_MODE) == 1) 224 reg |= GLKGPIO_CONF_RXEV_EDGE; 225 if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTLO) 226 reg |= GLKGPIO_CONF_RXINV; 227 if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTBOTH) 228 reg |= GLKGPIO_CONF_RXEV_EDGE | GLKGPIO_CONF_RXEV_ZERO; 229 bus_space_write_4(sc->sc_memt, sc->sc_memh, 230 GLKGPIO_PAD_CFG0 + pin * 16, reg); 231 232 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 233 GLKGPIO_IRQ_EN + (pin / 32) * 4); 234 reg |= (1 << (pin % 32)); 235 bus_space_write_4(sc->sc_memt, sc->sc_memh, 236 GLKGPIO_IRQ_EN + (pin / 32) * 4, reg); 237 } 238 239 void 240 glkgpio_intr_enable(void *cookie, int pin) 241 { 242 struct glkgpio_softc *sc = cookie; 243 uint32_t reg; 244 245 KASSERT(pin >= 0 && pin < sc->sc_npins); 246 247 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 248 GLKGPIO_IRQ_EN + (pin / 32) * 4); 249 reg |= (1 << (pin % 32)); 250 bus_space_write_4(sc->sc_memt, sc->sc_memh, 251 GLKGPIO_IRQ_EN + (pin / 32) * 4, reg); 252 } 253 254 void 255 glkgpio_intr_disable(void *cookie, int pin) 256 { 257 struct glkgpio_softc *sc = cookie; 258 uint32_t reg; 259 260 KASSERT(pin >= 0 && pin < sc->sc_npins); 261 262 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 263 GLKGPIO_IRQ_EN + (pin / 32) * 4); 264 reg &= ~(1 << (pin % 32)); 265 bus_space_write_4(sc->sc_memt, sc->sc_memh, 266 GLKGPIO_IRQ_EN + (pin / 32) * 4, reg); 267 } 268 269 int 270 glkgpio_intr(void *arg) 271 { 272 struct glkgpio_softc *sc = arg; 273 uint32_t status, enable; 274 int rc = 0; 275 int pin; 276 277 for (pin = 0; pin < sc->sc_npins; pin++) { 278 if (pin % 32 == 0) { 279 status = bus_space_read_4(sc->sc_memt, sc->sc_memh, 280 GLKGPIO_IRQ_STS + (pin / 32) * 4); 281 bus_space_write_4(sc->sc_memt, sc->sc_memh, 282 GLKGPIO_IRQ_STS + (pin / 32) * 4, status); 283 enable = bus_space_read_4(sc->sc_memt, sc->sc_memh, 284 GLKGPIO_IRQ_EN + (pin / 32) * 4); 285 status &= enable; 286 } 287 if (status & (1 << (pin % 32))) { 288 if (sc->sc_pin_ih[pin].ih_func) 289 sc->sc_pin_ih[pin].ih_func(sc->sc_pin_ih[pin].ih_arg); 290 rc = 1; 291 } 292 } 293 return rc; 294 } 295