1 /* $OpenBSD: aplgpio.c,v 1.3 2021/05/16 08:50:59 jsg Exp $ */ 2 /* 3 * Copyright (c) 2016 Mark Kettenis 4 * Copyright (c) 2019 James Hastings 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/param.h> 20 #include <sys/malloc.h> 21 #include <sys/systm.h> 22 23 #include <dev/acpi/acpireg.h> 24 #include <dev/acpi/acpivar.h> 25 #include <dev/acpi/acpidev.h> 26 #include <dev/acpi/amltypes.h> 27 #include <dev/acpi/dsdt.h> 28 29 #define APLGPIO_CONF_TXSTATE 0x00000001 30 #define APLGPIO_CONF_RXSTATE 0x00000002 31 #define APLGPIO_CONF_RXINV 0x00800000 32 #define APLGPIO_CONF_RXEV_EDGE 0x02000000 33 #define APLGPIO_CONF_RXEV_ZERO 0x04000000 34 #define APLGPIO_CONF_RXEV_MASK 0x06000000 35 36 #define APLGPIO_IRQ_STS 0x100 37 #define APLGPIO_IRQ_EN 0x110 38 #define APLGPIO_PAD_CFG0 0x500 39 40 struct aplgpio_intrhand { 41 int (*ih_func)(void *); 42 void *ih_arg; 43 }; 44 45 struct aplgpio_softc { 46 struct device sc_dev; 47 struct acpi_softc *sc_acpi; 48 struct aml_node *sc_node; 49 50 bus_space_tag_t sc_memt; 51 bus_space_handle_t sc_memh; 52 void *sc_ih; 53 54 int sc_npins; 55 struct aplgpio_intrhand *sc_pin_ih; 56 57 struct acpi_gpio sc_gpio; 58 }; 59 60 int aplgpio_match(struct device *, void *, void *); 61 void aplgpio_attach(struct device *, struct device *, void *); 62 63 struct cfattach aplgpio_ca = { 64 sizeof(struct aplgpio_softc), aplgpio_match, aplgpio_attach 65 }; 66 67 struct cfdriver aplgpio_cd = { 68 NULL, "aplgpio", DV_DULL 69 }; 70 71 const char *aplgpio_hids[] = { 72 "INT3452", 73 NULL 74 }; 75 76 int aplgpio_read_pin(void *, int); 77 void aplgpio_write_pin(void *, int, int); 78 void aplgpio_intr_establish(void *, int, int, int (*)(void *), void *); 79 int aplgpio_intr(void *); 80 81 int 82 aplgpio_match(struct device *parent, void *match, void *aux) 83 { 84 struct acpi_attach_args *aaa = aux; 85 struct cfdata *cf = match; 86 87 return acpi_matchhids(aaa, aplgpio_hids, cf->cf_driver->cd_name); 88 } 89 90 void 91 aplgpio_attach(struct device *parent, struct device *self, void *aux) 92 { 93 struct aplgpio_softc *sc = (struct aplgpio_softc *)self; 94 struct acpi_attach_args *aaa = aux; 95 int64_t uid; 96 int i; 97 98 sc->sc_acpi = (struct acpi_softc *)parent; 99 sc->sc_node = aaa->aaa_node; 100 printf(" %s", sc->sc_node->name); 101 102 if (aaa->aaa_naddr < 1) { 103 printf(": no registers\n"); 104 return; 105 } 106 107 if (aaa->aaa_nirq < 1) { 108 printf(": no interrupt\n"); 109 return; 110 } 111 112 if (aml_evalinteger(sc->sc_acpi, sc->sc_node, "_UID", 0, NULL, &uid)) { 113 printf(": can't find uid\n"); 114 return; 115 } 116 117 printf(" uid %lld", uid); 118 119 switch (uid) { 120 case 1: 121 sc->sc_npins = 78; 122 break; 123 case 2: 124 sc->sc_npins = 77; 125 break; 126 case 3: 127 sc->sc_npins = 47; 128 break; 129 case 4: 130 sc->sc_npins = 43; 131 break; 132 default: 133 printf("\n"); 134 return; 135 } 136 137 printf(" addr 0x%llx/0x%llx", aaa->aaa_addr[0], aaa->aaa_size[0]); 138 printf(" irq %d", aaa->aaa_irq[0]); 139 140 sc->sc_memt = aaa->aaa_bst[0]; 141 if (bus_space_map(sc->sc_memt, aaa->aaa_addr[0], aaa->aaa_size[0], 142 0, &sc->sc_memh)) { 143 printf(": can't map registers\n"); 144 return; 145 } 146 147 sc->sc_pin_ih = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_ih), 148 M_DEVBUF, M_WAITOK | M_ZERO); 149 150 sc->sc_ih = acpi_intr_establish(aaa->aaa_irq[0], aaa->aaa_irq_flags[0], 151 IPL_BIO, aplgpio_intr, sc, sc->sc_dev.dv_xname); 152 if (sc->sc_ih == NULL) { 153 printf(": can't establish interrupt\n"); 154 goto unmap; 155 } 156 157 sc->sc_gpio.cookie = sc; 158 sc->sc_gpio.read_pin = aplgpio_read_pin; 159 sc->sc_gpio.write_pin = aplgpio_write_pin; 160 sc->sc_gpio.intr_establish = aplgpio_intr_establish; 161 sc->sc_node->gpio = &sc->sc_gpio; 162 163 /* Mask and clear all interrupts. */ 164 for (i = 0; i < sc->sc_npins; i++) { 165 if (i % 32 == 0) { 166 bus_space_write_4(sc->sc_memt, sc->sc_memh, 167 APLGPIO_IRQ_EN + (i / 32) * 4, 0x00000000); 168 bus_space_write_4(sc->sc_memt, sc->sc_memh, 169 APLGPIO_IRQ_STS + (i / 32) * 4, 0xffffffff); 170 } 171 } 172 173 printf(", %d pins\n", sc->sc_npins); 174 175 acpi_register_gpio(sc->sc_acpi, sc->sc_node); 176 return; 177 178 unmap: 179 free(sc->sc_pin_ih, M_DEVBUF, sc->sc_npins * sizeof(*sc->sc_pin_ih)); 180 bus_space_unmap(sc->sc_memt, sc->sc_memh, aaa->aaa_size[0]); 181 } 182 183 int 184 aplgpio_read_pin(void *cookie, int pin) 185 { 186 struct aplgpio_softc *sc = cookie; 187 uint32_t reg; 188 189 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 190 APLGPIO_PAD_CFG0 + pin * 8); 191 192 return !!(reg & APLGPIO_CONF_RXSTATE); 193 } 194 195 void 196 aplgpio_write_pin(void *cookie, int pin, int value) 197 { 198 struct aplgpio_softc *sc = cookie; 199 uint32_t reg; 200 201 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 202 APLGPIO_PAD_CFG0 + pin * 8); 203 if (value) 204 reg |= APLGPIO_CONF_TXSTATE; 205 else 206 reg &= ~APLGPIO_CONF_TXSTATE; 207 bus_space_write_4(sc->sc_memt, sc->sc_memh, 208 APLGPIO_PAD_CFG0 + pin * 8, reg); 209 } 210 211 void 212 aplgpio_intr_establish(void *cookie, int pin, int flags, 213 int (*func)(void *), void *arg) 214 { 215 struct aplgpio_softc *sc = cookie; 216 uint32_t reg; 217 218 KASSERT(pin >= 0 && pin < sc->sc_npins); 219 220 sc->sc_pin_ih[pin].ih_func = func; 221 sc->sc_pin_ih[pin].ih_arg = arg; 222 223 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 224 APLGPIO_PAD_CFG0 + pin * 8); 225 reg &= ~(APLGPIO_CONF_RXEV_MASK | APLGPIO_CONF_RXINV); 226 if ((flags & LR_GPIO_MODE) == 1) 227 reg |= APLGPIO_CONF_RXEV_EDGE; 228 if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTLO) 229 reg |= APLGPIO_CONF_RXINV; 230 if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTBOTH) 231 reg |= APLGPIO_CONF_RXEV_EDGE | APLGPIO_CONF_RXEV_ZERO; 232 bus_space_write_4(sc->sc_memt, sc->sc_memh, 233 APLGPIO_PAD_CFG0 + pin * 8, reg); 234 235 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 236 APLGPIO_IRQ_EN + (pin / 32) * 4); 237 reg |= (1 << (pin % 32)); 238 bus_space_write_4(sc->sc_memt, sc->sc_memh, 239 APLGPIO_IRQ_EN + (pin / 32) * 4, reg); 240 } 241 242 int 243 aplgpio_intr(void *arg) 244 { 245 struct aplgpio_softc *sc = arg; 246 uint32_t status, enable; 247 int rc = 0; 248 int pin; 249 250 for (pin = 0; pin < sc->sc_npins; pin++) { 251 if (pin % 32 == 0) { 252 status = bus_space_read_4(sc->sc_memt, sc->sc_memh, 253 APLGPIO_IRQ_STS + (pin / 32) * 4); 254 bus_space_write_4(sc->sc_memt, sc->sc_memh, 255 APLGPIO_IRQ_STS + (pin / 32) * 4, status); 256 enable = bus_space_read_4(sc->sc_memt, sc->sc_memh, 257 APLGPIO_IRQ_EN + (pin / 32) * 4); 258 status &= enable; 259 } 260 if (status & (1 << (pin % 32))) { 261 if (sc->sc_pin_ih[pin].ih_func) 262 sc->sc_pin_ih[pin].ih_func(sc->sc_pin_ih[pin].ih_arg); 263 rc = 1; 264 } 265 } 266 return rc; 267 } 268