1 /* $OpenBSD: amdgpio.c,v 1.9 2022/06/27 08:00:31 mlarkin Exp $ */ 2 /* 3 * Copyright (c) 2016 Mark Kettenis 4 * Copyright (c) 2019 James Hastings 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/param.h> 20 #include <sys/malloc.h> 21 #include <sys/systm.h> 22 23 #include <dev/acpi/acpireg.h> 24 #include <dev/acpi/acpivar.h> 25 #include <dev/acpi/acpidev.h> 26 #include <dev/acpi/amltypes.h> 27 #include <dev/acpi/dsdt.h> 28 29 #define AMDGPIO_CONF_LEVEL 0x00000100 30 #define AMDGPIO_CONF_ACTLO 0x00000200 31 #define AMDGPIO_CONF_ACTBOTH 0x00000400 32 #define AMDGPIO_CONF_MASK 0x00000600 33 #define AMDGPIO_CONF_INT_EN 0x00000800 34 #define AMDGPIO_CONF_INT_MASK 0x00001000 35 #define AMDGPIO_CONF_RXSTATE 0x00010000 36 #define AMDGPIO_CONF_TXSTATE 0x00400000 37 #define AMDGPIO_CONF_TXSTATE_EN 0x00800000 38 #define AMDGPIO_CONF_INT_STS 0x10000000 39 #define AMDGPIO_IRQ_MASTER_EOI 0x20000000 40 #define AMDGPIO_IRQ_BITS 46 41 #define AMDGPIO_IRQ_PINS 4 42 43 #define AMDGPIO_IRQ_MASTER 0xfc 44 #define AMDGPIO_IRQ_STS 0x2f8 45 46 struct amdgpio_intrhand { 47 int (*ih_func)(void *); 48 void *ih_arg; 49 }; 50 51 struct amdgpio_pincfg { 52 /* Modeled after pchgpio but we only have one value to save/restore */ 53 uint32_t pin_cfg; 54 }; 55 56 struct amdgpio_softc { 57 struct device sc_dev; 58 struct acpi_softc *sc_acpi; 59 struct aml_node *sc_node; 60 61 bus_space_tag_t sc_memt; 62 bus_space_handle_t sc_memh; 63 int sc_irq_flags; 64 void *sc_ih; 65 66 int sc_npins; 67 struct amdgpio_pincfg *sc_pin_cfg; 68 struct amdgpio_intrhand *sc_pin_ih; 69 70 struct acpi_gpio sc_gpio; 71 }; 72 73 int amdgpio_match(struct device *, void *, void *); 74 void amdgpio_attach(struct device *, struct device *, void *); 75 int amdgpio_activate(struct device *, int); 76 77 const struct cfattach amdgpio_ca = { 78 sizeof(struct amdgpio_softc), amdgpio_match, amdgpio_attach, 79 NULL, amdgpio_activate 80 }; 81 82 struct cfdriver amdgpio_cd = { 83 NULL, "amdgpio", DV_DULL 84 }; 85 86 const char *amdgpio_hids[] = { 87 "AMDI0030", 88 "AMD0030", 89 NULL 90 }; 91 92 int amdgpio_read_pin(void *, int); 93 void amdgpio_write_pin(void *, int, int); 94 void amdgpio_intr_establish(void *, int, int, int (*)(void *), void *); 95 int amdgpio_pin_intr(struct amdgpio_softc *, int); 96 int amdgpio_intr(void *); 97 void amdgpio_save_pin(struct amdgpio_softc *, int pin); 98 void amdgpio_save(struct amdgpio_softc *); 99 void amdgpio_restore_pin(struct amdgpio_softc *, int pin); 100 void amdgpio_restore(struct amdgpio_softc *); 101 102 int 103 amdgpio_match(struct device *parent, void *match, void *aux) 104 { 105 struct acpi_attach_args *aaa = aux; 106 struct cfdata *cf = match; 107 108 if (aaa->aaa_naddr < 1 || aaa->aaa_nirq < 1) 109 return 0; 110 return acpi_matchhids(aaa, amdgpio_hids, cf->cf_driver->cd_name); 111 } 112 113 void 114 amdgpio_attach(struct device *parent, struct device *self, void *aux) 115 { 116 struct acpi_attach_args *aaa = aux; 117 struct amdgpio_softc *sc = (struct amdgpio_softc *)self; 118 int64_t uid; 119 120 sc->sc_acpi = (struct acpi_softc *)parent; 121 sc->sc_node = aaa->aaa_node; 122 printf(" %s", sc->sc_node->name); 123 124 if (aml_evalinteger(sc->sc_acpi, sc->sc_node, "_UID", 0, NULL, &uid)) { 125 printf(": can't find uid\n"); 126 return; 127 } 128 129 printf(" uid %lld", uid); 130 131 switch (uid) { 132 case 0: 133 sc->sc_npins = 184; 134 break; 135 default: 136 printf("\n"); 137 return; 138 } 139 140 printf(" addr 0x%llx/0x%llx", aaa->aaa_addr[0], aaa->aaa_size[0]); 141 printf(" irq %d", aaa->aaa_irq[0]); 142 143 sc->sc_memt = aaa->aaa_bst[0]; 144 if (bus_space_map(sc->sc_memt, aaa->aaa_addr[0], aaa->aaa_size[0], 145 0, &sc->sc_memh)) { 146 printf(": can't map registers\n"); 147 return; 148 } 149 150 sc->sc_pin_cfg = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_cfg), 151 M_DEVBUF, M_WAITOK); 152 sc->sc_pin_ih = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_ih), 153 M_DEVBUF, M_WAITOK | M_ZERO); 154 155 sc->sc_ih = acpi_intr_establish(aaa->aaa_irq[0], aaa->aaa_irq_flags[0], 156 IPL_BIO, amdgpio_intr, sc, sc->sc_dev.dv_xname); 157 if (sc->sc_ih == NULL) { 158 printf(": can't establish interrupt\n"); 159 goto unmap; 160 } 161 162 sc->sc_gpio.cookie = sc; 163 sc->sc_gpio.read_pin = amdgpio_read_pin; 164 sc->sc_gpio.write_pin = amdgpio_write_pin; 165 sc->sc_gpio.intr_establish = amdgpio_intr_establish; 166 sc->sc_node->gpio = &sc->sc_gpio; 167 168 printf(", %d pins\n", sc->sc_npins); 169 170 acpi_register_gpio(sc->sc_acpi, sc->sc_node); 171 return; 172 173 unmap: 174 free(sc->sc_pin_ih, M_DEVBUF, sc->sc_npins * sizeof(*sc->sc_pin_ih)); 175 bus_space_unmap(sc->sc_memt, sc->sc_memh, aaa->aaa_size[0]); 176 } 177 178 int 179 amdgpio_activate(struct device *self, int act) 180 { 181 struct amdgpio_softc *sc = (struct amdgpio_softc *)self; 182 183 switch (act) { 184 case DVACT_SUSPEND: 185 amdgpio_save(sc); 186 break; 187 case DVACT_RESUME: 188 amdgpio_restore(sc); 189 break; 190 } 191 192 return 0; 193 } 194 195 void 196 amdgpio_save_pin(struct amdgpio_softc *sc, int pin) 197 { 198 sc->sc_pin_cfg[pin].pin_cfg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 199 pin * 4); 200 } 201 202 void 203 amdgpio_save(struct amdgpio_softc *sc) 204 { 205 int pin; 206 207 for (pin = 0; pin < sc->sc_npins; pin++) 208 amdgpio_save_pin(sc, pin); 209 } 210 211 void 212 amdgpio_restore_pin(struct amdgpio_softc *sc, int pin) 213 { 214 if (!sc->sc_pin_ih[pin].ih_func) 215 return; 216 217 bus_space_write_4(sc->sc_memt, sc->sc_memh, pin * 4, 218 sc->sc_pin_cfg[pin].pin_cfg); 219 } 220 221 void 222 amdgpio_restore(struct amdgpio_softc *sc) 223 { 224 int pin; 225 226 for (pin = 0; pin < sc->sc_npins; pin++) 227 amdgpio_restore_pin(sc, pin); 228 } 229 230 int 231 amdgpio_read_pin(void *cookie, int pin) 232 { 233 struct amdgpio_softc *sc = cookie; 234 uint32_t reg; 235 236 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, pin * 4); 237 238 return !!(reg & AMDGPIO_CONF_RXSTATE); 239 } 240 241 void 242 amdgpio_write_pin(void *cookie, int pin, int value) 243 { 244 struct amdgpio_softc *sc = cookie; 245 uint32_t reg; 246 247 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, pin * 4); 248 reg |= AMDGPIO_CONF_TXSTATE_EN; 249 if (value) 250 reg |= AMDGPIO_CONF_TXSTATE; 251 else 252 reg &= ~AMDGPIO_CONF_TXSTATE; 253 bus_space_write_4(sc->sc_memt, sc->sc_memh, pin * 4, reg); 254 } 255 256 void 257 amdgpio_intr_establish(void *cookie, int pin, int flags, 258 int (*func)(void *), void *arg) 259 { 260 struct amdgpio_softc *sc = cookie; 261 uint32_t reg; 262 263 KASSERT(pin >= 0 && pin != 63 && pin < sc->sc_npins); 264 265 sc->sc_pin_ih[pin].ih_func = func; 266 sc->sc_pin_ih[pin].ih_arg = arg; 267 268 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, pin * 4); 269 reg &= ~(AMDGPIO_CONF_MASK | AMDGPIO_CONF_LEVEL | 270 AMDGPIO_CONF_TXSTATE_EN); 271 if ((flags & LR_GPIO_MODE) == 0) 272 reg |= AMDGPIO_CONF_LEVEL; 273 if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTLO) 274 reg |= AMDGPIO_CONF_ACTLO; 275 if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTBOTH) 276 reg |= AMDGPIO_CONF_ACTBOTH; 277 reg |= (AMDGPIO_CONF_INT_MASK | AMDGPIO_CONF_INT_EN); 278 bus_space_write_4(sc->sc_memt, sc->sc_memh, pin * 4, reg); 279 } 280 281 int 282 amdgpio_pin_intr(struct amdgpio_softc *sc, int pin) 283 { 284 uint32_t reg; 285 int rc = 0; 286 287 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, pin * 4); 288 if (reg & AMDGPIO_CONF_INT_STS) { 289 if (sc->sc_pin_ih[pin].ih_func) { 290 sc->sc_pin_ih[pin].ih_func(sc->sc_pin_ih[pin].ih_arg); 291 292 /* Clear interrupt */ 293 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 294 pin * 4); 295 bus_space_write_4(sc->sc_memt, sc->sc_memh, 296 pin * 4, reg); 297 rc = 1; 298 } else { 299 /* Mask unhandled interrupt */ 300 reg &= ~(AMDGPIO_CONF_INT_MASK | AMDGPIO_CONF_INT_EN); 301 bus_space_write_4(sc->sc_memt, sc->sc_memh, 302 pin * 4, reg); 303 } 304 } 305 306 return rc; 307 } 308 309 int 310 amdgpio_intr(void *arg) 311 { 312 struct amdgpio_softc *sc = arg; 313 uint64_t status; 314 uint32_t reg; 315 int rc = 0, pin = 0; 316 int i, j; 317 318 status = bus_space_read_4(sc->sc_memt, sc->sc_memh, 319 AMDGPIO_IRQ_STS + 4); 320 status <<= 32; 321 status |= bus_space_read_4(sc->sc_memt, sc->sc_memh, 322 AMDGPIO_IRQ_STS); 323 324 /* One status bit for every four pins */ 325 for (i = 0; i < AMDGPIO_IRQ_BITS; i++, pin += 4) { 326 if (status & (1ULL << i)) { 327 for (j = 0; j < AMDGPIO_IRQ_PINS; j++) { 328 if (amdgpio_pin_intr(sc, pin + j)) 329 rc = 1; 330 } 331 } 332 } 333 334 /* Signal end of interrupt */ 335 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 336 AMDGPIO_IRQ_MASTER); 337 reg |= AMDGPIO_IRQ_MASTER_EOI; 338 bus_space_write_4(sc->sc_memt, sc->sc_memh, 339 AMDGPIO_IRQ_MASTER, reg); 340 341 return rc; 342 } 343