1 /* $OpenBSD: acpireg.h,v 1.55 2021/03/23 09:41:12 patrick Exp $ */ 2 /* 3 * Copyright (c) 2005 Thorsten Lockert <tholo@sigmasoft.com> 4 * Copyright (c) 2005 Marco Peereboom <marco@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DEV_ACPI_ACPIREG_H_ 20 #define _DEV_ACPI_ACPIREG_H_ 21 22 /* Root System Descriptor Pointer */ 23 struct acpi_rsdp1 { 24 uint8_t signature[8]; 25 #define RSDP_SIG "RSD PTR " 26 #define rsdp_signaturee rsdp1.signature 27 uint8_t checksum; /* make sum == 0 */ 28 #define rsdp_checksum rsdp1.checksum 29 uint8_t oemid[6]; 30 #define rsdp_oemid rsdp1.oemid 31 uint8_t revision; /* 0 for 1, 2 for 2 */ 32 #define rsdp_revision rsdp1.revision 33 uint32_t rsdt; /* physical */ 34 #define rsdp_rsdt rsdp1.rsdt 35 } __packed; 36 37 struct acpi_rsdp { 38 struct acpi_rsdp1 rsdp1; 39 /* 40 * The following values are only valid 41 * when rsdp_revision == 2 42 */ 43 uint32_t rsdp_length; /* length of rsdp */ 44 uint64_t rsdp_xsdt; /* physical */ 45 uint8_t rsdp_extchecksum; /* entire table */ 46 uint8_t rsdp_reserved[3]; /* must be zero */ 47 } __packed; 48 49 struct acpi_table_header { 50 uint8_t signature[4]; 51 #define hdr_signature hdr.signature 52 uint32_t length; 53 #define hdr_length hdr.length 54 uint8_t revision; 55 #define hdr_revision hdr.revision 56 uint8_t checksum; 57 #define hdr_checksum hdr.checksum 58 uint8_t oemid[6]; 59 #define hdr_oemid hdr.oemid 60 uint8_t oemtableid[8]; 61 #define hdr_oemtableid hdr.oemtableid 62 uint32_t oemrevision; 63 #define hdr_oemrevision hdr.oemrevision 64 uint8_t aslcompilerid[4]; 65 #define hdr_aslcompilerid hdr.aslcompilerid 66 uint32_t aslcompilerrevision; 67 #define hdr_aslcompilerrevision hdr.aslcompilerrevision 68 } __packed; 69 70 struct acpi_rsdt { 71 struct acpi_table_header hdr; 72 #define RSDT_SIG "RSDT" 73 uint32_t table_offsets[1]; 74 } __packed; 75 76 struct acpi_xsdt { 77 struct acpi_table_header hdr; 78 #define XSDT_SIG "XSDT" 79 uint64_t table_offsets[1]; 80 } __packed; 81 82 struct acpi_gas { 83 uint8_t address_space_id; 84 #define GAS_SYSTEM_MEMORY 0 85 #define GAS_SYSTEM_IOSPACE 1 86 #define GAS_PCI_CFG_SPACE 2 87 #define GAS_EMBEDDED 3 88 #define GAS_SMBUS 4 89 #define GAS_FUNCTIONAL_FIXED 127 90 uint8_t register_bit_width; 91 uint8_t register_bit_offset; 92 uint8_t access_size; 93 #define GAS_ACCESS_UNDEFINED 0 94 #define GAS_ACCESS_BYTE 1 95 #define GAS_ACCESS_WORD 2 96 #define GAS_ACCESS_DWORD 3 97 #define GAS_ACCESS_QWORD 4 98 uint64_t address; 99 } __packed; 100 101 struct acpi_fadt { 102 struct acpi_table_header hdr; 103 #define FADT_SIG "FACP" 104 uint32_t firmware_ctl; /* phys addr FACS */ 105 uint32_t dsdt; /* phys addr DSDT */ 106 uint8_t int_model; /* interrupt model (hdr_revision < 3) */ 107 #define FADT_INT_DUAL_PIC 0 108 #define FADT_INT_MULTI_APIC 1 109 uint8_t pm_profile; /* power mgmt profile */ 110 #define FADT_PM_UNSPEC 0 111 #define FADT_PM_DESKTOP 1 112 #define FADT_PM_MOBILE 2 113 #define FADT_PM_WORKSTATION 3 114 #define FADT_PM_ENT_SERVER 4 115 #define FADT_PM_SOHO_SERVER 5 116 #define FADT_PM_APPLIANCE 6 117 #define FADT_PM_PERF_SERVER 7 118 uint16_t sci_int; /* SCI interrupt */ 119 uint32_t smi_cmd; /* SMI command port */ 120 uint8_t acpi_enable; /* value to enable */ 121 uint8_t acpi_disable; /* value to disable */ 122 uint8_t s4bios_req; /* value for S4 */ 123 uint8_t pstate_cnt; /* value for performance (hdr_revision > 2) */ 124 uint32_t pm1a_evt_blk; /* power management 1a */ 125 uint32_t pm1b_evt_blk; /* power mangement 1b */ 126 uint32_t pm1a_cnt_blk; /* pm control 1a */ 127 uint32_t pm1b_cnt_blk; /* pm control 1b */ 128 uint32_t pm2_cnt_blk; /* pm control 2 */ 129 uint32_t pm_tmr_blk; 130 uint32_t gpe0_blk; 131 uint32_t gpe1_blk; 132 uint8_t pm1_evt_len; 133 uint8_t pm1_cnt_len; 134 uint8_t pm2_cnt_len; 135 uint8_t pm_tmr_len; 136 uint8_t gpe0_blk_len; 137 uint8_t gpe1_blk_len; 138 uint8_t gpe1_base; 139 uint8_t cst_cnt; /* (hdr_revision > 2) */ 140 uint16_t p_lvl2_lat; 141 uint16_t p_lvl3_lat; 142 uint16_t flush_size; 143 uint16_t flush_stride; 144 uint8_t duty_offset; 145 uint8_t duty_width; 146 uint8_t day_alrm; 147 uint8_t mon_alrm; 148 uint8_t century; 149 uint16_t iapc_boot_arch; /* (hdr_revision > 2) */ 150 #define FADT_LEGACY_DEVICES 0x0001 /* Legacy devices supported */ 151 #define FADT_i8042 0x0002 /* Keyboard controller present */ 152 #define FADT_NO_VGA 0x0004 /* Do not probe VGA */ 153 #define FADT_NO_MSI 0x0008 /* Do not enable MSI */ 154 uint8_t reserved1; 155 uint32_t flags; 156 #define FADT_WBINVD 0x00000001 157 #define FADT_WBINVD_FLUSH 0x00000002 158 #define FADT_PROC_C1 0x00000004 159 #define FADT_P_LVL2_UP 0x00000008 160 #define FADT_PWR_BUTTON 0x00000010 161 #define FADT_SLP_BUTTON 0x00000020 162 #define FADT_FIX_RTC 0x00000040 163 #define FADT_RTC_S4 0x00000080 164 #define FADT_TMR_VAL_EXT 0x00000100 165 #define FADT_DCK_CAP 0x00000200 166 #define FADT_RESET_REG_SUP 0x00000400 167 #define FADT_SEALED_CASE 0x00000800 168 #define FADT_HEADLESS 0x00001000 169 #define FADT_CPU_SW_SLP 0x00002000 170 #define FADT_PCI_EXP_WAK 0x00004000 171 #define FADT_USE_PLATFORM_CLOCK 0x00008000 172 #define FADT_S4_RTC_STS_VALID 0x00010000 173 #define FADT_REMOTE_POWER_ON_CAPABLE 0x00020000 174 #define FADT_FORCE_APIC_CLUSTER_MODEL 0x00040000 175 #define FADT_FORCE_APIC_PHYS_DEST_MODE 0x00080000 176 #define FADT_HW_REDUCED_ACPI 0x00100000 177 #define FADT_POWER_S0_IDLE_CAPABLE 0x00200000 178 /* 179 * Following values only exist when rev > 1 180 * If the extended addresses exists, they 181 * must be used in preferense to the non- 182 * extended values above 183 */ 184 struct acpi_gas reset_reg; 185 uint8_t reset_value; 186 uint8_t reserved2a; 187 uint8_t reserved2b; 188 uint8_t fadt_minor; 189 uint64_t x_firmware_ctl; 190 uint64_t x_dsdt; 191 struct acpi_gas x_pm1a_evt_blk; 192 struct acpi_gas x_pm1b_evt_blk; 193 struct acpi_gas x_pm1a_cnt_blk; 194 struct acpi_gas x_pm1b_cnt_blk; 195 struct acpi_gas x_pm2_cnt_blk; 196 struct acpi_gas x_pm_tmr_blk; 197 struct acpi_gas x_gpe0_blk; 198 struct acpi_gas x_gpe1_blk; 199 struct acpi_gas sleep_control_reg; 200 struct acpi_gas sleep_status_reg; 201 } __packed; 202 203 struct acpi_dsdt { 204 struct acpi_table_header hdr; 205 #define DSDT_SIG "DSDT" 206 uint8_t aml[1]; 207 } __packed; 208 209 struct acpi_ssdt { 210 struct acpi_table_header hdr; 211 #define SSDT_SIG "SSDT" 212 uint8_t aml[1]; 213 } __packed; 214 215 /* 216 * Table deprecated by ACPI 2.0 217 */ 218 struct acpi_psdt { 219 struct acpi_table_header hdr; 220 #define PSDT_SIG "PSDT" 221 } __packed; 222 223 struct acpi_madt { 224 struct acpi_table_header hdr; 225 #define MADT_SIG "APIC" 226 uint32_t local_apic_address; 227 uint32_t flags; 228 #define ACPI_APIC_PCAT_COMPAT 0x00000001 229 } __packed; 230 231 struct acpi_madt_lapic { 232 uint8_t apic_type; 233 #define ACPI_MADT_LAPIC 0 234 uint8_t length; 235 uint8_t acpi_proc_id; 236 uint8_t apic_id; 237 uint32_t flags; 238 #define ACPI_PROC_ENABLE 0x00000001 239 } __packed; 240 241 struct acpi_madt_ioapic { 242 uint8_t apic_type; 243 #define ACPI_MADT_IOAPIC 1 244 uint8_t length; 245 uint8_t acpi_ioapic_id; 246 uint8_t reserved; 247 uint32_t address; 248 uint32_t global_int_base; 249 } __packed; 250 251 struct acpi_madt_override { 252 uint8_t apic_type; 253 #define ACPI_MADT_OVERRIDE 2 254 uint8_t length; 255 uint8_t bus; 256 #define ACPI_OVERRIDE_BUS_ISA 0 257 uint8_t source; 258 uint32_t global_int; 259 uint16_t flags; 260 #define ACPI_OVERRIDE_POLARITY_BITS 0x3 261 #define ACPI_OVERRIDE_POLARITY_BUS 0x0 262 #define ACPI_OVERRIDE_POLARITY_HIGH 0x1 263 #define ACPI_OVERRIDE_POLARITY_LOW 0x3 264 #define ACPI_OVERRIDE_TRIGGER_BITS 0xc 265 #define ACPI_OVERRIDE_TRIGGER_BUS 0x0 266 #define ACPI_OVERRIDE_TRIGGER_EDGE 0x4 267 #define ACPI_OVERRIDE_TRIGGER_LEVEL 0xc 268 } __packed; 269 270 struct acpi_madt_nmi { 271 uint8_t apic_type; 272 #define ACPI_MADT_NMI 3 273 uint8_t length; 274 uint16_t flags; /* Same flags as acpi_madt_override */ 275 uint32_t global_int; 276 } __packed; 277 278 struct acpi_madt_lapic_nmi { 279 uint8_t apic_type; 280 #define ACPI_MADT_LAPIC_NMI 4 281 uint8_t length; 282 uint8_t acpi_proc_id; 283 uint16_t flags; /* Same flags as acpi_madt_override */ 284 uint8_t local_apic_lint; 285 } __packed; 286 287 struct acpi_madt_lapic_override { 288 uint8_t apic_type; 289 #define ACPI_MADT_LAPIC_OVERRIDE 5 290 uint8_t length; 291 uint16_t reserved; 292 uint64_t lapic_address; 293 } __packed; 294 295 struct acpi_madt_io_sapic { 296 uint8_t apic_type; 297 #define ACPI_MADT_IO_SAPIC 6 298 uint8_t length; 299 uint8_t iosapic_id; 300 uint8_t reserved; 301 uint32_t global_int_base; 302 uint64_t iosapic_address; 303 } __packed; 304 305 struct acpi_madt_local_sapic { 306 uint8_t apic_type; 307 #define ACPI_MADT_LOCAL_SAPIC 7 308 uint8_t length; 309 uint8_t acpi_proc_id; 310 uint8_t local_sapic_id; 311 uint8_t local_sapic_eid; 312 uint8_t reserved[3]; 313 uint32_t flags; /* Same flags as acpi_madt_lapic */ 314 uint32_t acpi_proc_uid; 315 uint8_t acpi_proc_uid_string[1]; 316 } __packed; 317 318 struct acpi_madt_platform_int { 319 uint8_t apic_type; 320 #define ACPI_MADT_PLATFORM_INT 8 321 uint8_t length; 322 uint16_t flags; /* Same flags as acpi_madt_override */ 323 uint8_t int_type; 324 #define ACPI_MADT_PLATFORM_PMI 1 325 #define ACPI_MADT_PLATFORM_INIT 2 326 #define ACPI_MADT_PLATFORM_CORR_ERROR 3 327 uint8_t proc_id; 328 uint8_t proc_eid; 329 uint8_t io_sapic_vec; 330 uint32_t global_int; 331 uint32_t platform_int_flags; 332 #define ACPI_MADT_PLATFORM_CPEI 0x00000001 333 } __packed; 334 335 struct acpi_madt_x2apic { 336 uint8_t apic_type; 337 #define ACPI_MADT_X2APIC 9 338 uint8_t length; 339 uint8_t reserved[2]; 340 uint32_t apic_id; 341 uint32_t flags; /* Same flags as acpi_madt_lapic */ 342 uint32_t acpi_proc_uid; 343 } __packed; 344 345 struct acpi_madt_x2apic_nmi { 346 uint8_t apic_type; 347 #define ACPI_MADT_X2APIC_NMI 10 348 uint8_t length; 349 uint16_t flags; /* Same flags as acpi_madt_override */ 350 uint32_t apic_proc_uid; 351 uint8_t local_x2apic_lint; 352 uint8_t reserved[3]; 353 } __packed; 354 355 union acpi_madt_entry { 356 struct acpi_madt_lapic madt_lapic; 357 struct acpi_madt_ioapic madt_ioapic; 358 struct acpi_madt_override madt_override; 359 struct acpi_madt_nmi madt_nmi; 360 struct acpi_madt_lapic_nmi madt_lapic_nmi; 361 struct acpi_madt_lapic_override madt_lapic_override; 362 struct acpi_madt_io_sapic madt_io_sapic; 363 struct acpi_madt_local_sapic madt_local_sapic; 364 struct acpi_madt_platform_int madt_platform_int; 365 struct acpi_madt_x2apic madt_x2apic; 366 struct acpi_madt_x2apic_nmi madt_x2apic_nmi; 367 } __packed; 368 369 struct acpi_sbst { 370 struct acpi_table_header hdr; 371 #define SBST_SIG "SBST" 372 uint32_t warning_energy_level; 373 uint32_t low_energy_level; 374 uint32_t critical_energy_level; 375 } __packed; 376 377 struct acpi_ecdt { 378 struct acpi_table_header hdr; 379 #define ECDT_SIG "ECDT" 380 struct acpi_gas ec_control; 381 struct acpi_gas ec_data; 382 uint32_t uid; 383 uint8_t gpe_bit; 384 uint8_t ec_id[1]; 385 } __packed; 386 387 struct acpi_srat { 388 struct acpi_table_header hdr; 389 #define SRAT_SIG "SRAT" 390 uint32_t reserved1; 391 uint64_t reserved2; 392 } __packed; 393 394 struct acpi_slit { 395 struct acpi_table_header hdr; 396 #define SLIT_SIG "SLIT" 397 uint64_t number_of_localities; 398 } __packed; 399 400 struct acpi_hpet { 401 struct acpi_table_header hdr; 402 #define HPET_SIG "HPET" 403 uint32_t event_timer_block_id; 404 struct acpi_gas base_address; 405 uint8_t hpet_number; 406 uint16_t main_counter_min_clock_tick; 407 uint8_t page_protection; 408 } __packed; 409 410 struct acpi_mcfg { 411 struct acpi_table_header hdr; 412 #define MCFG_SIG "MCFG" 413 uint8_t reserved[8]; 414 } __packed; 415 416 struct acpi_mcfg_entry { 417 uint64_t base_address; 418 uint16_t segment; 419 uint8_t min_bus_number; 420 uint8_t max_bus_number; 421 uint32_t reserved1; 422 } __packed; 423 424 struct acpi_spcr { 425 struct acpi_table_header hdr; 426 #define SPCR_SIG "SPCR" 427 uint8_t interface_type; 428 #define SPCR_16550 0 429 #define SPCR_16450 1 430 #define SPCR_ARM_PL011 3 431 #define SPCR_ARM_SBSA 14 432 uint8_t reserved1[3]; 433 struct acpi_gas base_address; 434 uint8_t interrupt_type; 435 uint8_t irq; 436 uint32_t gsiv; 437 uint8_t baud_rate; 438 uint8_t parity; 439 uint8_t stop_bits; 440 uint8_t flow_control; 441 uint8_t terminal_type; 442 uint8_t reserved2; 443 uint16_t pci_device_id; 444 uint16_t pci_vendor_id; 445 uint8_t pci_bus; 446 uint8_t pci_device; 447 uint8_t pci_function; 448 uint32_t pci_flags; 449 uint8_t pci_segment; 450 uint32_t reserved3; 451 } __packed; 452 453 struct acpi_facs { 454 uint8_t signature[4]; 455 #define FACS_SIG "FACS" 456 uint32_t length; 457 uint32_t hardware_signature; 458 uint32_t wakeup_vector; 459 uint32_t global_lock; 460 #define FACS_LOCK_PENDING 0x00000001 461 #define FACS_LOCK_OWNED 0x00000002 462 uint32_t flags; 463 #define FACS_S4BIOS_F 0x00000001 /* S4BIOS_REQ supported */ 464 uint64_t x_wakeup_vector; 465 uint8_t version; 466 uint8_t reserved[31]; 467 } __packed; 468 469 /* 470 * Intel ACPI DMA Remapping Entries 471 */ 472 struct acpidmar_devpath { 473 uint8_t device; 474 uint8_t function; 475 } __packed; 476 477 struct acpidmar_devscope { 478 uint8_t type; 479 #define DMAR_ENDPOINT 0x1 480 #define DMAR_BRIDGE 0x2 481 #define DMAR_IOAPIC 0x3 482 #define DMAR_HPET 0x4 483 uint8_t length; 484 uint16_t reserved; 485 uint8_t enumid; 486 uint8_t bus; 487 } __packed; 488 489 /* DMA Remapping Hardware Unit */ 490 struct acpidmar_drhd { 491 uint16_t type; 492 uint16_t length; 493 494 uint8_t flags; 495 uint8_t reserved; 496 uint16_t segment; 497 uint64_t address; 498 /* struct acpidmar_devscope[]; */ 499 } __packed; 500 501 /* Reserved Memory Region Reporting */ 502 struct acpidmar_rmrr { 503 uint16_t type; 504 uint16_t length; 505 506 uint16_t reserved; 507 uint16_t segment; 508 uint64_t base; 509 uint64_t limit; 510 /* struct acpidmar_devscope[]; */ 511 } __packed; 512 513 /* Root Port ATS Capability Reporting */ 514 struct acpidmar_atsr { 515 uint16_t type; 516 uint16_t length; 517 518 uint8_t flags; 519 uint8_t reserved; 520 uint16_t segment; 521 /* struct acpidmar_devscope[]; */ 522 } __packed; 523 524 union acpidmar_entry { 525 struct { 526 uint16_t type; 527 #define DMAR_DRHD 0x0 528 #define DMAR_RMRR 0x1 529 #define DMAR_ATSR 0x2 530 #define DMAR_RHSA 0x3 531 uint16_t length; 532 } __packed; 533 struct acpidmar_drhd drhd; 534 struct acpidmar_rmrr rmrr; 535 struct acpidmar_atsr atsr; 536 } __packed; 537 538 struct acpi_dmar { 539 struct acpi_table_header hdr; 540 #define DMAR_SIG "DMAR" 541 uint8_t haw; 542 uint8_t flags; 543 uint8_t reserved[10]; 544 /* struct acpidmar_entry[]; */ 545 } __packed; 546 547 /* 548 * AMD I/O Virtualization Remapping Entries 549 */ 550 union acpi_ivhd_entry { 551 uint8_t type; 552 #define IVHD_ALL 1 553 #define IVHD_SEL 2 554 #define IVHD_SOR 3 555 #define IVHD_EOR 4 556 #define IVHD_ALIAS_SEL 66 557 #define IVHD_ALIAS_SOR 67 558 #define IVHD_EXT_SEL 70 559 #define IVHD_EXT_SOR 71 560 #define IVHD_SPECIAL 72 561 struct { 562 uint8_t type; 563 uint16_t resvd; 564 uint8_t data; 565 } __packed all; 566 struct { 567 uint8_t type; 568 uint16_t devid; 569 uint8_t data; 570 } __packed sel; 571 struct { 572 uint8_t type; 573 uint16_t devid; 574 uint8_t data; 575 } __packed sor; 576 struct { 577 uint8_t type; 578 uint16_t devid; 579 uint8_t resvd; 580 } __packed eor; 581 struct { 582 uint8_t type; 583 uint16_t devid; 584 uint8_t data; 585 uint8_t resvd1; 586 uint16_t srcid; 587 uint8_t resvd2; 588 } __packed alias; 589 struct { 590 uint8_t type; 591 uint16_t devid; 592 uint8_t data; 593 uint32_t extdata; 594 #define IVHD_ATS_DIS (1L << 31) 595 } __packed ext; 596 struct { 597 uint8_t type; 598 uint16_t resvd; 599 uint8_t data; 600 uint8_t handle; 601 uint16_t devid; 602 uint8_t variety; 603 #define IVHD_IOAPIC 0x01 604 #define IVHD_HPET 0x02 605 } __packed special; 606 } __packed; 607 608 struct acpi_ivmd { 609 uint8_t type; 610 uint8_t flags; 611 #define IVMD_EXCLRANGE (1L << 3) 612 #define IVMD_IW (1L << 2) 613 #define IVMD_IR (1L << 1) 614 #define IVMD_UNITY (1L << 0) 615 uint16_t length; 616 uint16_t devid; 617 uint16_t auxdata; 618 uint8_t reserved[8]; 619 uint64_t base; 620 uint64_t limit; 621 } __packed; 622 623 struct acpi_ivhd { 624 uint8_t type; 625 uint8_t flags; 626 #define IVHD_PPRSUP (1L << 7) 627 #define IVHD_PREFSUP (1L << 6) 628 #define IVHD_COHERENT (1L << 5) 629 #define IVHD_IOTLB (1L << 4) 630 #define IVHD_ISOC (1L << 3) 631 #define IVHD_RESPASSPW (1L << 2) 632 #define IVHD_PASSPW (1L << 1) 633 #define IVHD_HTTUNEN (1L << 0) 634 uint16_t length; 635 uint16_t devid; 636 uint16_t cap; 637 uint64_t address; 638 uint16_t segment; 639 uint16_t info; 640 #define IVHD_UNITID_SHIFT 8 641 #define IVHD_UNITID_MASK 0x1F 642 #define IVHD_MSINUM_SHIFT 0 643 #define IVHD_MSINUM_MASK 0x1F 644 uint32_t feature; 645 } __packed; 646 647 struct acpi_ivhd_ext { 648 uint8_t type; 649 uint8_t flags; 650 uint16_t length; 651 uint16_t devid; 652 uint16_t cap; 653 uint64_t address; 654 uint16_t segment; 655 uint16_t info; 656 uint32_t attrib; 657 uint64_t efr; 658 uint8_t reserved[8]; 659 } __packed; 660 661 union acpi_ivrs_entry { 662 struct { 663 uint8_t type; 664 #define IVRS_IVHD 0x10 665 #define IVRS_IVHD_EXT 0x11 666 #define IVRS_IVMD_ALL 0x20 667 #define IVRS_IVMD_SPECIFIED 0x21 668 #define IVRS_IVMD_RANGE 0x22 669 uint8_t flags; 670 uint16_t length; 671 } __packed; 672 struct acpi_ivhd ivhd; 673 struct acpi_ivhd_ext ivhd_ext; 674 struct acpi_ivmd ivmd; 675 } __packed; 676 677 struct acpi_ivrs { 678 struct acpi_table_header hdr; 679 #define IVRS_SIG "IVRS" 680 uint32_t ivinfo; 681 #define IVRS_ATSRNG (1L << 22) 682 #define IVRS_VASIZE_SHIFT 15 683 #define IVRS_VASIZE_MASK 0x7F 684 #define IVRS_PASIZE_SHIFT 8 685 #define IVRS_PASIZE_MASK 0x7F 686 uint8_t reserved[8]; 687 } __packed; 688 689 struct acpi_iort { 690 struct acpi_table_header hdr; 691 #define IORT_SIG "IORT" 692 uint32_t number_of_nodes; 693 uint32_t offset; 694 uint32_t reserved; 695 } __packed; 696 697 struct acpi_iort_node { 698 uint8_t type; 699 #define ACPI_IORT_ITS 0 700 #define ACPI_IORT_NAMED_COMPONENT 1 701 #define ACPI_IORT_ROOT_COMPLEX 2 702 #define ACPI_IORT_SMMU 3 703 #define ACPI_IORT_SMMU_V3 4 704 uint16_t length; 705 uint8_t revision; 706 uint32_t reserved1; 707 uint32_t number_of_mappings; 708 uint32_t mapping_offset; 709 } __packed; 710 711 struct acpi_iort_nc_node { 712 uint32_t node_flags; 713 uint64_t memory_access_properties; 714 uint8_t device_memory_address_size_limit; 715 char device_object_name[]; 716 } __packed; 717 718 struct acpi_iort_rc_node { 719 uint64_t memory_access_properties; 720 uint32_t ats_attributes; 721 uint32_t segment; 722 uint8_t memory_address_size_limit; 723 uint8_t reserved2[3]; 724 } __packed; 725 726 struct acpi_iort_smmu_node { 727 uint64_t base_address; 728 uint64_t span; 729 uint32_t model; 730 #define ACPI_IORT_SMMU_V1 0 731 #define ACPI_IORT_SMMU_V2 1 732 #define ACPI_IORT_SMMU_CORELINK_MMU400 2 733 #define ACPI_IORT_SMMU_CORELINK_MMU500 3 734 #define ACPI_IORT_SMMU_CORELINK_MMU401 4 735 #define ACPI_IORT_SMMU_CAVIUM_THUNDERX 5 736 uint32_t flags; 737 #define ACPI_IORT_SMMU_DVM 0x00000001 738 #define ACPI_IORT_SMMU_COHERENT 0x00000002 739 uint32_t global_interrupt_offset; 740 uint32_t number_of_context_interrupts; 741 uint32_t context_interrupt_offset; 742 uint32_t number_of_pmu_interrupts; 743 uint32_t pmu_interrupt_offset; 744 } __packed; 745 746 struct acpi_iort_smmu_global_interrupt { 747 uint32_t nsgirpt_gsiv; 748 uint32_t nsgirpt_flags; 749 #define ACPI_IORT_SMMU_INTR_EDGE (1 << 0) 750 uint32_t nscfgirpt_gsiv; 751 uint32_t nscfgirpt_flags; 752 } __packed; 753 754 struct acpi_iort_smmu_context_interrupt { 755 uint32_t gsiv; 756 uint32_t flags; 757 } __packed; 758 759 struct acpi_iort_smmu_pmu_interrupt { 760 uint32_t gsiv; 761 uint32_t flags; 762 } __packed; 763 764 struct acpi_iort_mapping { 765 uint32_t input_base; 766 uint32_t number_of_ids; 767 uint32_t output_base; 768 uint32_t output_reference; 769 uint32_t flags; 770 #define ACPI_IORT_MAPPING_SINGLE 0x00000001 771 } __packed; 772 773 #define ACPI_FREQUENCY 3579545 /* Per ACPI spec */ 774 775 /* 776 * PCI Configuration space 777 */ 778 #define ACPI_ADR_PCIDEV(addr) (uint16_t)(addr >> 16) 779 #define ACPI_ADR_PCIFUN(addr) (uint16_t)(addr & 0xFFFF) 780 781 #define ACPI_PCI_SEG(addr) (uint16_t)((addr) >> 48) 782 #define ACPI_PCI_BUS(addr) (uint8_t)((addr) >> 40) 783 #define ACPI_PCI_DEV(addr) (uint8_t)((addr) >> 32) 784 #define ACPI_PCI_FN(addr) (uint16_t)((addr) >> 16) 785 #define ACPI_PCI_REG(addr) (uint16_t)(addr) 786 787 /* 788 * PM1 Status Registers Fixed Hardware Feature Status Bits 789 */ 790 #define ACPI_PM1_STATUS 0x00 791 #define ACPI_PM1_TMR_STS 0x0001 792 #define ACPI_PM1_BM_STS 0x0010 793 #define ACPI_PM1_GBL_STS 0x0020 794 #define ACPI_PM1_PWRBTN_STS 0x0100 795 #define ACPI_PM1_SLPBTN_STS 0x0200 796 #define ACPI_PM1_RTC_STS 0x0400 797 #define ACPI_PM1_PCIEXP_WAKE_STS 0x4000 798 #define ACPI_PM1_WAK_STS 0x8000 799 800 #define ACPI_PM1_ALL_STS (ACPI_PM1_TMR_STS | ACPI_PM1_BM_STS | \ 801 ACPI_PM1_GBL_STS | ACPI_PM1_PWRBTN_STS | \ 802 ACPI_PM1_SLPBTN_STS | ACPI_PM1_RTC_STS | \ 803 ACPI_PM1_PCIEXP_WAKE_STS | ACPI_PM1_WAK_STS ) 804 805 /* 806 * PM1 Enable Registers 807 */ 808 #define ACPI_PM1_ENABLE 0x02 809 #define ACPI_PM1_TMR_EN 0x0001 810 #define ACPI_PM1_GBL_EN 0x0020 811 #define ACPI_PM1_PWRBTN_EN 0x0100 812 #define ACPI_PM1_SLPBTN_EN 0x0200 813 #define ACPI_PM1_RTC_EN 0x0400 814 #define ACPI_PM1_PCIEXP_WAKE_DIS 0x4000 815 816 /* 817 * PM1 Control Registers 818 */ 819 #define ACPI_PM1_CONTROL 0x00 820 #define ACPI_PM1_SCI_EN 0x0001 821 #define ACPI_PM1_BM_RLD 0x0002 822 #define ACPI_PM1_GBL_RLS 0x0004 823 #define ACPI_PM1_SLP_TYPX(x) ((x) << 10) 824 #define ACPI_PM1_SLP_TYPX_MASK 0x1c00 825 #define ACPI_PM1_SLP_EN 0x2000 826 827 /* 828 * PM2 Control Registers 829 */ 830 #define ACPI_PM2_CONTROL 0x06 831 #define ACPI_PM2_ARB_DIS 0x0001 832 833 /* 834 * Operation Region Address Space Identifiers 835 */ 836 #define ACPI_OPREG_SYSMEM 0 /* SystemMemory */ 837 #define ACPI_OPREG_SYSIO 1 /* SystemIO */ 838 #define ACPI_OPREG_PCICFG 2 /* PCI_Config */ 839 #define ACPI_OPREG_EC 3 /* EmbeddedControl */ 840 #define ACPI_OPREG_SMBUS 4 /* SMBus */ 841 #define ACPI_OPREG_CMOS 5 /* CMOS */ 842 #define ACPI_OPREG_PCIBAR 6 /* PCIBARTarget */ 843 #define ACPI_OPREG_IPMI 7 /* IPMI */ 844 #define ACPI_OPREG_GPIO 8 /* GeneralPurposeIO */ 845 #define ACPI_OPREG_GSB 9 /* GenericSerialBus */ 846 847 /* 848 * Sleeping States 849 */ 850 #define ACPI_STATE_S0 0 851 #define ACPI_STATE_S1 1 852 #define ACPI_STATE_S2 2 853 #define ACPI_STATE_S3 3 854 #define ACPI_STATE_S4 4 855 #define ACPI_STATE_S5 5 856 857 /* 858 * Device Power States 859 */ 860 #define ACPI_STATE_D0 0 861 #define ACPI_STATE_D1 1 862 #define ACPI_STATE_D2 2 863 #define ACPI_STATE_D3 3 864 865 /* 866 * ACPI Device IDs 867 */ 868 #define ACPI_DEV_TIM "PNP0100" /* System timer */ 869 #define ACPI_DEV_ACPI "PNP0C08" /* ACPI device */ 870 #define ACPI_DEV_PCIB "PNP0A03" /* PCI bus */ 871 #define ACPI_DEV_GISAB "PNP0A05" /* Generic ISA Bus */ 872 #define ACPI_DEV_EIOB "PNP0A06" /* Extended I/O Bus */ 873 #define ACPI_DEV_PCIEB "PNP0A08" /* PCIe bus */ 874 #define ACPI_DEV_MR "PNP0C02" /* Motherboard resources */ 875 #define ACPI_DEV_NPROC "PNP0C04" /* Numeric data processor */ 876 #define ACPI_DEV_CS "PNP0C08" /* ACPI-Compliant System */ 877 #define ACPI_DEV_ECD "PNP0C09" /* Embedded Controller Device */ 878 #define ACPI_DEV_CMB "PNP0C0A" /* Control Method Battery */ 879 #define ACPI_DEV_FAN "PNP0C0B" /* Fan Device */ 880 #define ACPI_DEV_PBD "PNP0C0C" /* Power Button Device */ 881 #define ACPI_DEV_LD "PNP0C0D" /* Lid Device */ 882 #define ACPI_DEV_SBD "PNP0C0E" /* Sleep Button Device */ 883 #define ACPI_DEV_PILD "PNP0C0F" /* PCI Interrupt Link Device */ 884 #define ACPI_DEV_MEMD "PNP0C80" /* Memory Device */ 885 #define ACPI_DEV_MOUSE "PNP0F13" /* PS/2 Mouse */ 886 #define ACPI_DEV_SHC "ACPI0001" /* SMBus 1.0 Host Controller */ 887 #define ACPI_DEV_SBS "ACPI0002" /* Smart Battery Subsystem */ 888 #define ACPI_DEV_AC "ACPI0003" /* AC Device */ 889 #define ACPI_DEV_MD "ACPI0004" /* Module Device */ 890 #define ACPI_DEV_SMBUS "ACPI0005" /* SMBus 2.0 Host Controller */ 891 #define ACPI_DEV_GBD "ACPI0006" /* GPE Block Device */ 892 #define ACPI_DEV_PD "ACPI0007" /* Processor Device */ 893 #define ACPI_DEV_ALSD "ACPI0008" /* Ambient Light Sensor Device */ 894 #define ACPI_DEV_IOXA "ACPI0009" /* IO x APIC Device */ 895 #define ACPI_DEV_IOA "ACPI000A" /* IO APIC Device */ 896 #define ACPI_DEV_IOSA "ACPI000B" /* IO SAPIC Device */ 897 #define ACPI_DEV_THZ "THERMALZONE" /* Thermal Zone */ 898 #define ACPI_DEV_FFB "FIXEDBUTTON" /* Fixed Feature Button */ 899 #define ACPI_DEV_IPMI "IPI0001" /* IPMI */ 900 901 #endif /* !_DEV_ACPI_ACPIREG_H_ */ 902