1 /* $OpenBSD: hypervisor.h,v 1.10 2009/01/02 15:35:54 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2008 Mark Kettenis 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * UltraSPARC Hypervisor API. 21 */ 22 23 /* 24 * API versioning 25 */ 26 27 int64_t hv_api_get_version(uint64_t api_group, 28 uint64_t *major_number, uint64_t *minor_number); 29 30 /* 31 * Domain services 32 */ 33 34 int64_t hv_mach_desc(paddr_t buffer, psize_t *length); 35 36 /* 37 * CPU services 38 */ 39 40 void hv_cpu_yield(void); 41 int64_t hv_cpu_qconf(uint64_t queue, uint64_t base, uint64_t nentries); 42 43 #define CPU_MONDO_QUEUE 0x3c 44 #define DEVICE_MONDO_QUEUE 0x3d 45 46 int64_t hv_cpu_mondo_send(uint64_t ncpus, paddr_t cpulist, paddr_t data); 47 int64_t hv_cpu_myid(uint64_t *cpuid); 48 49 /* 50 * MMU services 51 */ 52 53 int64_t hv_mmu_demap_page(vaddr_t vaddr, uint64_t context, uint64_t flags); 54 int64_t hv_mmu_demap_ctx(uint64_t context, uint64_t flags); 55 int64_t hv_mmu_demap_all(uint64_t flags); 56 int64_t hv_mmu_map_perm_addr(vaddr_t vaddr, uint64_t tte, uint64_t flags); 57 int64_t hv_mmu_unmap_perm_addr(vaddr_t vaddr, uint64_t flags); 58 int64_t hv_mmu_map_addr(vaddr_t vaddr, uint64_t context, uint64_t tte, 59 uint64_t flags); 60 int64_t hv_mmu_unmap_addr(vaddr_t vaddr, uint64_t context, uint64_t flags); 61 62 #define MAP_DTLB 0x1 63 #define MAP_ITLB 0x2 64 65 struct tsb_desc { 66 uint16_t td_idxpgsz; 67 uint16_t td_assoc; 68 uint32_t td_size; 69 uint32_t td_ctxidx; 70 uint32_t td_pgsz; 71 paddr_t td_pa; 72 uint64_t td_reserved; 73 }; 74 75 int64_t hv_mmu_tsb_ctx0(uint64_t ntsb, paddr_t tsbptr); 76 int64_t hv_mmu_tsb_ctxnon0(uint64_t ntsb, paddr_t tsbptr); 77 78 /* 79 * Cache and memory services 80 */ 81 82 int64_t hv_mem_scrub(paddr_t raddr, psize_t length); 83 int64_t hv_mem_sync(paddr_t raddr, psize_t length); 84 85 /* 86 * Device interrupt services 87 */ 88 89 int64_t hv_intr_devino_to_sysino(uint64_t devhandle, uint64_t devino, 90 uint64_t *sysino); 91 int64_t hv_intr_getenabled(uint64_t sysino, uint64_t *intr_enabled); 92 int64_t hv_intr_setenabled(uint64_t sysino, uint64_t intr_enabled); 93 int64_t hv_intr_getstate(uint64_t sysino, uint64_t *intr_state); 94 int64_t hv_intr_setstate(uint64_t sysino, uint64_t intr_state); 95 int64_t hv_intr_gettarget(uint64_t sysino, uint64_t *cpuid); 96 int64_t hv_intr_settarget(uint64_t sysino, uint64_t cpuid); 97 98 #define INTR_DISABLED 0 99 #define INTR_ENABLED 1 100 101 #define INTR_IDLE 0 102 #define INTR_RECEIVED 1 103 #define INTR_DELIVERED 2 104 105 int64_t hv_vintr_getcookie(uint64_t devhandle, uint64_t devino, 106 uint64_t *cookie_value); 107 int64_t hv_vintr_setcookie(uint64_t devhandle, uint64_t devino, 108 uint64_t cookie_value); 109 int64_t hv_vintr_getenabled(uint64_t devhandle, uint64_t devino, 110 uint64_t *intr_enabled); 111 int64_t hv_vintr_setenabled(uint64_t devhandle, uint64_t devino, 112 uint64_t intr_enabled); 113 int64_t hv_vintr_getstate(uint64_t devhandle, uint64_t devino, 114 uint64_t *intr_state); 115 int64_t hv_vintr_setstate(uint64_t devhandle, uint64_t devino, 116 uint64_t intr_state); 117 int64_t hv_vintr_gettarget(uint64_t devhandle, uint64_t devino, 118 uint64_t *cpuid); 119 int64_t hv_vintr_settarget(uint64_t devhandle, uint64_t devino, 120 uint64_t cpuid); 121 122 /* 123 * Time of day services 124 */ 125 126 int64_t hv_tod_get(uint64_t *tod); 127 int64_t hv_tod_set(uint64_t tod); 128 129 /* 130 * Console services 131 */ 132 133 int64_t hv_cons_getchar(int64_t *ch); 134 int64_t hv_cons_putchar(int64_t ch); 135 int64_t hv_api_putchar(int64_t ch); 136 137 /* 138 * Domain state services 139 */ 140 141 int64_t hv_soft_state_set(uint64_t software_state, 142 paddr_t software_description_ptr); 143 144 #define SIS_NORMAL 0x1 145 #define SIS_TRANSITION 0x2 146 147 /* 148 * PCI I/O services 149 */ 150 151 int64_t hv_pci_iommu_map(uint64_t devhandle, uint64_t tsbid, 152 uint64_t nttes, uint64_t io_attributes, paddr_t io_page_list_p, 153 uint64_t *nttes_mapped); 154 int64_t hv_pci_iommu_demap(uint64_t devhandle, uint64_t tsbid, 155 uint64_t nttes, uint64_t *nttes_demapped); 156 int64_t hv_pci_iommu_getmap(uint64_t devhandle, uint64_t tsbid, 157 uint64_t *io_attributes, paddr_t *r_addr); 158 int64_t hv_pci_iommu_getbypass(uint64_t devhandle, paddr_t r_addr, 159 uint64_t io_attributes, uint64_t *io_addr); 160 161 int64_t hv_pci_config_get(uint64_t devhandle, uint64_t pci_device, 162 uint64_t pci_config_offset, uint64_t size, 163 uint64_t *error_flag, uint64_t *data); 164 int64_t hv_pci_config_put(uint64_t devhandle, uint64_t pci_device, 165 uint64_t pci_config_offset, uint64_t size, uint64_t data, 166 uint64_t *error_flag); 167 168 #define PCI_MAP_ATTR_READ 0x01 /* From memory */ 169 #define PCI_MAP_ATTR_WRITE 0x02 /* To memory */ 170 171 /* 172 * Logical Domain Channel services 173 */ 174 175 int64_t hv_ldc_tx_qconf(uint64_t ldc_id, paddr_t base_raddr, 176 uint64_t nentries); 177 int64_t hv_ldc_tx_qinfo(uint64_t ldc_id, paddr_t *base_raddr, 178 uint64_t *nentries); 179 int64_t hv_ldc_tx_get_state(uint64_t ldc_id, uint64_t *head_offset, 180 uint64_t *tail_offset, uint64_t *channel_state); 181 int64_t hv_ldc_tx_set_qtail(uint64_t ldc_id, uint64_t tail_offset); 182 int64_t hv_ldc_rx_qconf(uint64_t ldc_id, paddr_t base_raddr, 183 uint64_t nentries); 184 int64_t hv_ldc_rx_qinfo(uint64_t ldc_id, paddr_t *base_raddr, 185 uint64_t *nentries); 186 int64_t hv_ldc_rx_get_state(uint64_t ldc_id, uint64_t *head_offset, 187 uint64_t *tail_offset, uint64_t *channel_state); 188 int64_t hv_ldc_rx_set_qhead(uint64_t ldc_id, uint64_t head_offset); 189 190 #define LDC_CHANNEL_DOWN 0 191 #define LDC_CHANNEL_UP 1 192 #define LDC_CHANNEL_RESET 2 193 194 int64_t hv_ldc_set_map_table(uint64_t ldc_id, paddr_t base_raddr, 195 uint64_t nentries); 196 int64_t hv_ldc_get_map_table(uint64_t ldc_id, paddr_t *base_raddr, 197 uint64_t *nentries); 198 int64_t hv_ldc_copy(uint64_t ldc_id, uint64_t flags, uint64_t cookie, 199 paddr_t raddr, psize_t length, paddr_t *ret_length); 200 201 #define LDC_COPY_IN 0 202 #define LDC_COPY_OUT 1 203 204 /* 205 * Cryptographic services 206 */ 207 208 int64_t hv_rng_get_diag_control(void); 209 int64_t hv_rng_ctl_read(paddr_t raddr, uint64_t *state, uint64_t *delta); 210 int64_t hv_rng_ctl_write(paddr_t raddr, uint64_t state, uint64_t timeout, 211 uint64_t *delta); 212 213 #define RNG_STATE_UNCONFIGURED 0 214 #define RNG_STATE_CONFIGURED 1 215 #define RNG_STATE_HEALTHCHECK 2 216 #define RNG_STATE_ERROR 3 217 218 int64_t hv_rng_data_read_diag(paddr_t raddr, uint64_t size, uint64_t *delta); 219 int64_t hv_rng_data_read(paddr_t raddr, uint64_t *delta); 220 221 /* 222 * Error codes 223 */ 224 225 #define H_EOK 0 226 #define H_ENOCPU 1 227 #define H_ENORADDR 2 228 #define H_ENOINTR 3 229 #define H_EBADPGSZ 4 230 #define H_EBADTSB 5 231 #define H_EINVAL 6 232 #define H_EBADTRAP 7 233 #define H_EBADALIGN 8 234 #define H_EWOULDBLOCK 9 235 #define H_ENOACCESS 10 236 #define H_EIO 11 237 #define H_ECPUERROR 12 238 #define H_ENOTSUPPORTED 13 239 #define H_ENOMAP 14 240 #define H_ETOOMANY 15 241 #define H_ECHANNEL 16 242