1 /* $OpenBSD: fpu_implode.c,v 1.5 2003/06/02 23:27:55 millert Exp $ */ 2 /* $NetBSD: fpu_implode.c,v 1.7 2000/08/03 18:32:08 eeh Exp $ */ 3 4 /* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 42 */ 43 44 /* 45 * FPU subroutines: `implode' internal format numbers into the machine's 46 * `packed binary' format. 47 */ 48 49 #include <sys/types.h> 50 #include <sys/systm.h> 51 52 #include <machine/ieee.h> 53 #include <machine/instr.h> 54 #include <machine/reg.h> 55 56 #include <sparc64/fpu/fpu_arith.h> 57 #include <sparc64/fpu/fpu_emu.h> 58 #include <sparc64/fpu/fpu_extern.h> 59 60 static int round(register struct fpemu *, register struct fpn *); 61 static int toinf(struct fpemu *, int); 62 63 /* 64 * Round a number (algorithm from Motorola MC68882 manual, modified for 65 * our internal format). Set inexact exception if rounding is required. 66 * Return true iff we rounded up. 67 * 68 * After rounding, we discard the guard and round bits by shifting right 69 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 70 * This saves effort later. 71 * 72 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 73 * responsibility to fix this if necessary. 74 */ 75 static int 76 round(register struct fpemu *fe, register struct fpn *fp) 77 { 78 register u_int m0, m1, m2, m3; 79 register int gr, s; 80 81 m0 = fp->fp_mant[0]; 82 m1 = fp->fp_mant[1]; 83 m2 = fp->fp_mant[2]; 84 m3 = fp->fp_mant[3]; 85 gr = m3 & 3; 86 s = fp->fp_sticky; 87 88 /* mant >>= FP_NG */ 89 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 90 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 91 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 92 m0 >>= FP_NG; 93 94 if ((gr | s) == 0) /* result is exact: no rounding needed */ 95 goto rounddown; 96 97 fe->fe_cx |= FSR_NX; /* inexact */ 98 99 /* Go to rounddown to round down; break to round up. */ 100 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 101 102 case FSR_RD_RN: 103 default: 104 /* 105 * Round only if guard is set (gr & 2). If guard is set, 106 * but round & sticky both clear, then we want to round 107 * but have a tie, so round to even, i.e., add 1 iff odd. 108 */ 109 if ((gr & 2) == 0) 110 goto rounddown; 111 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 112 break; 113 goto rounddown; 114 115 case FSR_RD_RZ: 116 /* Round towards zero, i.e., down. */ 117 goto rounddown; 118 119 case FSR_RD_RM: 120 /* Round towards -Inf: up if negative, down if positive. */ 121 if (fp->fp_sign) 122 break; 123 goto rounddown; 124 125 case FSR_RD_RP: 126 /* Round towards +Inf: up if positive, down otherwise. */ 127 if (!fp->fp_sign) 128 break; 129 goto rounddown; 130 } 131 132 /* Bump low bit of mantissa, with carry. */ 133 FPU_ADDS(m3, m3, 1); 134 FPU_ADDCS(m2, m2, 0); 135 FPU_ADDCS(m1, m1, 0); 136 FPU_ADDC(m0, m0, 0); 137 fp->fp_mant[0] = m0; 138 fp->fp_mant[1] = m1; 139 fp->fp_mant[2] = m2; 140 fp->fp_mant[3] = m3; 141 return (1); 142 143 rounddown: 144 fp->fp_mant[0] = m0; 145 fp->fp_mant[1] = m1; 146 fp->fp_mant[2] = m2; 147 fp->fp_mant[3] = m3; 148 return (0); 149 } 150 151 /* 152 * For overflow: return true if overflow is to go to +/-Inf, according 153 * to the sign of the overflowing result. If false, overflow is to go 154 * to the largest magnitude value instead. 155 */ 156 static int 157 toinf(struct fpemu *fe, int sign) 158 { 159 int inf; 160 161 /* look at rounding direction */ 162 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 163 164 default: 165 case FSR_RD_RN: /* the nearest value is always Inf */ 166 inf = 1; 167 break; 168 169 case FSR_RD_RZ: /* toward 0 => never towards Inf */ 170 inf = 0; 171 break; 172 173 case FSR_RD_RP: /* toward +Inf iff positive */ 174 inf = sign == 0; 175 break; 176 177 case FSR_RD_RM: /* toward -Inf iff negative */ 178 inf = sign; 179 break; 180 } 181 return (inf); 182 } 183 184 /* 185 * fpn -> int (int value returned as return value). 186 * 187 * N.B.: this conversion always rounds towards zero (this is a peculiarity 188 * of the SPARC instruction set). 189 */ 190 u_int 191 fpu_ftoi(fe, fp) 192 struct fpemu *fe; 193 register struct fpn *fp; 194 { 195 register u_int i; 196 register int sign, exp; 197 198 sign = fp->fp_sign; 199 switch (fp->fp_class) { 200 201 case FPC_ZERO: 202 return (0); 203 204 case FPC_NUM: 205 /* 206 * If exp >= 2^32, overflow. Otherwise shift value right 207 * into last mantissa word (this will not exceed 0xffffffff), 208 * shifting any guard and round bits out into the sticky 209 * bit. Then ``round'' towards zero, i.e., just set an 210 * inexact exception if sticky is set (see round()). 211 * If the result is > 0x80000000, or is positive and equals 212 * 0x80000000, overflow; otherwise the last fraction word 213 * is the result. 214 */ 215 if ((exp = fp->fp_exp) >= 32) 216 break; 217 /* NB: the following includes exp < 0 cases */ 218 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 219 fe->fe_cx |= FSR_NX; 220 i = fp->fp_mant[3]; 221 if (i >= ((u_int)0x80000000 + sign)) 222 break; 223 return (sign ? -i : i); 224 225 default: /* Inf, qNaN, sNaN */ 226 break; 227 } 228 /* overflow: replace any inexact exception with invalid */ 229 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 230 return (0x7fffffff + sign); 231 } 232 233 #ifdef SUN4U 234 /* 235 * fpn -> extended int (high bits of int value returned as return value). 236 * 237 * N.B.: this conversion always rounds towards zero (this is a peculiarity 238 * of the SPARC instruction set). 239 */ 240 u_int 241 fpu_ftox(fe, fp, res) 242 struct fpemu *fe; 243 register struct fpn *fp; 244 u_int *res; 245 { 246 register u_int64_t i; 247 register int sign, exp; 248 249 sign = fp->fp_sign; 250 switch (fp->fp_class) { 251 252 case FPC_ZERO: 253 i = 0; 254 goto out; 255 256 case FPC_NUM: 257 /* 258 * If exp >= 2^64, overflow. Otherwise shift value right 259 * into last mantissa word (this will not exceed 0xffffffffffffffff), 260 * shifting any guard and round bits out into the sticky 261 * bit. Then ``round'' towards zero, i.e., just set an 262 * inexact exception if sticky is set (see round()). 263 * If the result is > 0x8000000000000000, or is positive and equals 264 * 0x8000000000000000, overflow; otherwise the last fraction word 265 * is the result. 266 */ 267 if ((exp = fp->fp_exp) >= 64) 268 break; 269 /* NB: the following includes exp < 0 cases */ 270 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 271 fe->fe_cx |= FSR_NX; 272 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3]; 273 if (i >= ((u_int64_t)0x8000000000000000LL + sign)) 274 break; 275 if (sign) 276 i = -i; 277 goto out; 278 279 default: /* Inf, qNaN, sNaN */ 280 break; 281 } 282 /* overflow: replace any inexact exception with invalid */ 283 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 284 i = 0x7fffffffffffffffLL + sign; 285 out: 286 res[1] = i & 0xffffffff; 287 return (i >> 32); 288 } 289 #endif /* SUN4U */ 290 291 /* 292 * fpn -> single (32 bit single returned as return value). 293 * We assume <= 29 bits in a single-precision fraction (1.f part). 294 */ 295 u_int 296 fpu_ftos(fe, fp) 297 struct fpemu *fe; 298 register struct fpn *fp; 299 { 300 register u_int sign = fp->fp_sign << 31; 301 register int exp; 302 303 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 304 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 305 306 /* Take care of non-numbers first. */ 307 if (ISNAN(fp)) { 308 /* 309 * Preserve upper bits of NaN, per SPARC V8 appendix N. 310 * Note that fp->fp_mant[0] has the quiet bit set, 311 * even if it is classified as a signalling NaN. 312 */ 313 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 314 exp = SNG_EXP_INFNAN; 315 goto done; 316 } 317 if (ISINF(fp)) 318 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 319 if (ISZERO(fp)) 320 return (sign); 321 322 /* 323 * Normals (including subnormals). Drop all the fraction bits 324 * (including the explicit ``implied'' 1 bit) down into the 325 * single-precision range. If the number is subnormal, move 326 * the ``implied'' 1 into the explicit range as well, and shift 327 * right to introduce leading zeroes. Rounding then acts 328 * differently for normals and subnormals: the largest subnormal 329 * may round to the smallest normal (1.0 x 2^minexp), or may 330 * remain subnormal. In the latter case, signal an underflow 331 * if the result was inexact or if underflow traps are enabled. 332 * 333 * Rounding a normal, on the other hand, always produces another 334 * normal (although either way the result might be too big for 335 * single precision, and cause an overflow). If rounding a 336 * normal produces 2.0 in the fraction, we need not adjust that 337 * fraction at all, since both 1.0 and 2.0 are zero under the 338 * fraction mask. 339 * 340 * Note that the guard and round bits vanish from the number after 341 * rounding. 342 */ 343 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 344 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 345 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 346 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 347 return (sign | SNG_EXP(1) | 0); 348 if ((fe->fe_cx & FSR_NX) || 349 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 350 fe->fe_cx |= FSR_UF; 351 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 352 } 353 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 354 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 355 #ifdef DIAGNOSTIC 356 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 357 panic("fpu_ftos"); 358 #endif 359 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 360 exp++; 361 if (exp >= SNG_EXP_INFNAN) { 362 /* overflow to inf or to max single */ 363 fe->fe_cx |= FSR_OF | FSR_NX; 364 if (toinf(fe, sign)) 365 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 366 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 367 } 368 done: 369 /* phew, made it */ 370 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 371 } 372 373 /* 374 * fpn -> double (32 bit high-order result returned; 32-bit low order result 375 * left in res[1]). Assumes <= 61 bits in double precision fraction. 376 * 377 * This code mimics fpu_ftos; see it for comments. 378 */ 379 u_int 380 fpu_ftod(fe, fp, res) 381 struct fpemu *fe; 382 register struct fpn *fp; 383 u_int *res; 384 { 385 register u_int sign = fp->fp_sign << 31; 386 register int exp; 387 388 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 389 #define DBL_MASK (DBL_EXP(1) - 1) 390 391 if (ISNAN(fp)) { 392 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 393 exp = DBL_EXP_INFNAN; 394 goto done; 395 } 396 if (ISINF(fp)) { 397 sign |= DBL_EXP(DBL_EXP_INFNAN); 398 goto zero; 399 } 400 if (ISZERO(fp)) { 401 zero: res[1] = 0; 402 return (sign); 403 } 404 405 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 406 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 407 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 408 res[1] = 0; 409 return (sign | DBL_EXP(1) | 0); 410 } 411 if ((fe->fe_cx & FSR_NX) || 412 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 413 fe->fe_cx |= FSR_UF; 414 exp = 0; 415 goto done; 416 } 417 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 418 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 419 exp++; 420 if (exp >= DBL_EXP_INFNAN) { 421 fe->fe_cx |= FSR_OF | FSR_NX; 422 if (toinf(fe, sign)) { 423 res[1] = 0; 424 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 425 } 426 res[1] = ~0; 427 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 428 } 429 done: 430 res[1] = fp->fp_mant[3]; 431 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 432 } 433 434 /* 435 * fpn -> extended (32 bit high-order result returned; low-order fraction 436 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but 437 * our internal format *is* extended precision, plus 2 bits for guard/round, 438 * so we can avoid a small bit of work. 439 */ 440 u_int 441 fpu_ftoq(fe, fp, res) 442 struct fpemu *fe; 443 register struct fpn *fp; 444 u_int *res; 445 { 446 register u_int sign = fp->fp_sign << 31; 447 register int exp; 448 449 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31)) 450 #define EXT_MASK (EXT_EXP(1) - 1) 451 452 if (ISNAN(fp)) { 453 (void) fpu_shr(fp, 2); /* since we are not rounding */ 454 exp = EXT_EXP_INFNAN; 455 goto done; 456 } 457 if (ISINF(fp)) { 458 sign |= EXT_EXP(EXT_EXP_INFNAN); 459 goto zero; 460 } 461 if (ISZERO(fp)) { 462 zero: res[1] = res[2] = res[3] = 0; 463 return (sign); 464 } 465 466 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { 467 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 468 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { 469 res[1] = res[2] = res[3] = 0; 470 return (sign | EXT_EXP(1) | 0); 471 } 472 if ((fe->fe_cx & FSR_NX) || 473 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 474 fe->fe_cx |= FSR_UF; 475 exp = 0; 476 goto done; 477 } 478 /* Since internal == extended, no need to shift here. */ 479 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2)) 480 exp++; 481 if (exp >= EXT_EXP_INFNAN) { 482 fe->fe_cx |= FSR_OF | FSR_NX; 483 if (toinf(fe, sign)) { 484 res[1] = res[2] = res[3] = 0; 485 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 486 } 487 res[1] = res[2] = res[3] = ~0; 488 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 489 } 490 done: 491 res[1] = fp->fp_mant[1]; 492 res[2] = fp->fp_mant[2]; 493 res[3] = fp->fp_mant[3]; 494 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK)); 495 } 496 497 /* 498 * Implode an fpn, writing the result into the given space. 499 */ 500 void 501 fpu_implode(fe, fp, type, space) 502 struct fpemu *fe; 503 register struct fpn *fp; 504 int type; 505 register u_int *space; 506 { 507 DPRINTF(FPE_INSN, ("fpu_implode: ")); 508 switch (type) { 509 510 #ifdef SUN4U 511 case FTYPE_LNG: 512 space[0] = fpu_ftox(fe, fp, space); 513 DPRINTF(FPE_INSN, ("LNG %x %x\n", space[0], space[1])); 514 break; 515 #endif /* SUN4U */ 516 517 case FTYPE_INT: 518 space[0] = fpu_ftoi(fe, fp); 519 DPRINTF(FPE_INSN, ("INT %x\n", space[0])); 520 break; 521 522 case FTYPE_SNG: 523 space[0] = fpu_ftos(fe, fp); 524 DPRINTF(FPE_INSN, ("SNG %x\n", space[0])); 525 break; 526 527 case FTYPE_DBL: 528 space[0] = fpu_ftod(fe, fp, space); 529 DPRINTF(FPE_INSN, ("DBL %x %x\n", space[0], space[1])); 530 break; 531 532 case FTYPE_EXT: 533 /* funky rounding precision options ?? */ 534 space[0] = fpu_ftoq(fe, fp, space); 535 DPRINTF(FPE_INSN, ("EXT %x %x %x %x\n", space[0], space[1], 536 space[2], space[3])); 537 break; 538 539 default: 540 panic("fpu_implode"); 541 } 542 } 543