1 /* $OpenBSD: fpu_implode.c,v 1.3 2001/09/10 16:05:17 jason Exp $ */ 2 /* $NetBSD: fpu_implode.c,v 1.7 2000/08/03 18:32:08 eeh Exp $ */ 3 4 /* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. All advertising materials mentioning features or use of this software 26 * must display the following acknowledgement: 27 * This product includes software developed by the University of 28 * California, Berkeley and its contributors. 29 * 4. Neither the name of the University nor the names of its contributors 30 * may be used to endorse or promote products derived from this software 31 * without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 * 45 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 46 */ 47 48 /* 49 * FPU subroutines: `implode' internal format numbers into the machine's 50 * `packed binary' format. 51 */ 52 53 #include <sys/types.h> 54 #include <sys/systm.h> 55 56 #include <machine/ieee.h> 57 #include <machine/instr.h> 58 #include <machine/reg.h> 59 60 #include <sparc64/fpu/fpu_arith.h> 61 #include <sparc64/fpu/fpu_emu.h> 62 #include <sparc64/fpu/fpu_extern.h> 63 64 static int round __P((register struct fpemu *, register struct fpn *)); 65 static int toinf __P((struct fpemu *, int)); 66 67 /* 68 * Round a number (algorithm from Motorola MC68882 manual, modified for 69 * our internal format). Set inexact exception if rounding is required. 70 * Return true iff we rounded up. 71 * 72 * After rounding, we discard the guard and round bits by shifting right 73 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 74 * This saves effort later. 75 * 76 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 77 * responsibility to fix this if necessary. 78 */ 79 static int 80 round(register struct fpemu *fe, register struct fpn *fp) 81 { 82 register u_int m0, m1, m2, m3; 83 register int gr, s; 84 85 m0 = fp->fp_mant[0]; 86 m1 = fp->fp_mant[1]; 87 m2 = fp->fp_mant[2]; 88 m3 = fp->fp_mant[3]; 89 gr = m3 & 3; 90 s = fp->fp_sticky; 91 92 /* mant >>= FP_NG */ 93 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 94 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 95 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 96 m0 >>= FP_NG; 97 98 if ((gr | s) == 0) /* result is exact: no rounding needed */ 99 goto rounddown; 100 101 fe->fe_cx |= FSR_NX; /* inexact */ 102 103 /* Go to rounddown to round down; break to round up. */ 104 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 105 106 case FSR_RD_RN: 107 default: 108 /* 109 * Round only if guard is set (gr & 2). If guard is set, 110 * but round & sticky both clear, then we want to round 111 * but have a tie, so round to even, i.e., add 1 iff odd. 112 */ 113 if ((gr & 2) == 0) 114 goto rounddown; 115 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 116 break; 117 goto rounddown; 118 119 case FSR_RD_RZ: 120 /* Round towards zero, i.e., down. */ 121 goto rounddown; 122 123 case FSR_RD_RM: 124 /* Round towards -Inf: up if negative, down if positive. */ 125 if (fp->fp_sign) 126 break; 127 goto rounddown; 128 129 case FSR_RD_RP: 130 /* Round towards +Inf: up if positive, down otherwise. */ 131 if (!fp->fp_sign) 132 break; 133 goto rounddown; 134 } 135 136 /* Bump low bit of mantissa, with carry. */ 137 FPU_ADDS(m3, m3, 1); 138 FPU_ADDCS(m2, m2, 0); 139 FPU_ADDCS(m1, m1, 0); 140 FPU_ADDC(m0, m0, 0); 141 fp->fp_mant[0] = m0; 142 fp->fp_mant[1] = m1; 143 fp->fp_mant[2] = m2; 144 fp->fp_mant[3] = m3; 145 return (1); 146 147 rounddown: 148 fp->fp_mant[0] = m0; 149 fp->fp_mant[1] = m1; 150 fp->fp_mant[2] = m2; 151 fp->fp_mant[3] = m3; 152 return (0); 153 } 154 155 /* 156 * For overflow: return true if overflow is to go to +/-Inf, according 157 * to the sign of the overflowing result. If false, overflow is to go 158 * to the largest magnitude value instead. 159 */ 160 static int 161 toinf(struct fpemu *fe, int sign) 162 { 163 int inf; 164 165 /* look at rounding direction */ 166 switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) { 167 168 default: 169 case FSR_RD_RN: /* the nearest value is always Inf */ 170 inf = 1; 171 break; 172 173 case FSR_RD_RZ: /* toward 0 => never towards Inf */ 174 inf = 0; 175 break; 176 177 case FSR_RD_RP: /* toward +Inf iff positive */ 178 inf = sign == 0; 179 break; 180 181 case FSR_RD_RM: /* toward -Inf iff negative */ 182 inf = sign; 183 break; 184 } 185 return (inf); 186 } 187 188 /* 189 * fpn -> int (int value returned as return value). 190 * 191 * N.B.: this conversion always rounds towards zero (this is a peculiarity 192 * of the SPARC instruction set). 193 */ 194 u_int 195 fpu_ftoi(fe, fp) 196 struct fpemu *fe; 197 register struct fpn *fp; 198 { 199 register u_int i; 200 register int sign, exp; 201 202 sign = fp->fp_sign; 203 switch (fp->fp_class) { 204 205 case FPC_ZERO: 206 return (0); 207 208 case FPC_NUM: 209 /* 210 * If exp >= 2^32, overflow. Otherwise shift value right 211 * into last mantissa word (this will not exceed 0xffffffff), 212 * shifting any guard and round bits out into the sticky 213 * bit. Then ``round'' towards zero, i.e., just set an 214 * inexact exception if sticky is set (see round()). 215 * If the result is > 0x80000000, or is positive and equals 216 * 0x80000000, overflow; otherwise the last fraction word 217 * is the result. 218 */ 219 if ((exp = fp->fp_exp) >= 32) 220 break; 221 /* NB: the following includes exp < 0 cases */ 222 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 223 fe->fe_cx |= FSR_NX; 224 i = fp->fp_mant[3]; 225 if (i >= ((u_int)0x80000000 + sign)) 226 break; 227 return (sign ? -i : i); 228 229 default: /* Inf, qNaN, sNaN */ 230 break; 231 } 232 /* overflow: replace any inexact exception with invalid */ 233 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 234 return (0x7fffffff + sign); 235 } 236 237 #ifdef SUN4U 238 /* 239 * fpn -> extended int (high bits of int value returned as return value). 240 * 241 * N.B.: this conversion always rounds towards zero (this is a peculiarity 242 * of the SPARC instruction set). 243 */ 244 u_int 245 fpu_ftox(fe, fp, res) 246 struct fpemu *fe; 247 register struct fpn *fp; 248 u_int *res; 249 { 250 register u_int64_t i; 251 register int sign, exp; 252 253 sign = fp->fp_sign; 254 switch (fp->fp_class) { 255 256 case FPC_ZERO: 257 i = 0; 258 goto out; 259 260 case FPC_NUM: 261 /* 262 * If exp >= 2^64, overflow. Otherwise shift value right 263 * into last mantissa word (this will not exceed 0xffffffffffffffff), 264 * shifting any guard and round bits out into the sticky 265 * bit. Then ``round'' towards zero, i.e., just set an 266 * inexact exception if sticky is set (see round()). 267 * If the result is > 0x8000000000000000, or is positive and equals 268 * 0x8000000000000000, overflow; otherwise the last fraction word 269 * is the result. 270 */ 271 if ((exp = fp->fp_exp) >= 64) 272 break; 273 /* NB: the following includes exp < 0 cases */ 274 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 275 fe->fe_cx |= FSR_NX; 276 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3]; 277 if (i >= ((u_int64_t)0x8000000000000000LL + sign)) 278 break; 279 if (sign) 280 i = -i; 281 goto out; 282 283 default: /* Inf, qNaN, sNaN */ 284 break; 285 } 286 /* overflow: replace any inexact exception with invalid */ 287 fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV; 288 i = 0x7fffffffffffffffLL + sign; 289 out: 290 res[1] = i & 0xffffffff; 291 return (i >> 32); 292 } 293 #endif /* SUN4U */ 294 295 /* 296 * fpn -> single (32 bit single returned as return value). 297 * We assume <= 29 bits in a single-precision fraction (1.f part). 298 */ 299 u_int 300 fpu_ftos(fe, fp) 301 struct fpemu *fe; 302 register struct fpn *fp; 303 { 304 register u_int sign = fp->fp_sign << 31; 305 register int exp; 306 307 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 308 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 309 310 /* Take care of non-numbers first. */ 311 if (ISNAN(fp)) { 312 /* 313 * Preserve upper bits of NaN, per SPARC V8 appendix N. 314 * Note that fp->fp_mant[0] has the quiet bit set, 315 * even if it is classified as a signalling NaN. 316 */ 317 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 318 exp = SNG_EXP_INFNAN; 319 goto done; 320 } 321 if (ISINF(fp)) 322 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 323 if (ISZERO(fp)) 324 return (sign); 325 326 /* 327 * Normals (including subnormals). Drop all the fraction bits 328 * (including the explicit ``implied'' 1 bit) down into the 329 * single-precision range. If the number is subnormal, move 330 * the ``implied'' 1 into the explicit range as well, and shift 331 * right to introduce leading zeroes. Rounding then acts 332 * differently for normals and subnormals: the largest subnormal 333 * may round to the smallest normal (1.0 x 2^minexp), or may 334 * remain subnormal. In the latter case, signal an underflow 335 * if the result was inexact or if underflow traps are enabled. 336 * 337 * Rounding a normal, on the other hand, always produces another 338 * normal (although either way the result might be too big for 339 * single precision, and cause an overflow). If rounding a 340 * normal produces 2.0 in the fraction, we need not adjust that 341 * fraction at all, since both 1.0 and 2.0 are zero under the 342 * fraction mask. 343 * 344 * Note that the guard and round bits vanish from the number after 345 * rounding. 346 */ 347 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 348 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 349 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 350 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 351 return (sign | SNG_EXP(1) | 0); 352 if ((fe->fe_cx & FSR_NX) || 353 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 354 fe->fe_cx |= FSR_UF; 355 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 356 } 357 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 358 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 359 #ifdef DIAGNOSTIC 360 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 361 panic("fpu_ftos"); 362 #endif 363 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 364 exp++; 365 if (exp >= SNG_EXP_INFNAN) { 366 /* overflow to inf or to max single */ 367 fe->fe_cx |= FSR_OF | FSR_NX; 368 if (toinf(fe, sign)) 369 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 370 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 371 } 372 done: 373 /* phew, made it */ 374 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 375 } 376 377 /* 378 * fpn -> double (32 bit high-order result returned; 32-bit low order result 379 * left in res[1]). Assumes <= 61 bits in double precision fraction. 380 * 381 * This code mimics fpu_ftos; see it for comments. 382 */ 383 u_int 384 fpu_ftod(fe, fp, res) 385 struct fpemu *fe; 386 register struct fpn *fp; 387 u_int *res; 388 { 389 register u_int sign = fp->fp_sign << 31; 390 register int exp; 391 392 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 393 #define DBL_MASK (DBL_EXP(1) - 1) 394 395 if (ISNAN(fp)) { 396 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 397 exp = DBL_EXP_INFNAN; 398 goto done; 399 } 400 if (ISINF(fp)) { 401 sign |= DBL_EXP(DBL_EXP_INFNAN); 402 goto zero; 403 } 404 if (ISZERO(fp)) { 405 zero: res[1] = 0; 406 return (sign); 407 } 408 409 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 410 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 411 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 412 res[1] = 0; 413 return (sign | DBL_EXP(1) | 0); 414 } 415 if ((fe->fe_cx & FSR_NX) || 416 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 417 fe->fe_cx |= FSR_UF; 418 exp = 0; 419 goto done; 420 } 421 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 422 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 423 exp++; 424 if (exp >= DBL_EXP_INFNAN) { 425 fe->fe_cx |= FSR_OF | FSR_NX; 426 if (toinf(fe, sign)) { 427 res[1] = 0; 428 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 429 } 430 res[1] = ~0; 431 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 432 } 433 done: 434 res[1] = fp->fp_mant[3]; 435 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 436 } 437 438 /* 439 * fpn -> extended (32 bit high-order result returned; low-order fraction 440 * words left in res[1]..res[3]). Like ftod, which is like ftos ... but 441 * our internal format *is* extended precision, plus 2 bits for guard/round, 442 * so we can avoid a small bit of work. 443 */ 444 u_int 445 fpu_ftoq(fe, fp, res) 446 struct fpemu *fe; 447 register struct fpn *fp; 448 u_int *res; 449 { 450 register u_int sign = fp->fp_sign << 31; 451 register int exp; 452 453 #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31)) 454 #define EXT_MASK (EXT_EXP(1) - 1) 455 456 if (ISNAN(fp)) { 457 (void) fpu_shr(fp, 2); /* since we are not rounding */ 458 exp = EXT_EXP_INFNAN; 459 goto done; 460 } 461 if (ISINF(fp)) { 462 sign |= EXT_EXP(EXT_EXP_INFNAN); 463 goto zero; 464 } 465 if (ISZERO(fp)) { 466 zero: res[1] = res[2] = res[3] = 0; 467 return (sign); 468 } 469 470 if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) { 471 (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp); 472 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) { 473 res[1] = res[2] = res[3] = 0; 474 return (sign | EXT_EXP(1) | 0); 475 } 476 if ((fe->fe_cx & FSR_NX) || 477 (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT))) 478 fe->fe_cx |= FSR_UF; 479 exp = 0; 480 goto done; 481 } 482 /* Since internal == extended, no need to shift here. */ 483 if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2)) 484 exp++; 485 if (exp >= EXT_EXP_INFNAN) { 486 fe->fe_cx |= FSR_OF | FSR_NX; 487 if (toinf(fe, sign)) { 488 res[1] = res[2] = res[3] = 0; 489 return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0); 490 } 491 res[1] = res[2] = res[3] = ~0; 492 return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK); 493 } 494 done: 495 res[1] = fp->fp_mant[1]; 496 res[2] = fp->fp_mant[2]; 497 res[3] = fp->fp_mant[3]; 498 return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK)); 499 } 500 501 /* 502 * Implode an fpn, writing the result into the given space. 503 */ 504 void 505 fpu_implode(fe, fp, type, space) 506 struct fpemu *fe; 507 register struct fpn *fp; 508 int type; 509 register u_int *space; 510 { 511 DPRINTF(FPE_INSN, ("fpu_implode: ")); 512 switch (type) { 513 514 #ifdef SUN4U 515 case FTYPE_LNG: 516 space[0] = fpu_ftox(fe, fp, space); 517 DPRINTF(FPE_INSN, ("LNG %x %x\n", space[0], space[1])); 518 break; 519 #endif /* SUN4U */ 520 521 case FTYPE_INT: 522 space[0] = fpu_ftoi(fe, fp); 523 DPRINTF(FPE_INSN, ("INT %x\n", space[0])); 524 break; 525 526 case FTYPE_SNG: 527 space[0] = fpu_ftos(fe, fp); 528 DPRINTF(FPE_INSN, ("SNG %x\n", space[0])); 529 break; 530 531 case FTYPE_DBL: 532 space[0] = fpu_ftod(fe, fp, space); 533 DPRINTF(FPE_INSN, ("DBL %x %x\n", space[0], space[1])); 534 break; 535 536 case FTYPE_EXT: 537 /* funky rounding precision options ?? */ 538 space[0] = fpu_ftoq(fe, fp, space); 539 DPRINTF(FPE_INSN, ("EXT %x %x %x %x\n", space[0], space[1], 540 space[2], space[3])); 541 break; 542 543 default: 544 panic("fpu_implode"); 545 } 546 } 547