1 /* $OpenBSD: fpu_explode.c,v 1.3 2003/06/02 23:27:55 millert Exp $ */ 2 /* $NetBSD: fpu_explode.c,v 1.5 2000/08/03 18:32:08 eeh Exp $ */ 3 4 /* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 42 */ 43 44 /* 45 * FPU subroutines: `explode' the machine's `packed binary' format numbers 46 * into our internal format. 47 */ 48 49 #include <sys/types.h> 50 #include <sys/systm.h> 51 52 #include <machine/ieee.h> 53 #include <machine/instr.h> 54 #include <machine/reg.h> 55 56 #include <sparc64/fpu/fpu_arith.h> 57 #include <sparc64/fpu/fpu_emu.h> 58 #include <sparc64/fpu/fpu_extern.h> 59 60 /* 61 * N.B.: in all of the following, we assume the FP format is 62 * 63 * --------------------------- 64 * | s | exponent | fraction | 65 * --------------------------- 66 * 67 * (which represents -1**s * 1.fraction * 2**exponent), so that the 68 * sign bit is way at the top (bit 31), the exponent is next, and 69 * then the remaining bits mark the fraction. A zero exponent means 70 * zero or denormalized (0.fraction rather than 1.fraction), and the 71 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 72 * 73 * Since the sign bit is always the topmost bit---this holds even for 74 * integers---we set that outside all the *tof functions. Each function 75 * returns the class code for the new number (but note that we use 76 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 77 */ 78 79 /* 80 * int -> fpn. 81 */ 82 int 83 fpu_itof(fp, i) 84 register struct fpn *fp; 85 register u_int i; 86 { 87 88 if (i == 0) 89 return (FPC_ZERO); 90 /* 91 * The value FP_1 represents 2^FP_LG, so set the exponent 92 * there and let normalization fix it up. Convert negative 93 * numbers to sign-and-magnitude. Note that this relies on 94 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 95 */ 96 fp->fp_exp = FP_LG; 97 fp->fp_mant[0] = (int)i < 0 ? -i : i; 98 fp->fp_mant[1] = 0; 99 fp->fp_mant[2] = 0; 100 fp->fp_mant[3] = 0; 101 fpu_norm(fp); 102 return (FPC_NUM); 103 } 104 105 #ifdef SUN4U 106 /* 107 * 64-bit int -> fpn. 108 */ 109 int 110 fpu_xtof(fp, i) 111 register struct fpn *fp; 112 register u_int64_t i; 113 { 114 if (i == 0) 115 return (FPC_ZERO); 116 117 /* 118 * The value FP_1 represents 2^FP_LG, so set the exponent 119 * there and let normalization fix it up. Convert negative 120 * numbers to sign-and-magnitude. Note that this relies on 121 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 122 */ 123 fp->fp_exp = FP_LG2; 124 *((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i; 125 fp->fp_mant[2] = 0; 126 fp->fp_mant[3] = 0; 127 fpu_norm(fp); 128 return (FPC_NUM); 129 } 130 #endif /* SUN4U */ 131 132 #define mask(nbits) ((1L << (nbits)) - 1) 133 134 /* 135 * All external floating formats convert to internal in the same manner, 136 * as defined here. Note that only normals get an implied 1.0 inserted. 137 */ 138 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 139 if (exp == 0) { \ 140 if (allfrac == 0) \ 141 return (FPC_ZERO); \ 142 fp->fp_exp = 1 - expbias; \ 143 fp->fp_mant[0] = f0; \ 144 fp->fp_mant[1] = f1; \ 145 fp->fp_mant[2] = f2; \ 146 fp->fp_mant[3] = f3; \ 147 fpu_norm(fp); \ 148 return (FPC_NUM); \ 149 } \ 150 if (exp == (2 * expbias + 1)) { \ 151 if (allfrac == 0) \ 152 return (FPC_INF); \ 153 fp->fp_mant[0] = f0; \ 154 fp->fp_mant[1] = f1; \ 155 fp->fp_mant[2] = f2; \ 156 fp->fp_mant[3] = f3; \ 157 return (FPC_QNAN); \ 158 } \ 159 fp->fp_exp = exp - expbias; \ 160 fp->fp_mant[0] = FP_1 | f0; \ 161 fp->fp_mant[1] = f1; \ 162 fp->fp_mant[2] = f2; \ 163 fp->fp_mant[3] = f3; \ 164 return (FPC_NUM) 165 166 /* 167 * 32-bit single precision -> fpn. 168 * We assume a single occupies at most (64-FP_LG) bits in the internal 169 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 170 */ 171 int 172 fpu_stof(fp, i) 173 register struct fpn *fp; 174 register u_int i; 175 { 176 register int exp; 177 register u_int frac, f0, f1; 178 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 179 180 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 181 frac = i & mask(SNG_FRACBITS); 182 f0 = frac >> SNG_SHIFT; 183 f1 = frac << (32 - SNG_SHIFT); 184 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 185 } 186 187 /* 188 * 64-bit double -> fpn. 189 * We assume this uses at most (96-FP_LG) bits. 190 */ 191 int 192 fpu_dtof(fp, i, j) 193 register struct fpn *fp; 194 register u_int i, j; 195 { 196 register int exp; 197 register u_int frac, f0, f1, f2; 198 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 199 200 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 201 frac = i & mask(DBL_FRACBITS - 32); 202 f0 = frac >> DBL_SHIFT; 203 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 204 f2 = j << (32 - DBL_SHIFT); 205 frac |= j; 206 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 207 } 208 209 /* 210 * 128-bit extended -> fpn. 211 */ 212 int 213 fpu_qtof(fp, i, j, k, l) 214 register struct fpn *fp; 215 register u_int i, j, k, l; 216 { 217 register int exp; 218 register u_int frac, f0, f1, f2, f3; 219 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */ 220 221 /* 222 * Note that ext and fpn `line up', hence no shifting needed. 223 */ 224 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 225 frac = i & mask(EXT_FRACBITS - 3 * 32); 226 f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT)); 227 f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT)); 228 f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT)); 229 f3 = l << EXT_SHIFT; 230 frac |= j | k | l; 231 FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3); 232 } 233 234 /* 235 * Explode the contents of a register / regpair / regquad. 236 * If the input is a signalling NaN, an NV (invalid) exception 237 * will be set. (Note that nothing but NV can occur until ALU 238 * operations are performed.) 239 */ 240 void 241 fpu_explode(fe, fp, type, reg) 242 register struct fpemu *fe; 243 register struct fpn *fp; 244 int type, reg; 245 { 246 register u_int s, *space; 247 #ifdef SUN4U 248 u_int64_t l, *xspace; 249 250 xspace = (u_int64_t *)&fe->fe_fpstate->fs_regs[reg & ~1]; 251 l = xspace[0]; 252 #endif /* SUN4U */ 253 space = &fe->fe_fpstate->fs_regs[reg]; 254 s = space[0]; 255 fp->fp_sign = s >> 31; 256 fp->fp_sticky = 0; 257 DPRINTF(FPE_INSN, ("fpu_explode: ")); 258 switch (type) { 259 #ifdef SUN4U 260 case FTYPE_LNG: 261 DPRINTF(FPE_INSN, ("LNG: %llx", l)); 262 s = fpu_xtof(fp, l); 263 break; 264 #endif /* SUN4U */ 265 266 case FTYPE_INT: 267 DPRINTF(FPE_INSN, ("INT: %x", s)); 268 s = fpu_itof(fp, s); 269 break; 270 271 case FTYPE_SNG: 272 DPRINTF(FPE_INSN, ("SNG: %x", s)); 273 s = fpu_stof(fp, s); 274 break; 275 276 case FTYPE_DBL: 277 DPRINTF(FPE_INSN, ("DBL: %x %x", s, space[1])); 278 s = fpu_dtof(fp, s, space[1]); 279 break; 280 281 case FTYPE_EXT: 282 DPRINTF(FPE_INSN, ("EXT: %x %x %x %x", s, space[1], 283 space[2], space[3])); 284 s = fpu_qtof(fp, s, space[1], space[2], space[3]); 285 break; 286 287 default: 288 panic("fpu_explode"); 289 } 290 DPRINTF(FPE_INSN, ("\n")); 291 292 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 293 /* 294 * Input is a signalling NaN. All operations that return 295 * an input NaN operand put it through a ``NaN conversion'', 296 * which basically just means ``turn on the quiet bit''. 297 * We do this here so that all NaNs internally look quiet 298 * (we can tell signalling ones by their class). 299 */ 300 fp->fp_mant[0] |= FP_QUIETBIT; 301 fe->fe_cx = FSR_NV; /* assert invalid operand */ 302 s = FPC_SNAN; 303 } 304 fp->fp_class = s; 305 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' : 306 ((type == FTYPE_INT) ? 'i' : 307 ((type == FTYPE_SNG) ? 's' : 308 ((type == FTYPE_DBL) ? 'd' : 309 ((type == FTYPE_EXT) ? 'q' : '?')))), 310 reg)); 311 DUMPFPN(FPE_REG, fp); 312 DPRINTF(FPE_REG, ("\n")); 313 } 314