1 /* $OpenBSD: pyro.c,v 1.23 2011/07/06 22:26:44 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 5 * Copyright (c) 2003 Henric Jungheim 6 * Copyright (c) 2007 Mark Kettenis 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/errno.h> 34 #include <sys/malloc.h> 35 #include <sys/systm.h> 36 37 #define _SPARC_BUS_DMA_PRIVATE 38 #include <machine/bus.h> 39 #include <machine/autoconf.h> 40 #include <machine/openfirm.h> 41 42 #ifdef DDB 43 #include <machine/db_machdep.h> 44 #endif 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 49 #include <sparc64/dev/iommureg.h> 50 #include <sparc64/dev/iommuvar.h> 51 #include <sparc64/dev/msivar.h> 52 #include <sparc64/dev/pyrovar.h> 53 54 #ifdef DEBUG 55 #define PDB_PROM 0x01 56 #define PDB_BUSMAP 0x02 57 #define PDB_INTR 0x04 58 #define PDB_CONF 0x08 59 int pyro_debug = ~0; 60 #define DPRINTF(l, s) do { if (pyro_debug & l) printf s; } while (0) 61 #else 62 #define DPRINTF(l, s) 63 #endif 64 65 #define FIRE_EQ_BASE_ADDR 0x10000 66 #define FIRE_EQ_CNTRL_SET 0x11000 67 #define FIRE_EQ_CTRL_SET_EN 0x0000100000000000UL 68 #define FIRE_EQ_CNTRL_CLEAR 0x11200 69 #define FIRE_EQ_STATE 0x11400 70 #define FIRE_EQ_TAIL 0x11600 71 #define FIRE_EQ_HEAD 0x11800 72 #define FIRE_MSI_MAP 0x20000 73 #define FIRE_MSI_MAP_V 0x8000000000000000UL 74 #define FIRE_MSI_MAP_EQWR_N 0x4000000000000000UL 75 #define FIRE_MSI_MAP_EQNUM 0x000000000000003fUL 76 #define FIRE_MSI_CLEAR 0x28000 77 #define FIRE_MSI_CLEAR_EQWR_N 0x4000000000000000UL 78 #define FIRE_INTRMONDO_DATA0 0x2c000 79 #define FIRE_INTRMONDO_DATA1 0x2c008 80 #define FIRE_MSI32_ADDR 0x34000 81 #define FIRE_MSI64_ADDR 0x34008 82 83 #define FIRE_RESET_GEN 0x7010 84 85 #define FIRE_RESET_GEN_XIR 0x0000000000000002UL 86 87 #define FIRE_INTRMAP_INT_CNTRL_NUM_MASK 0x000003c0 88 #define FIRE_INTRMAP_INT_CNTRL_NUM0 0x00000040 89 #define FIRE_INTRMAP_INT_CNTRL_NUM1 0x00000080 90 #define FIRE_INTRMAP_INT_CNTRL_NUM2 0x00000100 91 #define FIRE_INTRMAP_INT_CNTRL_NUM3 0x00000200 92 #define FIRE_INTRMAP_T_JPID_SHIFT 26 93 #define FIRE_INTRMAP_T_JPID_MASK 0x7c000000 94 95 #define OBERON_INTRMAP_T_DESTID_SHIFT 21 96 #define OBERON_INTRMAP_T_DESTID_MASK 0x7fe00000 97 98 extern struct sparc_pci_chipset _sparc_pci_chipset; 99 100 int pyro_match(struct device *, void *, void *); 101 void pyro_attach(struct device *, struct device *, void *); 102 void pyro_init(struct pyro_softc *, int); 103 void pyro_init_iommu(struct pyro_softc *, struct pyro_pbm *); 104 void pyro_init_msi(struct pyro_softc *, struct pyro_pbm *); 105 int pyro_print(void *, const char *); 106 107 pci_chipset_tag_t pyro_alloc_chipset(struct pyro_pbm *, int, 108 pci_chipset_tag_t); 109 bus_space_tag_t pyro_alloc_mem_tag(struct pyro_pbm *); 110 bus_space_tag_t pyro_alloc_io_tag(struct pyro_pbm *); 111 bus_space_tag_t pyro_alloc_config_tag(struct pyro_pbm *); 112 bus_space_tag_t _pyro_alloc_bus_tag(struct pyro_pbm *, const char *, 113 int, int, int); 114 bus_dma_tag_t pyro_alloc_dma_tag(struct pyro_pbm *); 115 116 int pyro_conf_size(pci_chipset_tag_t, pcitag_t); 117 pcireg_t pyro_conf_read(pci_chipset_tag_t, pcitag_t, int); 118 void pyro_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 119 120 int pyro_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 121 int _pyro_bus_map(bus_space_tag_t, bus_space_tag_t, bus_addr_t, 122 bus_size_t, int, bus_space_handle_t *); 123 paddr_t _pyro_bus_mmap(bus_space_tag_t, bus_space_tag_t, bus_addr_t, off_t, 124 int, int); 125 void *_pyro_intr_establish(bus_space_tag_t, bus_space_tag_t, int, int, int, 126 int (*)(void *), void *, const char *); 127 void pyro_msi_ack(struct intrhand *); 128 129 int pyro_msi_eq_intr(void *); 130 131 int pyro_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, int, 132 bus_size_t, bus_size_t, int, bus_dmamap_t *); 133 134 #ifdef DDB 135 void pyro_xir(void *, int); 136 #endif 137 138 int 139 pyro_match(struct device *parent, void *match, void *aux) 140 { 141 struct mainbus_attach_args *ma = aux; 142 char *str; 143 144 if (strcmp(ma->ma_name, "pci") != 0) 145 return (0); 146 147 str = getpropstring(ma->ma_node, "compatible"); 148 if (strcmp(str, "pciex108e,80f0") == 0 || 149 strcmp(str, "pciex108e,80f8") == 0) 150 return (1); 151 152 return (0); 153 } 154 155 void 156 pyro_attach(struct device *parent, struct device *self, void *aux) 157 { 158 struct pyro_softc *sc = (struct pyro_softc *)self; 159 struct mainbus_attach_args *ma = aux; 160 char *str; 161 int busa; 162 163 sc->sc_node = ma->ma_node; 164 sc->sc_dmat = ma->ma_dmatag; 165 sc->sc_bust = ma->ma_bustag; 166 sc->sc_csr = ma->ma_reg[0].ur_paddr; 167 sc->sc_xbc = ma->ma_reg[1].ur_paddr; 168 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 169 170 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 171 busa = 1; 172 else 173 busa = 0; 174 175 if (bus_space_map(sc->sc_bust, sc->sc_csr, 176 ma->ma_reg[0].ur_len, 0, &sc->sc_csrh)) { 177 printf(": failed to map csr registers\n"); 178 return; 179 } 180 181 if (bus_space_map(sc->sc_bust, sc->sc_xbc, 182 ma->ma_reg[1].ur_len, 0, &sc->sc_xbch)) { 183 printf(": failed to map xbc registers\n"); 184 return; 185 } 186 187 str = getpropstring(ma->ma_node, "compatible"); 188 if (strcmp(str, "pciex108e,80f8") == 0) 189 sc->sc_oberon = 1; 190 191 pyro_init(sc, busa); 192 } 193 194 void 195 pyro_init(struct pyro_softc *sc, int busa) 196 { 197 struct pyro_pbm *pbm; 198 struct pcibus_attach_args pba; 199 int *busranges = NULL, nranges; 200 201 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 202 if (pbm == NULL) 203 panic("pyro: can't alloc pyro pbm"); 204 205 pbm->pp_sc = sc; 206 pbm->pp_bus_a = busa; 207 208 if (getprop(sc->sc_node, "ranges", sizeof(struct pyro_range), 209 &pbm->pp_nrange, (void **)&pbm->pp_range)) 210 panic("pyro: can't get ranges"); 211 212 if (getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 213 (void **)&busranges)) 214 panic("pyro: can't get bus-range"); 215 216 printf(": \"%s\", rev %d, ign %x, bus %c %d to %d\n", 217 sc->sc_oberon ? "Oberon" : "Fire", 218 getpropint(sc->sc_node, "module-revision#", 0), sc->sc_ign, 219 busa ? 'A' : 'B', busranges[0], busranges[1]); 220 221 printf("%s: ", sc->sc_dv.dv_xname); 222 pyro_init_iommu(sc, pbm); 223 224 pbm->pp_memt = pyro_alloc_mem_tag(pbm); 225 pbm->pp_iot = pyro_alloc_io_tag(pbm); 226 pbm->pp_cfgt = pyro_alloc_config_tag(pbm); 227 pbm->pp_dmat = pyro_alloc_dma_tag(pbm); 228 229 pyro_init_msi(sc, pbm); 230 231 if (bus_space_map(pbm->pp_cfgt, 0, 0x10000000, 0, &pbm->pp_cfgh)) 232 panic("pyro: can't map config space"); 233 234 pbm->pp_pc = pyro_alloc_chipset(pbm, sc->sc_node, &_sparc_pci_chipset); 235 236 pbm->pp_pc->bustag = pbm->pp_cfgt; 237 pbm->pp_pc->bushandle = pbm->pp_cfgh; 238 239 bzero(&pba, sizeof(pba)); 240 pba.pba_busname = "pci"; 241 pba.pba_domain = pci_ndomains++; 242 pba.pba_bus = busranges[0]; 243 pba.pba_pc = pbm->pp_pc; 244 pba.pba_flags = pbm->pp_flags; 245 pba.pba_dmat = pbm->pp_dmat; 246 pba.pba_memt = pbm->pp_memt; 247 pba.pba_iot = pbm->pp_iot; 248 pba.pba_pc->conf_size = pyro_conf_size; 249 pba.pba_pc->conf_read = pyro_conf_read; 250 pba.pba_pc->conf_write = pyro_conf_write; 251 pba.pba_pc->intr_map = pyro_intr_map; 252 253 free(busranges, M_DEVBUF); 254 255 #ifdef DDB 256 db_register_xir(pyro_xir, sc); 257 #endif 258 259 config_found(&sc->sc_dv, &pba, pyro_print); 260 } 261 262 void 263 pyro_init_iommu(struct pyro_softc *sc, struct pyro_pbm *pbm) 264 { 265 struct iommu_state *is = &pbm->pp_is; 266 int tsbsize = 7; 267 u_int32_t iobase = -1; 268 char *name; 269 270 is->is_bustag = sc->sc_bust; 271 272 if (bus_space_subregion(is->is_bustag, sc->sc_csrh, 273 0x40000, 0x100, &is->is_iommu)) { 274 panic("pyro: unable to create iommu handle"); 275 } 276 277 is->is_sb[0] = &pbm->pp_sb; 278 is->is_sb[0]->sb_bustag = is->is_bustag; 279 280 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 281 if (name == NULL) 282 panic("couldn't malloc iommu name"); 283 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 284 285 /* On Oberon, we need to flush the cache. */ 286 if (sc->sc_oberon) 287 is->is_flags |= IOMMU_FLUSH_CACHE; 288 289 iommu_init(name, is, tsbsize, iobase); 290 } 291 292 void 293 pyro_init_msi(struct pyro_softc *sc, struct pyro_pbm *pbm) 294 { 295 u_int32_t msi_addr_range[3]; 296 u_int32_t msi_eq_devino[3] = { 0, 36, 24 }; 297 int ihandle; 298 int msis, msi_eq_size; 299 300 /* Don't do MSI on Oberon for now. */ 301 if (sc->sc_oberon) 302 return; 303 304 if (OF_getprop(sc->sc_node, "msi-address-ranges", 305 msi_addr_range, sizeof(msi_addr_range)) <= 0) 306 return; 307 pbm->pp_msiaddr = msi_addr_range[1]; 308 pbm->pp_msiaddr |= ((bus_addr_t)msi_addr_range[0]) << 32; 309 310 msis = getpropint(sc->sc_node, "#msi", 256); 311 pbm->pp_msi = malloc(msis * sizeof(*pbm->pp_msi), 312 M_DEVBUF, M_NOWAIT | M_ZERO); 313 if (pbm->pp_msi == NULL) 314 return; 315 316 msi_eq_size = getpropint(sc->sc_node, "msi-eq-size", 256); 317 pbm->pp_meq = msi_eq_alloc(pbm->pp_dmat, msi_eq_size); 318 if (pbm->pp_meq == NULL) 319 goto free_table; 320 321 bzero(pbm->pp_meq->meq_va, 322 pbm->pp_meq->meq_nentries * sizeof(struct pyro_msi_msg)); 323 324 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_BASE_ADDR, 325 pbm->pp_meq->meq_map->dm_segs[0].ds_addr); 326 327 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 328 FIRE_INTRMONDO_DATA0, sc->sc_ign); 329 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 330 FIRE_INTRMONDO_DATA1, 0); 331 332 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_MSI32_ADDR, 333 pbm->pp_msiaddr); 334 335 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_HEAD, 0); 336 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_TAIL, 0); 337 338 OF_getprop(sc->sc_node, "msi-eq-to-devino", 339 msi_eq_devino, sizeof(msi_eq_devino)); 340 341 ihandle = msi_eq_devino[2] | sc->sc_ign; 342 if (_pyro_intr_establish(pbm->pp_memt, sc->sc_bust, ihandle, 343 IPL_HIGH, 0, pyro_msi_eq_intr, pbm, sc->sc_dv.dv_xname) == NULL) 344 goto free_table; 345 346 /* Enable EQ. */ 347 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_CNTRL_SET, 348 FIRE_EQ_CTRL_SET_EN); 349 350 pbm->pp_flags |= PCI_FLAGS_MSI_ENABLED; 351 return; 352 353 free_table: 354 free(pbm->pp_msi, M_DEVBUF); 355 } 356 357 int 358 pyro_print(void *aux, const char *p) 359 { 360 if (p == NULL) 361 return (UNCONF); 362 return (QUIET); 363 } 364 365 int 366 pyro_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 367 { 368 return PCIE_CONFIG_SPACE_SIZE; 369 } 370 371 pcireg_t 372 pyro_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 373 { 374 struct cpu_info *ci = curcpu(); 375 pcireg_t val; 376 int s; 377 378 s = splhigh(); 379 membar(Sync); 380 ci->ci_pci_probe = 1; 381 val = bus_space_read_4(pc->bustag, pc->bushandle, 382 (PCITAG_OFFSET(tag) << 4) + reg); 383 membar(Sync); 384 if (ci->ci_pci_fault) 385 val = 0xffffffff; 386 ci->ci_pci_probe = ci->ci_pci_fault = 0; 387 splx(s); 388 389 return (val); 390 } 391 392 void 393 pyro_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 394 { 395 bus_space_write_4(pc->bustag, pc->bushandle, 396 (PCITAG_OFFSET(tag) << 4) + reg, data); 397 } 398 399 /* 400 * Bus-specific interrupt mapping 401 */ 402 int 403 pyro_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 404 { 405 struct pyro_pbm *pp = pa->pa_pc->cookie; 406 struct pyro_softc *sc = pp->pp_sc; 407 u_int dev; 408 409 if (*ihp != (pci_intr_handle_t)-1) { 410 *ihp |= sc->sc_ign; 411 return (0); 412 } 413 414 /* 415 * We didn't find a PROM mapping for this interrupt. Try to 416 * construct one ourselves based on the swizzled interrupt pin 417 * and the interrupt mapping for PCI slots documented in the 418 * UltraSPARC-IIi User's Manual. 419 */ 420 421 if (pa->pa_intrpin == 0) 422 return (-1); 423 424 /* 425 * This deserves some documentation. Should anyone 426 * have anything official looking, please speak up. 427 */ 428 dev = pa->pa_device - 1; 429 430 *ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT; 431 *ihp |= (dev << 2) & INTMAP_PCISLOT; 432 *ihp |= sc->sc_ign; 433 434 return (0); 435 } 436 437 bus_space_tag_t 438 pyro_alloc_mem_tag(struct pyro_pbm *pp) 439 { 440 return (_pyro_alloc_bus_tag(pp, "mem", 441 0x02, /* 32-bit mem space (where's the #define???) */ 442 ASI_PRIMARY, ASI_PRIMARY_LITTLE)); 443 } 444 445 bus_space_tag_t 446 pyro_alloc_io_tag(struct pyro_pbm *pp) 447 { 448 return (_pyro_alloc_bus_tag(pp, "io", 449 0x01, /* IO space (where's the #define???) */ 450 ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED)); 451 } 452 453 bus_space_tag_t 454 pyro_alloc_config_tag(struct pyro_pbm *pp) 455 { 456 return (_pyro_alloc_bus_tag(pp, "cfg", 457 0x00, /* Config space (where's the #define???) */ 458 ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED)); 459 } 460 461 bus_space_tag_t 462 _pyro_alloc_bus_tag(struct pyro_pbm *pbm, const char *name, int ss, 463 int asi, int sasi) 464 { 465 struct pyro_softc *sc = pbm->pp_sc; 466 struct sparc_bus_space_tag *bt; 467 468 bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO); 469 if (bt == NULL) 470 panic("pyro: could not allocate bus tag"); 471 472 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)", 473 sc->sc_dv.dv_xname, name, ss, asi); 474 475 bt->cookie = pbm; 476 bt->parent = sc->sc_bust; 477 bt->default_type = ss; 478 bt->asi = asi; 479 bt->sasi = sasi; 480 bt->sparc_bus_map = _pyro_bus_map; 481 bt->sparc_bus_mmap = _pyro_bus_mmap; 482 bt->sparc_intr_establish = _pyro_intr_establish; 483 return (bt); 484 } 485 486 bus_dma_tag_t 487 pyro_alloc_dma_tag(struct pyro_pbm *pbm) 488 { 489 struct pyro_softc *sc = pbm->pp_sc; 490 bus_dma_tag_t dt, pdt = sc->sc_dmat; 491 492 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 493 if (dt == NULL) 494 panic("pyro: could not alloc dma tag"); 495 496 dt->_cookie = pbm; 497 dt->_parent = pdt; 498 dt->_dmamap_create = pyro_dmamap_create; 499 dt->_dmamap_destroy = iommu_dvmamap_destroy; 500 dt->_dmamap_load = iommu_dvmamap_load; 501 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 502 dt->_dmamap_unload = iommu_dvmamap_unload; 503 dt->_dmamap_sync = iommu_dvmamap_sync; 504 dt->_dmamem_alloc = iommu_dvmamem_alloc; 505 dt->_dmamem_free = iommu_dvmamem_free; 506 return (dt); 507 } 508 509 pci_chipset_tag_t 510 pyro_alloc_chipset(struct pyro_pbm *pbm, int node, pci_chipset_tag_t pc) 511 { 512 pci_chipset_tag_t npc; 513 514 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 515 if (npc == NULL) 516 panic("pyro: could not allocate pci_chipset_tag_t"); 517 memcpy(npc, pc, sizeof *pc); 518 npc->cookie = pbm; 519 npc->rootnode = node; 520 return (npc); 521 } 522 523 int 524 pyro_dmamap_create(bus_dma_tag_t t, bus_dma_tag_t t0, bus_size_t size, 525 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 526 bus_dmamap_t *dmamp) 527 { 528 struct pyro_pbm *pp = t->_cookie; 529 530 return (iommu_dvmamap_create(t, t0, &pp->pp_sb, size, nsegments, 531 maxsegsz, boundary, flags, dmamp)); 532 } 533 534 int 535 _pyro_bus_map(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t offset, 536 bus_size_t size, int flags, bus_space_handle_t *hp) 537 { 538 struct pyro_pbm *pbm = t->cookie; 539 int i, ss; 540 541 DPRINTF(PDB_BUSMAP, ("_pyro_bus_map: type %d off %qx sz %qx flags %d", 542 t->default_type, 543 (unsigned long long)offset, 544 (unsigned long long)size, 545 flags)); 546 547 ss = t->default_type; 548 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 549 550 if (t->parent == 0 || t->parent->sparc_bus_map == 0) { 551 printf("\n_pyro_bus_map: invalid parent"); 552 return (EINVAL); 553 } 554 555 if (flags & BUS_SPACE_MAP_PROMADDRESS) { 556 return ((*t->parent->sparc_bus_map) 557 (t, t0, offset, size, flags, hp)); 558 } 559 560 for (i = 0; i < pbm->pp_nrange; i++) { 561 bus_addr_t paddr; 562 563 if (((pbm->pp_range[i].cspace >> 24) & 0x03) != ss) 564 continue; 565 566 paddr = pbm->pp_range[i].phys_lo + offset; 567 paddr |= ((bus_addr_t)pbm->pp_range[i].phys_hi) << 32; 568 return ((*t->parent->sparc_bus_map) 569 (t, t0, paddr, size, flags, hp)); 570 } 571 572 return (EINVAL); 573 } 574 575 paddr_t 576 _pyro_bus_mmap(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t paddr, 577 off_t off, int prot, int flags) 578 { 579 bus_addr_t offset = paddr; 580 struct pyro_pbm *pbm = t->cookie; 581 int i, ss; 582 583 ss = t->default_type; 584 585 DPRINTF(PDB_BUSMAP, ("_pyro_bus_mmap: prot %d flags %d pa %qx\n", 586 prot, flags, (unsigned long long)paddr)); 587 588 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) { 589 printf("\n_pyro_bus_mmap: invalid parent"); 590 return (-1); 591 } 592 593 for (i = 0; i < pbm->pp_nrange; i++) { 594 bus_addr_t paddr; 595 596 if (((pbm->pp_range[i].cspace >> 24) & 0x03) != ss) 597 continue; 598 599 paddr = pbm->pp_range[i].phys_lo + offset; 600 paddr |= ((bus_addr_t)pbm->pp_range[i].phys_hi) << 32; 601 return ((*t->parent->sparc_bus_mmap) 602 (t, t0, paddr, off, prot, flags)); 603 } 604 605 return (-1); 606 } 607 608 void * 609 _pyro_intr_establish(bus_space_tag_t t, bus_space_tag_t t0, int ihandle, 610 int level, int flags, int (*handler)(void *), void *arg, const char *what) 611 { 612 struct pyro_pbm *pbm = t->cookie; 613 struct pyro_softc *sc = pbm->pp_sc; 614 struct intrhand *ih = NULL; 615 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 616 int ino; 617 618 if (ihandle & PCI_INTR_MSI) { 619 pci_chipset_tag_t pc = pbm->pp_pc; 620 pcitag_t tag = ihandle & ~PCI_INTR_MSI; 621 int msinum = pbm->pp_msinum++; 622 u_int64_t reg; 623 624 ih = bus_intr_allocate(t0, handler, arg, ihandle, level, 625 NULL, NULL, what); 626 if (ih == NULL) 627 return (NULL); 628 629 if (ih->ih_name) 630 evcount_attach(&ih->ih_count, ih->ih_name, NULL); 631 else 632 evcount_attach(&ih->ih_count, "unknown", NULL); 633 634 ih->ih_ack = pyro_msi_ack; 635 636 pbm->pp_msi[msinum] = ih; 637 ih->ih_number = msinum; 638 639 pci_msi_enable(pc, tag, pbm->pp_msiaddr, msinum); 640 641 /* Map MSI to the right EQ and mark it as valid. */ 642 reg = bus_space_read_8(sc->sc_bust, sc->sc_csrh, 643 FIRE_MSI_MAP + msinum * 8); 644 reg &= ~FIRE_MSI_MAP_EQNUM; 645 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 646 FIRE_MSI_MAP + msinum * 8, reg); 647 648 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 649 FIRE_MSI_CLEAR + msinum * 8, FIRE_MSI_CLEAR_EQWR_N); 650 651 reg = bus_space_read_8(sc->sc_bust, sc->sc_csrh, 652 FIRE_MSI_MAP + msinum * 8); 653 reg |= FIRE_MSI_MAP_V; 654 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 655 FIRE_MSI_MAP + msinum * 8, reg); 656 657 return (ih); 658 } 659 660 ino = INTINO(ihandle); 661 662 if (level == IPL_NONE) 663 level = INTLEV(ihandle); 664 if (level == IPL_NONE) { 665 printf(": no IPL, setting IPL 2.\n"); 666 level = 2; 667 } 668 669 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) == 0) { 670 u_int64_t *imap, *iclr; 671 672 imap = bus_space_vaddr(sc->sc_bust, sc->sc_csrh) + 0x1000; 673 iclr = bus_space_vaddr(sc->sc_bust, sc->sc_csrh) + 0x1400; 674 intrmapptr = &imap[ino]; 675 intrclrptr = &iclr[ino]; 676 ino |= INTVEC(ihandle); 677 } 678 679 ih = bus_intr_allocate(t0, handler, arg, ino, level, intrmapptr, 680 intrclrptr, what); 681 if (ih == NULL) 682 return (NULL); 683 684 intr_establish(ih->ih_pil, ih); 685 686 if (intrmapptr != NULL) { 687 u_int64_t intrmap; 688 689 intrmap = *intrmapptr; 690 intrmap &= ~FIRE_INTRMAP_INT_CNTRL_NUM_MASK; 691 intrmap |= FIRE_INTRMAP_INT_CNTRL_NUM0; 692 if (sc->sc_oberon) { 693 intrmap &= ~OBERON_INTRMAP_T_DESTID_MASK; 694 intrmap |= CPU_JUPITERID << 695 OBERON_INTRMAP_T_DESTID_SHIFT; 696 } else { 697 intrmap &= ~FIRE_INTRMAP_T_JPID_MASK; 698 intrmap |= CPU_UPAID << FIRE_INTRMAP_T_JPID_SHIFT; 699 } 700 intrmap |= INTMAP_V; 701 *intrmapptr = intrmap; 702 intrmap = *intrmapptr; 703 ih->ih_number |= intrmap & INTMAP_INR; 704 } 705 706 return (ih); 707 } 708 709 void 710 pyro_msi_ack(struct intrhand *ih) 711 { 712 } 713 714 int 715 pyro_msi_eq_intr(void *arg) 716 { 717 struct pyro_pbm *pbm = arg; 718 struct pyro_softc *sc = pbm->pp_sc; 719 struct msi_eq *meq = pbm->pp_meq; 720 struct pyro_msi_msg *msg; 721 uint64_t head, tail; 722 struct intrhand *ih; 723 int msinum; 724 725 head = bus_space_read_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_HEAD); 726 tail = bus_space_read_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_TAIL); 727 728 if (head == tail) 729 return (0); 730 731 while (head != tail) { 732 msg = (struct pyro_msi_msg *)meq->meq_va; 733 734 if (msg[head].mm_type == 0) 735 break; 736 msg[head].mm_type = 0; 737 738 msinum = msg[head].mm_data; 739 ih = pbm->pp_msi[msinum]; 740 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 741 FIRE_MSI_CLEAR + msinum * 8, FIRE_MSI_CLEAR_EQWR_N); 742 743 send_softint(-1, ih->ih_pil, ih); 744 745 head += 1; 746 head &= (meq->meq_nentries - 1); 747 } 748 749 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_HEAD, head); 750 751 return (1); 752 } 753 754 #ifdef DDB 755 void 756 pyro_xir(void *arg, int cpu) 757 { 758 struct pyro_softc *sc = arg; 759 760 bus_space_write_8(sc->sc_bust, sc->sc_xbch, FIRE_RESET_GEN, 761 FIRE_RESET_GEN_XIR); 762 } 763 #endif 764 765 const struct cfattach pyro_ca = { 766 sizeof(struct pyro_softc), pyro_match, pyro_attach 767 }; 768 769 struct cfdriver pyro_cd = { 770 NULL, "pyro", DV_DULL 771 }; 772