1 /* $OpenBSD: pyro.c,v 1.33 2019/06/25 22:30:56 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 5 * Copyright (c) 2003 Henric Jungheim 6 * Copyright (c) 2007 Mark Kettenis 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/errno.h> 34 #include <sys/malloc.h> 35 #include <sys/systm.h> 36 37 #define _SPARC_BUS_DMA_PRIVATE 38 #include <machine/bus.h> 39 #include <machine/autoconf.h> 40 #include <machine/openfirm.h> 41 42 #ifdef DDB 43 #include <machine/db_machdep.h> 44 #endif 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 49 #include <sparc64/dev/iommureg.h> 50 #include <sparc64/dev/iommuvar.h> 51 #include <sparc64/dev/msivar.h> 52 #include <sparc64/dev/pyrovar.h> 53 54 #ifdef DEBUG 55 #define PDB_PROM 0x01 56 #define PDB_BUSMAP 0x02 57 #define PDB_INTR 0x04 58 #define PDB_CONF 0x08 59 int pyro_debug = ~0; 60 #define DPRINTF(l, s) do { if (pyro_debug & l) printf s; } while (0) 61 #else 62 #define DPRINTF(l, s) 63 #endif 64 65 #define FIRE_EQ_BASE_ADDR 0x10000 66 #define FIRE_EQ_CNTRL_SET 0x11000 67 #define FIRE_EQ_CTRL_SET_EN 0x0000100000000000UL 68 #define FIRE_EQ_CNTRL_CLEAR 0x11200 69 #define FIRE_EQ_STATE 0x11400 70 #define FIRE_EQ_TAIL 0x11600 71 #define FIRE_EQ_HEAD 0x11800 72 #define FIRE_MSI_MAP 0x20000 73 #define FIRE_MSI_MAP_V 0x8000000000000000UL 74 #define FIRE_MSI_MAP_EQWR_N 0x4000000000000000UL 75 #define FIRE_MSI_MAP_EQNUM 0x000000000000003fUL 76 #define FIRE_MSI_CLEAR 0x28000 77 #define FIRE_MSI_CLEAR_EQWR_N 0x4000000000000000UL 78 #define FIRE_INTRMONDO_DATA0 0x2c000 79 #define FIRE_INTRMONDO_DATA1 0x2c008 80 #define FIRE_MSI32_ADDR 0x34000 81 #define FIRE_MSI64_ADDR 0x34008 82 83 #define FIRE_RESET_GEN 0x7010 84 85 #define FIRE_RESET_GEN_XIR 0x0000000000000002UL 86 87 #define FIRE_INTRMAP_INT_CNTRL_NUM_MASK 0x000003c0 88 #define FIRE_INTRMAP_INT_CNTRL_NUM0 0x00000040 89 #define FIRE_INTRMAP_INT_CNTRL_NUM1 0x00000080 90 #define FIRE_INTRMAP_INT_CNTRL_NUM2 0x00000100 91 #define FIRE_INTRMAP_INT_CNTRL_NUM3 0x00000200 92 #define FIRE_INTRMAP_T_JPID_SHIFT 26 93 #define FIRE_INTRMAP_T_JPID_MASK 0x7c000000 94 95 #define OBERON_INTRMAP_T_DESTID_SHIFT 21 96 #define OBERON_INTRMAP_T_DESTID_MASK 0x7fe00000 97 98 extern struct sparc_pci_chipset _sparc_pci_chipset; 99 100 int pyro_match(struct device *, void *, void *); 101 void pyro_attach(struct device *, struct device *, void *); 102 void pyro_init(struct pyro_softc *, int); 103 void pyro_init_iommu(struct pyro_softc *, struct pyro_pbm *); 104 void pyro_init_msi(struct pyro_softc *, struct pyro_pbm *); 105 int pyro_print(void *, const char *); 106 107 pci_chipset_tag_t pyro_alloc_chipset(struct pyro_pbm *, int, 108 pci_chipset_tag_t); 109 bus_space_tag_t pyro_alloc_mem_tag(struct pyro_pbm *); 110 bus_space_tag_t pyro_alloc_io_tag(struct pyro_pbm *); 111 bus_space_tag_t pyro_alloc_config_tag(struct pyro_pbm *); 112 bus_space_tag_t pyro_alloc_bus_tag(struct pyro_pbm *, const char *, 113 int, int, int); 114 bus_dma_tag_t pyro_alloc_dma_tag(struct pyro_pbm *); 115 116 int pyro_conf_size(pci_chipset_tag_t, pcitag_t); 117 pcireg_t pyro_conf_read(pci_chipset_tag_t, pcitag_t, int); 118 void pyro_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 119 120 int pyro_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 121 int pyro_bus_map(bus_space_tag_t, bus_space_tag_t, bus_addr_t, 122 bus_size_t, int, bus_space_handle_t *); 123 paddr_t pyro_bus_mmap(bus_space_tag_t, bus_space_tag_t, bus_addr_t, off_t, 124 int, int); 125 void *pyro_intr_establish(bus_space_tag_t, bus_space_tag_t, int, int, int, 126 int (*)(void *), void *, const char *); 127 void pyro_msi_ack(struct intrhand *); 128 129 int pyro_msi_eq_intr(void *); 130 131 int pyro_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, int, 132 bus_size_t, bus_size_t, int, bus_dmamap_t *); 133 134 void pyro_iommu_enable(struct iommu_state *); 135 136 const struct iommu_hw iommu_hw_fire = { 137 .ihw_enable = pyro_iommu_enable, 138 139 .ihw_dvma_pa = 0x000007ffffffffffUL, 140 141 .ihw_bypass = 0xfffc000000000000UL, 142 .ihw_bypass_nc = 0x0000080000000000UL, 143 .ihw_bypass_ro = 0, 144 }; 145 146 const struct iommu_hw iommu_hw_oberon = { 147 .ihw_enable = pyro_iommu_enable, 148 149 .ihw_dvma_pa = 0x00007fffffffffffUL, 150 151 .ihw_bypass = 0x7ffc000000000000UL, 152 .ihw_bypass_nc = 0x0000800000000000UL, 153 .ihw_bypass_ro = 0x8000000000000000UL, 154 155 .ihw_flags = IOMMU_HW_FLUSH_CACHE, 156 }; 157 158 #ifdef DDB 159 void pyro_xir(void *, int); 160 #endif 161 162 int 163 pyro_match(struct device *parent, void *match, void *aux) 164 { 165 struct mainbus_attach_args *ma = aux; 166 char *str; 167 168 if (strcmp(ma->ma_name, "pci") != 0) 169 return (0); 170 171 str = getpropstring(ma->ma_node, "compatible"); 172 if (strcmp(str, "pciex108e,80f0") == 0 || 173 strcmp(str, "pciex108e,80f8") == 0) 174 return (1); 175 176 return (0); 177 } 178 179 void 180 pyro_attach(struct device *parent, struct device *self, void *aux) 181 { 182 struct pyro_softc *sc = (struct pyro_softc *)self; 183 struct mainbus_attach_args *ma = aux; 184 char *str; 185 int busa; 186 187 sc->sc_node = ma->ma_node; 188 sc->sc_dmat = ma->ma_dmatag; 189 sc->sc_bust = ma->ma_bustag; 190 sc->sc_csr = ma->ma_reg[0].ur_paddr; 191 sc->sc_xbc = ma->ma_reg[1].ur_paddr; 192 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 193 194 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 195 busa = 1; 196 else 197 busa = 0; 198 199 if (bus_space_map(sc->sc_bust, sc->sc_csr, 200 ma->ma_reg[0].ur_len, 0, &sc->sc_csrh)) { 201 printf(": failed to map csr registers\n"); 202 return; 203 } 204 205 if (bus_space_map(sc->sc_bust, sc->sc_xbc, 206 ma->ma_reg[1].ur_len, 0, &sc->sc_xbch)) { 207 printf(": failed to map xbc registers\n"); 208 return; 209 } 210 211 str = getpropstring(ma->ma_node, "compatible"); 212 if (strcmp(str, "pciex108e,80f8") == 0) 213 sc->sc_oberon = 1; 214 215 pyro_init(sc, busa); 216 } 217 218 void 219 pyro_init(struct pyro_softc *sc, int busa) 220 { 221 struct pyro_pbm *pbm; 222 struct pcibus_attach_args pba; 223 int *busranges = NULL, nranges; 224 225 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 226 if (pbm == NULL) 227 panic("pyro: can't alloc pyro pbm"); 228 229 pbm->pp_sc = sc; 230 pbm->pp_bus_a = busa; 231 232 if (getprop(sc->sc_node, "ranges", sizeof(struct pyro_range), 233 &pbm->pp_nrange, (void **)&pbm->pp_range)) 234 panic("pyro: can't get ranges"); 235 236 if (getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 237 (void **)&busranges)) 238 panic("pyro: can't get bus-range"); 239 240 printf(": \"%s\", rev %d, ign %x, bus %c %d to %d\n", 241 sc->sc_oberon ? "Oberon" : "Fire", 242 getpropint(sc->sc_node, "module-revision#", 0), sc->sc_ign, 243 busa ? 'A' : 'B', busranges[0], busranges[1]); 244 245 printf("%s: ", sc->sc_dv.dv_xname); 246 pyro_init_iommu(sc, pbm); 247 248 pbm->pp_memt = pyro_alloc_mem_tag(pbm); 249 pbm->pp_iot = pyro_alloc_io_tag(pbm); 250 pbm->pp_cfgt = pyro_alloc_config_tag(pbm); 251 pbm->pp_dmat = pyro_alloc_dma_tag(pbm); 252 253 pyro_init_msi(sc, pbm); 254 255 if (bus_space_map(pbm->pp_cfgt, 0, 0x10000000, 0, &pbm->pp_cfgh)) 256 panic("pyro: can't map config space"); 257 258 pbm->pp_pc = pyro_alloc_chipset(pbm, sc->sc_node, &_sparc_pci_chipset); 259 260 pbm->pp_pc->bustag = pbm->pp_cfgt; 261 pbm->pp_pc->bushandle = pbm->pp_cfgh; 262 263 bzero(&pba, sizeof(pba)); 264 pba.pba_busname = "pci"; 265 pba.pba_domain = pci_ndomains++; 266 pba.pba_bus = busranges[0]; 267 pba.pba_pc = pbm->pp_pc; 268 pba.pba_flags = pbm->pp_flags; 269 pba.pba_dmat = pbm->pp_dmat; 270 pba.pba_memt = pbm->pp_memt; 271 pba.pba_iot = pbm->pp_iot; 272 pba.pba_pc->conf_size = pyro_conf_size; 273 pba.pba_pc->conf_read = pyro_conf_read; 274 pba.pba_pc->conf_write = pyro_conf_write; 275 pba.pba_pc->intr_map = pyro_intr_map; 276 277 free(busranges, M_DEVBUF, 0); 278 279 #ifdef DDB 280 db_register_xir(pyro_xir, sc); 281 #endif 282 283 config_found(&sc->sc_dv, &pba, pyro_print); 284 } 285 286 void 287 pyro_init_iommu(struct pyro_softc *sc, struct pyro_pbm *pbm) 288 { 289 struct iommu_state *is = &pbm->pp_is; 290 int tsbsize = 7; 291 u_int32_t iobase = -1; 292 char *name; 293 const struct iommu_hw *ihw = &iommu_hw_fire; 294 295 is->is_bustag = sc->sc_bust; 296 297 if (bus_space_subregion(is->is_bustag, sc->sc_csrh, 298 0x40000, 0x100, &is->is_iommu)) { 299 panic("pyro: unable to create iommu handle"); 300 } 301 302 is->is_sb[0] = &pbm->pp_sb; 303 is->is_sb[0]->sb_bustag = is->is_bustag; 304 305 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 306 if (name == NULL) 307 panic("couldn't malloc iommu name"); 308 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 309 310 if (sc->sc_oberon) 311 ihw = &iommu_hw_oberon; 312 313 iommu_init(name, ihw, is, tsbsize, iobase); 314 } 315 316 void 317 pyro_iommu_enable(struct iommu_state *is) 318 { 319 unsigned long cr; 320 321 cr = IOMMUREG_READ(is, iommu_cr); 322 cr |= IOMMUCR_FIRE_BE | IOMMUCR_FIRE_SE | IOMMUCR_FIRE_CM_EN | 323 IOMMUCR_FIRE_TE; 324 325 IOMMUREG_WRITE(is, iommu_tsb, is->is_ptsb | is->is_tsbsize); 326 IOMMUREG_WRITE(is, iommu_cr, cr); 327 } 328 329 void 330 pyro_init_msi(struct pyro_softc *sc, struct pyro_pbm *pbm) 331 { 332 u_int32_t msi_addr_range[3]; 333 u_int32_t msi_eq_devino[3] = { 0, 36, 24 }; 334 int ihandle; 335 int msis, msi_eq_size; 336 337 if (OF_getprop(sc->sc_node, "msi-address-ranges", 338 msi_addr_range, sizeof(msi_addr_range)) <= 0) 339 return; 340 pbm->pp_msiaddr = msi_addr_range[1]; 341 pbm->pp_msiaddr |= ((bus_addr_t)msi_addr_range[0]) << 32; 342 343 msis = getpropint(sc->sc_node, "#msi", 256); 344 pbm->pp_msi = mallocarray(msis, sizeof(*pbm->pp_msi), M_DEVBUF, 345 M_NOWAIT | M_ZERO); 346 if (pbm->pp_msi == NULL) 347 return; 348 349 msi_eq_size = getpropint(sc->sc_node, "msi-eq-size", 256); 350 pbm->pp_meq = msi_eq_alloc(pbm->pp_dmat, msi_eq_size); 351 if (pbm->pp_meq == NULL) 352 goto free_table; 353 354 bzero(pbm->pp_meq->meq_va, 355 pbm->pp_meq->meq_nentries * sizeof(struct pyro_msi_msg)); 356 357 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_BASE_ADDR, 358 pbm->pp_meq->meq_map->dm_segs[0].ds_addr); 359 360 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 361 FIRE_INTRMONDO_DATA0, sc->sc_ign); 362 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 363 FIRE_INTRMONDO_DATA1, 0); 364 365 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_MSI32_ADDR, 366 pbm->pp_msiaddr); 367 368 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_HEAD, 0); 369 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_TAIL, 0); 370 371 OF_getprop(sc->sc_node, "msi-eq-to-devino", 372 msi_eq_devino, sizeof(msi_eq_devino)); 373 374 ihandle = msi_eq_devino[2] | sc->sc_ign; 375 if (pyro_intr_establish(pbm->pp_memt, sc->sc_bust, ihandle, 376 IPL_HIGH, 0, pyro_msi_eq_intr, pbm, sc->sc_dv.dv_xname) == NULL) 377 goto free_table; 378 379 /* Enable EQ. */ 380 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_CNTRL_SET, 381 FIRE_EQ_CTRL_SET_EN); 382 383 pbm->pp_flags |= PCI_FLAGS_MSI_ENABLED; 384 return; 385 386 free_table: 387 free(pbm->pp_msi, M_DEVBUF, 0); 388 } 389 390 int 391 pyro_print(void *aux, const char *p) 392 { 393 if (p == NULL) 394 return (UNCONF); 395 return (QUIET); 396 } 397 398 int 399 pyro_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 400 { 401 return PCIE_CONFIG_SPACE_SIZE; 402 } 403 404 pcireg_t 405 pyro_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 406 { 407 struct cpu_info *ci = curcpu(); 408 pcireg_t val; 409 int s; 410 411 s = splhigh(); 412 __membar("#Sync"); 413 ci->ci_pci_probe = 1; 414 val = bus_space_read_4(pc->bustag, pc->bushandle, 415 (PCITAG_OFFSET(tag) << 4) + reg); 416 __membar("#Sync"); 417 if (ci->ci_pci_fault) 418 val = 0xffffffff; 419 ci->ci_pci_probe = ci->ci_pci_fault = 0; 420 splx(s); 421 422 return (val); 423 } 424 425 void 426 pyro_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 427 { 428 bus_space_write_4(pc->bustag, pc->bushandle, 429 (PCITAG_OFFSET(tag) << 4) + reg, data); 430 } 431 432 /* 433 * Bus-specific interrupt mapping 434 */ 435 int 436 pyro_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 437 { 438 struct pyro_pbm *pp = pa->pa_pc->cookie; 439 struct pyro_softc *sc = pp->pp_sc; 440 u_int dev; 441 442 if (*ihp != (pci_intr_handle_t)-1) { 443 *ihp |= sc->sc_ign; 444 return (0); 445 } 446 447 /* 448 * We didn't find a PROM mapping for this interrupt. Try to 449 * construct one ourselves based on the swizzled interrupt pin 450 * and the interrupt mapping for PCI slots documented in the 451 * UltraSPARC-IIi User's Manual. 452 */ 453 454 if (pa->pa_intrpin == 0) 455 return (-1); 456 457 /* 458 * This deserves some documentation. Should anyone 459 * have anything official looking, please speak up. 460 */ 461 dev = pa->pa_device - 1; 462 463 *ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT; 464 *ihp |= (dev << 2) & INTMAP_PCISLOT; 465 *ihp |= sc->sc_ign; 466 467 return (0); 468 } 469 470 bus_space_tag_t 471 pyro_alloc_mem_tag(struct pyro_pbm *pp) 472 { 473 return (pyro_alloc_bus_tag(pp, "mem", 474 0x02, /* 32-bit mem space (where's the #define???) */ 475 ASI_PRIMARY, ASI_PRIMARY_LITTLE)); 476 } 477 478 bus_space_tag_t 479 pyro_alloc_io_tag(struct pyro_pbm *pp) 480 { 481 return (pyro_alloc_bus_tag(pp, "io", 482 0x01, /* IO space (where's the #define???) */ 483 ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED)); 484 } 485 486 bus_space_tag_t 487 pyro_alloc_config_tag(struct pyro_pbm *pp) 488 { 489 return (pyro_alloc_bus_tag(pp, "cfg", 490 0x00, /* Config space (where's the #define???) */ 491 ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED)); 492 } 493 494 bus_space_tag_t 495 pyro_alloc_bus_tag(struct pyro_pbm *pbm, const char *name, int ss, 496 int asi, int sasi) 497 { 498 struct pyro_softc *sc = pbm->pp_sc; 499 struct sparc_bus_space_tag *bt; 500 501 bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO); 502 if (bt == NULL) 503 panic("pyro: could not allocate bus tag"); 504 505 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)", 506 sc->sc_dv.dv_xname, name, ss, asi); 507 508 bt->cookie = pbm; 509 bt->parent = sc->sc_bust; 510 bt->default_type = ss; 511 bt->asi = asi; 512 bt->sasi = sasi; 513 bt->sparc_bus_map = pyro_bus_map; 514 bt->sparc_bus_mmap = pyro_bus_mmap; 515 bt->sparc_intr_establish = pyro_intr_establish; 516 return (bt); 517 } 518 519 bus_dma_tag_t 520 pyro_alloc_dma_tag(struct pyro_pbm *pbm) 521 { 522 struct pyro_softc *sc = pbm->pp_sc; 523 bus_dma_tag_t dt, pdt = sc->sc_dmat; 524 525 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 526 if (dt == NULL) 527 panic("pyro: could not alloc dma tag"); 528 529 dt->_cookie = pbm; 530 dt->_parent = pdt; 531 dt->_dmamap_create = pyro_dmamap_create; 532 dt->_dmamap_destroy = iommu_dvmamap_destroy; 533 dt->_dmamap_load = iommu_dvmamap_load; 534 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 535 dt->_dmamap_unload = iommu_dvmamap_unload; 536 dt->_dmamap_sync = iommu_dvmamap_sync; 537 dt->_dmamem_alloc = iommu_dvmamem_alloc; 538 dt->_dmamem_free = iommu_dvmamem_free; 539 return (dt); 540 } 541 542 pci_chipset_tag_t 543 pyro_alloc_chipset(struct pyro_pbm *pbm, int node, pci_chipset_tag_t pc) 544 { 545 pci_chipset_tag_t npc; 546 547 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 548 if (npc == NULL) 549 panic("pyro: could not allocate pci_chipset_tag_t"); 550 memcpy(npc, pc, sizeof *pc); 551 npc->cookie = pbm; 552 npc->rootnode = node; 553 return (npc); 554 } 555 556 int 557 pyro_dmamap_create(bus_dma_tag_t t, bus_dma_tag_t t0, bus_size_t size, 558 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 559 bus_dmamap_t *dmamp) 560 { 561 struct pyro_pbm *pp = t->_cookie; 562 563 return (iommu_dvmamap_create(t, t0, &pp->pp_sb, size, nsegments, 564 maxsegsz, boundary, flags, dmamp)); 565 } 566 567 int 568 pyro_bus_map(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t offset, 569 bus_size_t size, int flags, bus_space_handle_t *hp) 570 { 571 struct pyro_pbm *pbm = t->cookie; 572 int i, ss; 573 574 DPRINTF(PDB_BUSMAP, ("pyro_bus_map: type %d off %llx sz %llx flags %d", 575 t->default_type, 576 (unsigned long long)offset, 577 (unsigned long long)size, 578 flags)); 579 580 ss = t->default_type; 581 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 582 583 if (t->parent == 0 || t->parent->sparc_bus_map == 0) { 584 printf("\npyro_bus_map: invalid parent"); 585 return (EINVAL); 586 } 587 588 if (flags & BUS_SPACE_MAP_PROMADDRESS) { 589 return ((*t->parent->sparc_bus_map) 590 (t, t0, offset, size, flags, hp)); 591 } 592 593 for (i = 0; i < pbm->pp_nrange; i++) { 594 bus_addr_t paddr; 595 596 if (((pbm->pp_range[i].cspace >> 24) & 0x03) != ss) 597 continue; 598 599 paddr = pbm->pp_range[i].phys_lo + offset; 600 paddr |= ((bus_addr_t)pbm->pp_range[i].phys_hi) << 32; 601 return ((*t->parent->sparc_bus_map) 602 (t, t0, paddr, size, flags, hp)); 603 } 604 605 return (EINVAL); 606 } 607 608 paddr_t 609 pyro_bus_mmap(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t paddr, 610 off_t off, int prot, int flags) 611 { 612 bus_addr_t offset = paddr; 613 struct pyro_pbm *pbm = t->cookie; 614 int i, ss; 615 616 ss = t->default_type; 617 618 DPRINTF(PDB_BUSMAP, ("pyro_bus_mmap: prot %d flags %d pa %llx\n", 619 prot, flags, (unsigned long long)paddr)); 620 621 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) { 622 printf("\npyro_bus_mmap: invalid parent"); 623 return (-1); 624 } 625 626 for (i = 0; i < pbm->pp_nrange; i++) { 627 bus_addr_t paddr; 628 629 if (((pbm->pp_range[i].cspace >> 24) & 0x03) != ss) 630 continue; 631 632 paddr = pbm->pp_range[i].phys_lo + offset; 633 paddr |= ((bus_addr_t)pbm->pp_range[i].phys_hi) << 32; 634 return ((*t->parent->sparc_bus_mmap) 635 (t, t0, paddr, off, prot, flags)); 636 } 637 638 return (-1); 639 } 640 641 void * 642 pyro_intr_establish(bus_space_tag_t t, bus_space_tag_t t0, int ihandle, 643 int level, int flags, int (*handler)(void *), void *arg, const char *what) 644 { 645 struct pyro_pbm *pbm = t->cookie; 646 struct pyro_softc *sc = pbm->pp_sc; 647 struct intrhand *ih = NULL; 648 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 649 int ino; 650 651 if (PCI_INTR_TYPE(ihandle) != PCI_INTR_INTX) { 652 pci_chipset_tag_t pc = pbm->pp_pc; 653 pcitag_t tag = PCI_INTR_TAG(ihandle); 654 int msinum = pbm->pp_msinum++; 655 u_int64_t reg; 656 657 ih = bus_intr_allocate(t0, handler, arg, ihandle, level, 658 NULL, NULL, what); 659 if (ih == NULL) 660 return (NULL); 661 662 evcount_attach(&ih->ih_count, ih->ih_name, NULL); 663 664 ih->ih_ack = pyro_msi_ack; 665 666 pbm->pp_msi[msinum] = ih; 667 ih->ih_number = msinum; 668 669 if (flags & BUS_INTR_ESTABLISH_MPSAFE) 670 ih->ih_mpsafe = 1; 671 672 switch (PCI_INTR_TYPE(ihandle)) { 673 case PCI_INTR_MSI: 674 pci_msi_enable(pc, tag, pbm->pp_msiaddr, msinum); 675 break; 676 case PCI_INTR_MSIX: 677 pci_msix_enable(pc, tag, pbm->pp_memt, 678 PCI_INTR_VEC(ihandle), pbm->pp_msiaddr, msinum); 679 break; 680 } 681 682 /* Map MSI to the right EQ and mark it as valid. */ 683 reg = bus_space_read_8(sc->sc_bust, sc->sc_csrh, 684 FIRE_MSI_MAP + msinum * 8); 685 reg &= ~FIRE_MSI_MAP_EQNUM; 686 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 687 FIRE_MSI_MAP + msinum * 8, reg); 688 689 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 690 FIRE_MSI_CLEAR + msinum * 8, FIRE_MSI_CLEAR_EQWR_N); 691 692 reg = bus_space_read_8(sc->sc_bust, sc->sc_csrh, 693 FIRE_MSI_MAP + msinum * 8); 694 reg |= FIRE_MSI_MAP_V; 695 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 696 FIRE_MSI_MAP + msinum * 8, reg); 697 698 return (ih); 699 } 700 701 ino = INTINO(ihandle); 702 703 if (level == IPL_NONE) 704 level = INTLEV(ihandle); 705 if (level == IPL_NONE) { 706 printf(": no IPL, setting IPL 2.\n"); 707 level = 2; 708 } 709 710 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) == 0) { 711 u_int64_t *imap, *iclr; 712 713 imap = bus_space_vaddr(sc->sc_bust, sc->sc_csrh) + 0x1000; 714 iclr = bus_space_vaddr(sc->sc_bust, sc->sc_csrh) + 0x1400; 715 intrmapptr = &imap[ino]; 716 intrclrptr = &iclr[ino]; 717 ino |= INTVEC(ihandle); 718 } 719 720 ih = bus_intr_allocate(t0, handler, arg, ino, level, intrmapptr, 721 intrclrptr, what); 722 if (ih == NULL) 723 return (NULL); 724 725 if (flags & BUS_INTR_ESTABLISH_MPSAFE) 726 ih->ih_mpsafe = 1; 727 728 intr_establish(ih->ih_pil, ih); 729 730 if (intrmapptr != NULL) { 731 u_int64_t intrmap; 732 733 intrmap = *intrmapptr; 734 intrmap &= ~FIRE_INTRMAP_INT_CNTRL_NUM_MASK; 735 intrmap |= FIRE_INTRMAP_INT_CNTRL_NUM0; 736 if (sc->sc_oberon) { 737 intrmap &= ~OBERON_INTRMAP_T_DESTID_MASK; 738 intrmap |= CPU_JUPITERID << 739 OBERON_INTRMAP_T_DESTID_SHIFT; 740 } else { 741 intrmap &= ~FIRE_INTRMAP_T_JPID_MASK; 742 intrmap |= CPU_UPAID << FIRE_INTRMAP_T_JPID_SHIFT; 743 } 744 intrmap |= INTMAP_V; 745 *intrmapptr = intrmap; 746 intrmap = *intrmapptr; 747 ih->ih_number |= intrmap & INTMAP_INR; 748 } 749 750 return (ih); 751 } 752 753 void 754 pyro_msi_ack(struct intrhand *ih) 755 { 756 } 757 758 int 759 pyro_msi_eq_intr(void *arg) 760 { 761 struct pyro_pbm *pbm = arg; 762 struct pyro_softc *sc = pbm->pp_sc; 763 struct msi_eq *meq = pbm->pp_meq; 764 struct pyro_msi_msg *msg; 765 uint64_t head, tail; 766 struct intrhand *ih; 767 int msinum; 768 769 head = bus_space_read_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_HEAD); 770 tail = bus_space_read_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_TAIL); 771 772 if (head == tail) 773 return (0); 774 775 while (head != tail) { 776 msg = (struct pyro_msi_msg *)meq->meq_va; 777 778 if (msg[head].mm_type == 0) 779 break; 780 msg[head].mm_type = 0; 781 782 msinum = msg[head].mm_data; 783 ih = pbm->pp_msi[msinum]; 784 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 785 FIRE_MSI_CLEAR + msinum * 8, FIRE_MSI_CLEAR_EQWR_N); 786 787 send_softint(-1, ih->ih_pil, ih); 788 789 head += 1; 790 head &= (meq->meq_nentries - 1); 791 } 792 793 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_HEAD, head); 794 795 return (1); 796 } 797 798 #ifdef DDB 799 void 800 pyro_xir(void *arg, int cpu) 801 { 802 struct pyro_softc *sc = arg; 803 804 bus_space_write_8(sc->sc_bust, sc->sc_xbch, FIRE_RESET_GEN, 805 FIRE_RESET_GEN_XIR); 806 } 807 #endif 808 809 const struct cfattach pyro_ca = { 810 sizeof(struct pyro_softc), pyro_match, pyro_attach 811 }; 812 813 struct cfdriver pyro_cd = { 814 NULL, "pyro", DV_DULL 815 }; 816