1 /* $OpenBSD: pyro.c,v 1.14 2008/07/12 13:08:04 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 5 * Copyright (c) 2003 Henric Jungheim 6 * Copyright (c) 2007 Mark Kettenis 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/errno.h> 34 #include <sys/malloc.h> 35 #include <sys/systm.h> 36 37 #define _SPARC_BUS_DMA_PRIVATE 38 #include <machine/bus.h> 39 #include <machine/autoconf.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 44 #include <sparc64/dev/iommureg.h> 45 #include <sparc64/dev/iommuvar.h> 46 #include <sparc64/dev/pyrovar.h> 47 48 #ifdef DEBUG 49 #define PDB_PROM 0x01 50 #define PDB_BUSMAP 0x02 51 #define PDB_INTR 0x04 52 #define PDB_CONF 0x08 53 int pyro_debug = ~0; 54 #define DPRINTF(l, s) do { if (pyro_debug & l) printf s; } while (0) 55 #else 56 #define DPRINTF(l, s) 57 #endif 58 59 #define FIRE_INTRMAP_INT_CNTRL_NUM_MASK 0x000003c0 60 #define FIRE_INTRMAP_INT_CNTRL_NUM0 0x00000040 61 #define FIRE_INTRMAP_INT_CNTRL_NUM1 0x00000080 62 #define FIRE_INTRMAP_INT_CNTRL_NUM2 0x00000100 63 #define FIRE_INTRMAP_INT_CNTRL_NUM3 0x00000200 64 #define FIRE_INTRMAP_T_JPID_SHIFT 26 65 #define FIRE_INTRMAP_T_JPID_MASK 0x7c000000 66 67 #define OBERON_INTRMAP_T_DESTID_SHIFT 21 68 #define OBERON_INTRMAP_T_DESTID_MASK 0x7fe00000 69 70 extern struct sparc_pci_chipset _sparc_pci_chipset; 71 72 int pyro_match(struct device *, void *, void *); 73 void pyro_attach(struct device *, struct device *, void *); 74 void pyro_init(struct pyro_softc *, int); 75 void pyro_init_iommu(struct pyro_softc *, struct pyro_pbm *); 76 int pyro_print(void *, const char *); 77 78 pci_chipset_tag_t pyro_alloc_chipset(struct pyro_pbm *, int, 79 pci_chipset_tag_t); 80 bus_space_tag_t pyro_alloc_mem_tag(struct pyro_pbm *); 81 bus_space_tag_t pyro_alloc_io_tag(struct pyro_pbm *); 82 bus_space_tag_t pyro_alloc_config_tag(struct pyro_pbm *); 83 bus_space_tag_t _pyro_alloc_bus_tag(struct pyro_pbm *, const char *, 84 int, int, int); 85 bus_dma_tag_t pyro_alloc_dma_tag(struct pyro_pbm *); 86 87 pcireg_t pyro_conf_read(pci_chipset_tag_t, pcitag_t, int); 88 void pyro_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 89 90 int pyro_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 91 int _pyro_bus_map(bus_space_tag_t, bus_space_tag_t, bus_addr_t, 92 bus_size_t, int, bus_space_handle_t *); 93 paddr_t _pyro_bus_mmap(bus_space_tag_t, bus_space_tag_t, bus_addr_t, off_t, 94 int, int); 95 void *_pyro_intr_establish(bus_space_tag_t, bus_space_tag_t, int, int, int, 96 int (*)(void *), void *, const char *); 97 98 int pyro_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, int, 99 bus_size_t, bus_size_t, int, bus_dmamap_t *); 100 101 int 102 pyro_match(struct device *parent, void *match, void *aux) 103 { 104 struct mainbus_attach_args *ma = aux; 105 char *str; 106 107 if (strcmp(ma->ma_name, "pci") != 0) 108 return (0); 109 110 str = getpropstring(ma->ma_node, "compatible"); 111 if (strcmp(str, "pciex108e,80f0") == 0 || 112 strcmp(str, "pciex108e,80f8") == 0) 113 return (1); 114 115 return (0); 116 } 117 118 void 119 pyro_attach(struct device *parent, struct device *self, void *aux) 120 { 121 struct pyro_softc *sc = (struct pyro_softc *)self; 122 struct mainbus_attach_args *ma = aux; 123 char *str; 124 int busa; 125 126 sc->sc_node = ma->ma_node; 127 sc->sc_dmat = ma->ma_dmatag; 128 sc->sc_bust = ma->ma_bustag; 129 sc->sc_csr = ma->ma_reg[0].ur_paddr; 130 sc->sc_xbc = ma->ma_reg[1].ur_paddr; 131 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 132 133 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 134 busa = 1; 135 else 136 busa = 0; 137 138 if (bus_space_map(sc->sc_bust, sc->sc_csr, 139 ma->ma_reg[0].ur_len, 0, &sc->sc_csrh)) { 140 printf(": failed to map csr registers\n"); 141 return; 142 } 143 144 if (bus_space_map(sc->sc_bust, sc->sc_xbc, 145 ma->ma_reg[1].ur_len, 0, &sc->sc_xbch)) { 146 printf(": failed to map xbc registers\n"); 147 return; 148 } 149 150 str = getpropstring(ma->ma_node, "compatible"); 151 if (strcmp(str, "pciex108e,80f8") == 0) 152 sc->sc_oberon = 1; 153 154 pyro_init(sc, busa); 155 } 156 157 void 158 pyro_init(struct pyro_softc *sc, int busa) 159 { 160 struct pyro_pbm *pbm; 161 struct pcibus_attach_args pba; 162 int *busranges = NULL, nranges; 163 164 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 165 if (pbm == NULL) 166 panic("pyro: can't alloc pyro pbm"); 167 168 pbm->pp_sc = sc; 169 pbm->pp_bus_a = busa; 170 171 if (getprop(sc->sc_node, "ranges", sizeof(struct pyro_range), 172 &pbm->pp_nrange, (void **)&pbm->pp_range)) 173 panic("pyro: can't get ranges"); 174 175 if (getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 176 (void **)&busranges)) 177 panic("pyro: can't get bus-range"); 178 179 printf(": \"%s\", rev %d, ign %x, bus %c %d to %d\n", 180 sc->sc_oberon ? "Oberon" : "Fire", 181 getpropint(sc->sc_node, "module-revision#", 0), sc->sc_ign, 182 busa ? 'A' : 'B', busranges[0], busranges[1]); 183 184 printf("%s: ", sc->sc_dv.dv_xname); 185 pyro_init_iommu(sc, pbm); 186 187 pbm->pp_memt = pyro_alloc_mem_tag(pbm); 188 pbm->pp_iot = pyro_alloc_io_tag(pbm); 189 pbm->pp_cfgt = pyro_alloc_config_tag(pbm); 190 pbm->pp_dmat = pyro_alloc_dma_tag(pbm); 191 192 if (bus_space_map(pbm->pp_cfgt, 0, 0x10000000, 0, &pbm->pp_cfgh)) 193 panic("pyro: could not map config space"); 194 195 pbm->pp_pc = pyro_alloc_chipset(pbm, sc->sc_node, &_sparc_pci_chipset); 196 197 pbm->pp_pc->bustag = pbm->pp_cfgt; 198 pbm->pp_pc->bushandle = pbm->pp_cfgh; 199 200 pba.pba_busname = "pci"; 201 pba.pba_domain = pci_ndomains++; 202 pba.pba_bus = busranges[0]; 203 pba.pba_bridgetag = NULL; 204 pba.pba_pc = pbm->pp_pc; 205 #if 0 206 pba.pba_flags = pbm->pp_flags; 207 #endif 208 pba.pba_dmat = pbm->pp_dmat; 209 pba.pba_memt = pbm->pp_memt; 210 pba.pba_iot = pbm->pp_iot; 211 pba.pba_pc->conf_read = pyro_conf_read; 212 pba.pba_pc->conf_write = pyro_conf_write; 213 pba.pba_pc->intr_map = pyro_intr_map; 214 215 free(busranges, M_DEVBUF); 216 217 config_found(&sc->sc_dv, &pba, pyro_print); 218 } 219 220 void 221 pyro_init_iommu(struct pyro_softc *sc, struct pyro_pbm *pbm) 222 { 223 struct iommu_state *is = &pbm->pp_is; 224 int tsbsize = 7; 225 u_int32_t iobase = -1; 226 char *name; 227 228 is->is_bustag = sc->sc_bust; 229 230 if (bus_space_subregion(is->is_bustag, sc->sc_csrh, 231 0x40000, 0x100, &is->is_iommu)) { 232 panic("pyro: unable to create iommu handle"); 233 } 234 235 is->is_sb[0] = &pbm->pp_sb; 236 is->is_sb[0]->sb_bustag = is->is_bustag; 237 238 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 239 if (name == NULL) 240 panic("couldn't malloc iommu name"); 241 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 242 243 /* On Oberon, we need to flush the cache. */ 244 if (sc->sc_oberon) 245 is->is_flags |= IOMMU_FLUSH_CACHE; 246 247 iommu_init(name, is, tsbsize, iobase); 248 } 249 250 int 251 pyro_print(void *aux, const char *p) 252 { 253 if (p == NULL) 254 return (UNCONF); 255 return (QUIET); 256 } 257 258 pcireg_t 259 pyro_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 260 { 261 return (bus_space_read_4(pc->bustag, pc->bushandle, 262 (PCITAG_OFFSET(tag) << 4) + reg)); 263 } 264 265 void 266 pyro_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 267 { 268 bus_space_write_4(pc->bustag, pc->bushandle, 269 (PCITAG_OFFSET(tag) << 4) + reg, data); 270 } 271 272 /* 273 * Bus-specific interrupt mapping 274 */ 275 int 276 pyro_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 277 { 278 struct pyro_pbm *pp = pa->pa_pc->cookie; 279 struct pyro_softc *sc = pp->pp_sc; 280 u_int dev; 281 282 if (*ihp != (pci_intr_handle_t)-1) { 283 *ihp |= sc->sc_ign; 284 return (0); 285 } 286 287 /* 288 * We didn't find a PROM mapping for this interrupt. Try to 289 * construct one ourselves based on the swizzled interrupt pin 290 * and the interrupt mapping for PCI slots documented in the 291 * UltraSPARC-IIi User's Manual. 292 */ 293 294 if (pa->pa_intrpin == 0) 295 return (-1); 296 297 /* 298 * This deserves some documentation. Should anyone 299 * have anything official looking, please speak up. 300 */ 301 dev = pa->pa_device - 1; 302 303 *ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT; 304 *ihp |= (dev << 2) & INTMAP_PCISLOT; 305 *ihp |= sc->sc_ign; 306 307 return (0); 308 } 309 310 bus_space_tag_t 311 pyro_alloc_mem_tag(struct pyro_pbm *pp) 312 { 313 return (_pyro_alloc_bus_tag(pp, "mem", 314 0x02, /* 32-bit mem space (where's the #define???) */ 315 ASI_PRIMARY, ASI_PRIMARY_LITTLE)); 316 } 317 318 bus_space_tag_t 319 pyro_alloc_io_tag(struct pyro_pbm *pp) 320 { 321 return (_pyro_alloc_bus_tag(pp, "io", 322 0x01, /* IO space (where's the #define???) */ 323 ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED)); 324 } 325 326 bus_space_tag_t 327 pyro_alloc_config_tag(struct pyro_pbm *pp) 328 { 329 return (_pyro_alloc_bus_tag(pp, "cfg", 330 0x00, /* Config space (where's the #define???) */ 331 ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED)); 332 } 333 334 bus_space_tag_t 335 _pyro_alloc_bus_tag(struct pyro_pbm *pbm, const char *name, int ss, 336 int asi, int sasi) 337 { 338 struct pyro_softc *sc = pbm->pp_sc; 339 struct sparc_bus_space_tag *bt; 340 341 bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO); 342 if (bt == NULL) 343 panic("pyro: could not allocate bus tag"); 344 345 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)", 346 sc->sc_dv.dv_xname, name, ss, asi); 347 348 bt->cookie = pbm; 349 bt->parent = sc->sc_bust; 350 bt->default_type = ss; 351 bt->asi = asi; 352 bt->sasi = sasi; 353 bt->sparc_bus_map = _pyro_bus_map; 354 bt->sparc_bus_mmap = _pyro_bus_mmap; 355 bt->sparc_intr_establish = _pyro_intr_establish; 356 return (bt); 357 } 358 359 bus_dma_tag_t 360 pyro_alloc_dma_tag(struct pyro_pbm *pbm) 361 { 362 struct pyro_softc *sc = pbm->pp_sc; 363 bus_dma_tag_t dt, pdt = sc->sc_dmat; 364 365 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 366 if (dt == NULL) 367 panic("pyro: could not alloc dma tag"); 368 369 dt->_cookie = pbm; 370 dt->_parent = pdt; 371 dt->_dmamap_create = pyro_dmamap_create; 372 dt->_dmamap_destroy = iommu_dvmamap_destroy; 373 dt->_dmamap_load = iommu_dvmamap_load; 374 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 375 dt->_dmamap_unload = iommu_dvmamap_unload; 376 dt->_dmamap_sync = iommu_dvmamap_sync; 377 dt->_dmamem_alloc = iommu_dvmamem_alloc; 378 dt->_dmamem_free = iommu_dvmamem_free; 379 dt->_dmamem_map = iommu_dvmamem_map; 380 dt->_dmamem_unmap = iommu_dvmamem_unmap; 381 return (dt); 382 } 383 384 pci_chipset_tag_t 385 pyro_alloc_chipset(struct pyro_pbm *pbm, int node, pci_chipset_tag_t pc) 386 { 387 pci_chipset_tag_t npc; 388 389 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 390 if (npc == NULL) 391 panic("pyro: could not allocate pci_chipset_tag_t"); 392 memcpy(npc, pc, sizeof *pc); 393 npc->cookie = pbm; 394 npc->rootnode = node; 395 return (npc); 396 } 397 398 int 399 pyro_dmamap_create(bus_dma_tag_t t, bus_dma_tag_t t0, bus_size_t size, 400 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 401 bus_dmamap_t *dmamp) 402 { 403 struct pyro_pbm *pp = t->_cookie; 404 405 return (iommu_dvmamap_create(t, t0, &pp->pp_sb, size, nsegments, 406 maxsegsz, boundary, flags, dmamp)); 407 } 408 409 int 410 _pyro_bus_map(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t offset, 411 bus_size_t size, int flags, bus_space_handle_t *hp) 412 { 413 struct pyro_pbm *pbm = t->cookie; 414 int i, ss; 415 416 DPRINTF(PDB_BUSMAP, ("_pyro_bus_map: type %d off %qx sz %qx flags %d", 417 t->default_type, 418 (unsigned long long)offset, 419 (unsigned long long)size, 420 flags)); 421 422 ss = t->default_type; 423 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 424 425 if (t->parent == 0 || t->parent->sparc_bus_map == 0) { 426 printf("\n_pyro_bus_map: invalid parent"); 427 return (EINVAL); 428 } 429 430 if (flags & BUS_SPACE_MAP_PROMADDRESS) { 431 return ((*t->parent->sparc_bus_map) 432 (t, t0, offset, size, flags, hp)); 433 } 434 435 for (i = 0; i < pbm->pp_nrange; i++) { 436 bus_addr_t paddr; 437 438 if (((pbm->pp_range[i].cspace >> 24) & 0x03) != ss) 439 continue; 440 441 paddr = pbm->pp_range[i].phys_lo + offset; 442 paddr |= ((bus_addr_t)pbm->pp_range[i].phys_hi) << 32; 443 return ((*t->parent->sparc_bus_map) 444 (t, t0, paddr, size, flags, hp)); 445 } 446 447 return (EINVAL); 448 } 449 450 paddr_t 451 _pyro_bus_mmap(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t paddr, 452 off_t off, int prot, int flags) 453 { 454 bus_addr_t offset = paddr; 455 struct pyro_pbm *pbm = t->cookie; 456 int i, ss; 457 458 ss = t->default_type; 459 460 DPRINTF(PDB_BUSMAP, ("_pyro_bus_mmap: prot %d flags %d pa %qx\n", 461 prot, flags, (unsigned long long)paddr)); 462 463 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) { 464 printf("\n_pyro_bus_mmap: invalid parent"); 465 return (-1); 466 } 467 468 for (i = 0; i < pbm->pp_nrange; i++) { 469 bus_addr_t paddr; 470 471 if (((pbm->pp_range[i].cspace >> 24) & 0x03) != ss) 472 continue; 473 474 paddr = pbm->pp_range[i].phys_lo + offset; 475 paddr |= ((bus_addr_t)pbm->pp_range[i].phys_hi<<32); 476 return ((*t->parent->sparc_bus_mmap) 477 (t, t0, paddr, off, prot, flags)); 478 } 479 480 return (-1); 481 } 482 483 void * 484 _pyro_intr_establish(bus_space_tag_t t, bus_space_tag_t t0, int ihandle, 485 int level, int flags, int (*handler)(void *), void *arg, const char *what) 486 { 487 struct pyro_pbm *pbm = t->cookie; 488 struct pyro_softc *sc = pbm->pp_sc; 489 struct intrhand *ih = NULL; 490 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 491 int ino; 492 493 ino = INTINO(ihandle); 494 495 if (level == IPL_NONE) 496 level = INTLEV(ihandle); 497 if (level == IPL_NONE) { 498 printf(": no IPL, setting IPL 2.\n"); 499 level = 2; 500 } 501 502 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) == 0) { 503 u_int64_t *imap, *iclr; 504 505 imap = bus_space_vaddr(sc->sc_bust, sc->sc_csrh) + 0x1000; 506 iclr = bus_space_vaddr(sc->sc_bust, sc->sc_csrh) + 0x1400; 507 intrmapptr = &imap[ino]; 508 intrclrptr = &iclr[ino]; 509 ino |= INTVEC(ihandle); 510 } 511 512 ih = bus_intr_allocate(t0, handler, arg, ino, level, intrmapptr, 513 intrclrptr, what); 514 if (ih == NULL) 515 return (NULL); 516 517 intr_establish(ih->ih_pil, ih); 518 519 if (intrmapptr != NULL) { 520 u_int64_t intrmap; 521 522 intrmap = *intrmapptr; 523 intrmap &= ~FIRE_INTRMAP_INT_CNTRL_NUM_MASK; 524 intrmap |= FIRE_INTRMAP_INT_CNTRL_NUM0; 525 if (sc->sc_oberon) { 526 intrmap &= ~OBERON_INTRMAP_T_DESTID_MASK; 527 intrmap |= CPU_JUPITERID << 528 OBERON_INTRMAP_T_DESTID_SHIFT; 529 } else { 530 intrmap &= ~FIRE_INTRMAP_T_JPID_MASK; 531 intrmap |= CPU_UPAID << FIRE_INTRMAP_T_JPID_SHIFT; 532 } 533 intrmap |= INTMAP_V; 534 *intrmapptr = intrmap; 535 intrmap = *intrmapptr; 536 ih->ih_number |= intrmap & INTMAP_INR; 537 } 538 539 return (ih); 540 } 541 542 const struct cfattach pyro_ca = { 543 sizeof(struct pyro_softc), pyro_match, pyro_attach 544 }; 545 546 struct cfdriver pyro_cd = { 547 NULL, "pyro", DV_DULL 548 }; 549