1 /* $OpenBSD: pyro.c,v 1.28 2014/12/09 06:58:29 doug Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 5 * Copyright (c) 2003 Henric Jungheim 6 * Copyright (c) 2007 Mark Kettenis 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/device.h> 33 #include <sys/errno.h> 34 #include <sys/malloc.h> 35 #include <sys/systm.h> 36 37 #define _SPARC_BUS_DMA_PRIVATE 38 #include <machine/bus.h> 39 #include <machine/autoconf.h> 40 #include <machine/openfirm.h> 41 42 #ifdef DDB 43 #include <machine/db_machdep.h> 44 #endif 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 49 #include <sparc64/dev/iommureg.h> 50 #include <sparc64/dev/iommuvar.h> 51 #include <sparc64/dev/msivar.h> 52 #include <sparc64/dev/pyrovar.h> 53 54 #ifdef DEBUG 55 #define PDB_PROM 0x01 56 #define PDB_BUSMAP 0x02 57 #define PDB_INTR 0x04 58 #define PDB_CONF 0x08 59 int pyro_debug = ~0; 60 #define DPRINTF(l, s) do { if (pyro_debug & l) printf s; } while (0) 61 #else 62 #define DPRINTF(l, s) 63 #endif 64 65 #define FIRE_EQ_BASE_ADDR 0x10000 66 #define FIRE_EQ_CNTRL_SET 0x11000 67 #define FIRE_EQ_CTRL_SET_EN 0x0000100000000000UL 68 #define FIRE_EQ_CNTRL_CLEAR 0x11200 69 #define FIRE_EQ_STATE 0x11400 70 #define FIRE_EQ_TAIL 0x11600 71 #define FIRE_EQ_HEAD 0x11800 72 #define FIRE_MSI_MAP 0x20000 73 #define FIRE_MSI_MAP_V 0x8000000000000000UL 74 #define FIRE_MSI_MAP_EQWR_N 0x4000000000000000UL 75 #define FIRE_MSI_MAP_EQNUM 0x000000000000003fUL 76 #define FIRE_MSI_CLEAR 0x28000 77 #define FIRE_MSI_CLEAR_EQWR_N 0x4000000000000000UL 78 #define FIRE_INTRMONDO_DATA0 0x2c000 79 #define FIRE_INTRMONDO_DATA1 0x2c008 80 #define FIRE_MSI32_ADDR 0x34000 81 #define FIRE_MSI64_ADDR 0x34008 82 83 #define FIRE_RESET_GEN 0x7010 84 85 #define FIRE_RESET_GEN_XIR 0x0000000000000002UL 86 87 #define FIRE_INTRMAP_INT_CNTRL_NUM_MASK 0x000003c0 88 #define FIRE_INTRMAP_INT_CNTRL_NUM0 0x00000040 89 #define FIRE_INTRMAP_INT_CNTRL_NUM1 0x00000080 90 #define FIRE_INTRMAP_INT_CNTRL_NUM2 0x00000100 91 #define FIRE_INTRMAP_INT_CNTRL_NUM3 0x00000200 92 #define FIRE_INTRMAP_T_JPID_SHIFT 26 93 #define FIRE_INTRMAP_T_JPID_MASK 0x7c000000 94 95 #define OBERON_INTRMAP_T_DESTID_SHIFT 21 96 #define OBERON_INTRMAP_T_DESTID_MASK 0x7fe00000 97 98 extern struct sparc_pci_chipset _sparc_pci_chipset; 99 100 int pyro_match(struct device *, void *, void *); 101 void pyro_attach(struct device *, struct device *, void *); 102 void pyro_init(struct pyro_softc *, int); 103 void pyro_init_iommu(struct pyro_softc *, struct pyro_pbm *); 104 void pyro_init_msi(struct pyro_softc *, struct pyro_pbm *); 105 int pyro_print(void *, const char *); 106 107 pci_chipset_tag_t pyro_alloc_chipset(struct pyro_pbm *, int, 108 pci_chipset_tag_t); 109 bus_space_tag_t pyro_alloc_mem_tag(struct pyro_pbm *); 110 bus_space_tag_t pyro_alloc_io_tag(struct pyro_pbm *); 111 bus_space_tag_t pyro_alloc_config_tag(struct pyro_pbm *); 112 bus_space_tag_t pyro_alloc_bus_tag(struct pyro_pbm *, const char *, 113 int, int, int); 114 bus_dma_tag_t pyro_alloc_dma_tag(struct pyro_pbm *); 115 116 int pyro_conf_size(pci_chipset_tag_t, pcitag_t); 117 pcireg_t pyro_conf_read(pci_chipset_tag_t, pcitag_t, int); 118 void pyro_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 119 120 int pyro_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 121 int pyro_bus_map(bus_space_tag_t, bus_space_tag_t, bus_addr_t, 122 bus_size_t, int, bus_space_handle_t *); 123 paddr_t pyro_bus_mmap(bus_space_tag_t, bus_space_tag_t, bus_addr_t, off_t, 124 int, int); 125 void *pyro_intr_establish(bus_space_tag_t, bus_space_tag_t, int, int, int, 126 int (*)(void *), void *, const char *); 127 void pyro_msi_ack(struct intrhand *); 128 129 int pyro_msi_eq_intr(void *); 130 131 int pyro_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, int, 132 bus_size_t, bus_size_t, int, bus_dmamap_t *); 133 134 #ifdef DDB 135 void pyro_xir(void *, int); 136 #endif 137 138 int 139 pyro_match(struct device *parent, void *match, void *aux) 140 { 141 struct mainbus_attach_args *ma = aux; 142 char *str; 143 144 if (strcmp(ma->ma_name, "pci") != 0) 145 return (0); 146 147 str = getpropstring(ma->ma_node, "compatible"); 148 if (strcmp(str, "pciex108e,80f0") == 0 || 149 strcmp(str, "pciex108e,80f8") == 0) 150 return (1); 151 152 return (0); 153 } 154 155 void 156 pyro_attach(struct device *parent, struct device *self, void *aux) 157 { 158 struct pyro_softc *sc = (struct pyro_softc *)self; 159 struct mainbus_attach_args *ma = aux; 160 char *str; 161 int busa; 162 163 sc->sc_node = ma->ma_node; 164 sc->sc_dmat = ma->ma_dmatag; 165 sc->sc_bust = ma->ma_bustag; 166 sc->sc_csr = ma->ma_reg[0].ur_paddr; 167 sc->sc_xbc = ma->ma_reg[1].ur_paddr; 168 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT); 169 170 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000) 171 busa = 1; 172 else 173 busa = 0; 174 175 if (bus_space_map(sc->sc_bust, sc->sc_csr, 176 ma->ma_reg[0].ur_len, 0, &sc->sc_csrh)) { 177 printf(": failed to map csr registers\n"); 178 return; 179 } 180 181 if (bus_space_map(sc->sc_bust, sc->sc_xbc, 182 ma->ma_reg[1].ur_len, 0, &sc->sc_xbch)) { 183 printf(": failed to map xbc registers\n"); 184 return; 185 } 186 187 str = getpropstring(ma->ma_node, "compatible"); 188 if (strcmp(str, "pciex108e,80f8") == 0) 189 sc->sc_oberon = 1; 190 191 pyro_init(sc, busa); 192 } 193 194 void 195 pyro_init(struct pyro_softc *sc, int busa) 196 { 197 struct pyro_pbm *pbm; 198 struct pcibus_attach_args pba; 199 int *busranges = NULL, nranges; 200 201 pbm = malloc(sizeof(*pbm), M_DEVBUF, M_NOWAIT | M_ZERO); 202 if (pbm == NULL) 203 panic("pyro: can't alloc pyro pbm"); 204 205 pbm->pp_sc = sc; 206 pbm->pp_bus_a = busa; 207 208 if (getprop(sc->sc_node, "ranges", sizeof(struct pyro_range), 209 &pbm->pp_nrange, (void **)&pbm->pp_range)) 210 panic("pyro: can't get ranges"); 211 212 if (getprop(sc->sc_node, "bus-range", sizeof(int), &nranges, 213 (void **)&busranges)) 214 panic("pyro: can't get bus-range"); 215 216 printf(": \"%s\", rev %d, ign %x, bus %c %d to %d\n", 217 sc->sc_oberon ? "Oberon" : "Fire", 218 getpropint(sc->sc_node, "module-revision#", 0), sc->sc_ign, 219 busa ? 'A' : 'B', busranges[0], busranges[1]); 220 221 printf("%s: ", sc->sc_dv.dv_xname); 222 pyro_init_iommu(sc, pbm); 223 224 pbm->pp_memt = pyro_alloc_mem_tag(pbm); 225 pbm->pp_iot = pyro_alloc_io_tag(pbm); 226 pbm->pp_cfgt = pyro_alloc_config_tag(pbm); 227 pbm->pp_dmat = pyro_alloc_dma_tag(pbm); 228 229 pyro_init_msi(sc, pbm); 230 231 if (bus_space_map(pbm->pp_cfgt, 0, 0x10000000, 0, &pbm->pp_cfgh)) 232 panic("pyro: can't map config space"); 233 234 pbm->pp_pc = pyro_alloc_chipset(pbm, sc->sc_node, &_sparc_pci_chipset); 235 236 pbm->pp_pc->bustag = pbm->pp_cfgt; 237 pbm->pp_pc->bushandle = pbm->pp_cfgh; 238 239 bzero(&pba, sizeof(pba)); 240 pba.pba_busname = "pci"; 241 pba.pba_domain = pci_ndomains++; 242 pba.pba_bus = busranges[0]; 243 pba.pba_pc = pbm->pp_pc; 244 pba.pba_flags = pbm->pp_flags; 245 pba.pba_dmat = pbm->pp_dmat; 246 pba.pba_memt = pbm->pp_memt; 247 pba.pba_iot = pbm->pp_iot; 248 pba.pba_pc->conf_size = pyro_conf_size; 249 pba.pba_pc->conf_read = pyro_conf_read; 250 pba.pba_pc->conf_write = pyro_conf_write; 251 pba.pba_pc->intr_map = pyro_intr_map; 252 253 free(busranges, M_DEVBUF, 0); 254 255 #ifdef DDB 256 db_register_xir(pyro_xir, sc); 257 #endif 258 259 config_found(&sc->sc_dv, &pba, pyro_print); 260 } 261 262 void 263 pyro_init_iommu(struct pyro_softc *sc, struct pyro_pbm *pbm) 264 { 265 struct iommu_state *is = &pbm->pp_is; 266 int tsbsize = 7; 267 u_int32_t iobase = -1; 268 char *name; 269 270 is->is_bustag = sc->sc_bust; 271 272 if (bus_space_subregion(is->is_bustag, sc->sc_csrh, 273 0x40000, 0x100, &is->is_iommu)) { 274 panic("pyro: unable to create iommu handle"); 275 } 276 277 is->is_sb[0] = &pbm->pp_sb; 278 is->is_sb[0]->sb_bustag = is->is_bustag; 279 280 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 281 if (name == NULL) 282 panic("couldn't malloc iommu name"); 283 snprintf(name, 32, "%s dvma", sc->sc_dv.dv_xname); 284 285 /* On Oberon, we need to flush the cache. */ 286 if (sc->sc_oberon) 287 is->is_flags |= IOMMU_FLUSH_CACHE; 288 289 iommu_init(name, is, tsbsize, iobase); 290 } 291 292 void 293 pyro_init_msi(struct pyro_softc *sc, struct pyro_pbm *pbm) 294 { 295 u_int32_t msi_addr_range[3]; 296 u_int32_t msi_eq_devino[3] = { 0, 36, 24 }; 297 int ihandle; 298 int msis, msi_eq_size; 299 300 if (OF_getprop(sc->sc_node, "msi-address-ranges", 301 msi_addr_range, sizeof(msi_addr_range)) <= 0) 302 return; 303 pbm->pp_msiaddr = msi_addr_range[1]; 304 pbm->pp_msiaddr |= ((bus_addr_t)msi_addr_range[0]) << 32; 305 306 msis = getpropint(sc->sc_node, "#msi", 256); 307 pbm->pp_msi = mallocarray(msis, sizeof(*pbm->pp_msi), M_DEVBUF, 308 M_NOWAIT | M_ZERO); 309 if (pbm->pp_msi == NULL) 310 return; 311 312 msi_eq_size = getpropint(sc->sc_node, "msi-eq-size", 256); 313 pbm->pp_meq = msi_eq_alloc(pbm->pp_dmat, msi_eq_size); 314 if (pbm->pp_meq == NULL) 315 goto free_table; 316 317 bzero(pbm->pp_meq->meq_va, 318 pbm->pp_meq->meq_nentries * sizeof(struct pyro_msi_msg)); 319 320 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_BASE_ADDR, 321 pbm->pp_meq->meq_map->dm_segs[0].ds_addr); 322 323 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 324 FIRE_INTRMONDO_DATA0, sc->sc_ign); 325 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 326 FIRE_INTRMONDO_DATA1, 0); 327 328 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_MSI32_ADDR, 329 pbm->pp_msiaddr); 330 331 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_HEAD, 0); 332 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_TAIL, 0); 333 334 OF_getprop(sc->sc_node, "msi-eq-to-devino", 335 msi_eq_devino, sizeof(msi_eq_devino)); 336 337 ihandle = msi_eq_devino[2] | sc->sc_ign; 338 if (pyro_intr_establish(pbm->pp_memt, sc->sc_bust, ihandle, 339 IPL_HIGH, 0, pyro_msi_eq_intr, pbm, sc->sc_dv.dv_xname) == NULL) 340 goto free_table; 341 342 /* Enable EQ. */ 343 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_CNTRL_SET, 344 FIRE_EQ_CTRL_SET_EN); 345 346 pbm->pp_flags |= PCI_FLAGS_MSI_ENABLED; 347 return; 348 349 free_table: 350 free(pbm->pp_msi, M_DEVBUF, 0); 351 } 352 353 int 354 pyro_print(void *aux, const char *p) 355 { 356 if (p == NULL) 357 return (UNCONF); 358 return (QUIET); 359 } 360 361 int 362 pyro_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 363 { 364 return PCIE_CONFIG_SPACE_SIZE; 365 } 366 367 pcireg_t 368 pyro_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 369 { 370 struct cpu_info *ci = curcpu(); 371 pcireg_t val; 372 int s; 373 374 s = splhigh(); 375 membar(Sync); 376 ci->ci_pci_probe = 1; 377 val = bus_space_read_4(pc->bustag, pc->bushandle, 378 (PCITAG_OFFSET(tag) << 4) + reg); 379 membar(Sync); 380 if (ci->ci_pci_fault) 381 val = 0xffffffff; 382 ci->ci_pci_probe = ci->ci_pci_fault = 0; 383 splx(s); 384 385 return (val); 386 } 387 388 void 389 pyro_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 390 { 391 bus_space_write_4(pc->bustag, pc->bushandle, 392 (PCITAG_OFFSET(tag) << 4) + reg, data); 393 } 394 395 /* 396 * Bus-specific interrupt mapping 397 */ 398 int 399 pyro_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 400 { 401 struct pyro_pbm *pp = pa->pa_pc->cookie; 402 struct pyro_softc *sc = pp->pp_sc; 403 u_int dev; 404 405 if (*ihp != (pci_intr_handle_t)-1) { 406 *ihp |= sc->sc_ign; 407 return (0); 408 } 409 410 /* 411 * We didn't find a PROM mapping for this interrupt. Try to 412 * construct one ourselves based on the swizzled interrupt pin 413 * and the interrupt mapping for PCI slots documented in the 414 * UltraSPARC-IIi User's Manual. 415 */ 416 417 if (pa->pa_intrpin == 0) 418 return (-1); 419 420 /* 421 * This deserves some documentation. Should anyone 422 * have anything official looking, please speak up. 423 */ 424 dev = pa->pa_device - 1; 425 426 *ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT; 427 *ihp |= (dev << 2) & INTMAP_PCISLOT; 428 *ihp |= sc->sc_ign; 429 430 return (0); 431 } 432 433 bus_space_tag_t 434 pyro_alloc_mem_tag(struct pyro_pbm *pp) 435 { 436 return (pyro_alloc_bus_tag(pp, "mem", 437 0x02, /* 32-bit mem space (where's the #define???) */ 438 ASI_PRIMARY, ASI_PRIMARY_LITTLE)); 439 } 440 441 bus_space_tag_t 442 pyro_alloc_io_tag(struct pyro_pbm *pp) 443 { 444 return (pyro_alloc_bus_tag(pp, "io", 445 0x01, /* IO space (where's the #define???) */ 446 ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED)); 447 } 448 449 bus_space_tag_t 450 pyro_alloc_config_tag(struct pyro_pbm *pp) 451 { 452 return (pyro_alloc_bus_tag(pp, "cfg", 453 0x00, /* Config space (where's the #define???) */ 454 ASI_PHYS_NON_CACHED_LITTLE, ASI_PHYS_NON_CACHED)); 455 } 456 457 bus_space_tag_t 458 pyro_alloc_bus_tag(struct pyro_pbm *pbm, const char *name, int ss, 459 int asi, int sasi) 460 { 461 struct pyro_softc *sc = pbm->pp_sc; 462 struct sparc_bus_space_tag *bt; 463 464 bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO); 465 if (bt == NULL) 466 panic("pyro: could not allocate bus tag"); 467 468 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)", 469 sc->sc_dv.dv_xname, name, ss, asi); 470 471 bt->cookie = pbm; 472 bt->parent = sc->sc_bust; 473 bt->default_type = ss; 474 bt->asi = asi; 475 bt->sasi = sasi; 476 bt->sparc_bus_map = pyro_bus_map; 477 bt->sparc_bus_mmap = pyro_bus_mmap; 478 bt->sparc_intr_establish = pyro_intr_establish; 479 return (bt); 480 } 481 482 bus_dma_tag_t 483 pyro_alloc_dma_tag(struct pyro_pbm *pbm) 484 { 485 struct pyro_softc *sc = pbm->pp_sc; 486 bus_dma_tag_t dt, pdt = sc->sc_dmat; 487 488 dt = malloc(sizeof(*dt), M_DEVBUF, M_NOWAIT | M_ZERO); 489 if (dt == NULL) 490 panic("pyro: could not alloc dma tag"); 491 492 dt->_cookie = pbm; 493 dt->_parent = pdt; 494 dt->_dmamap_create = pyro_dmamap_create; 495 dt->_dmamap_destroy = iommu_dvmamap_destroy; 496 dt->_dmamap_load = iommu_dvmamap_load; 497 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 498 dt->_dmamap_unload = iommu_dvmamap_unload; 499 dt->_dmamap_sync = iommu_dvmamap_sync; 500 dt->_dmamem_alloc = iommu_dvmamem_alloc; 501 dt->_dmamem_free = iommu_dvmamem_free; 502 return (dt); 503 } 504 505 pci_chipset_tag_t 506 pyro_alloc_chipset(struct pyro_pbm *pbm, int node, pci_chipset_tag_t pc) 507 { 508 pci_chipset_tag_t npc; 509 510 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 511 if (npc == NULL) 512 panic("pyro: could not allocate pci_chipset_tag_t"); 513 memcpy(npc, pc, sizeof *pc); 514 npc->cookie = pbm; 515 npc->rootnode = node; 516 return (npc); 517 } 518 519 int 520 pyro_dmamap_create(bus_dma_tag_t t, bus_dma_tag_t t0, bus_size_t size, 521 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, 522 bus_dmamap_t *dmamp) 523 { 524 struct pyro_pbm *pp = t->_cookie; 525 526 return (iommu_dvmamap_create(t, t0, &pp->pp_sb, size, nsegments, 527 maxsegsz, boundary, flags, dmamp)); 528 } 529 530 int 531 pyro_bus_map(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t offset, 532 bus_size_t size, int flags, bus_space_handle_t *hp) 533 { 534 struct pyro_pbm *pbm = t->cookie; 535 int i, ss; 536 537 DPRINTF(PDB_BUSMAP, ("pyro_bus_map: type %d off %qx sz %qx flags %d", 538 t->default_type, 539 (unsigned long long)offset, 540 (unsigned long long)size, 541 flags)); 542 543 ss = t->default_type; 544 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 545 546 if (t->parent == 0 || t->parent->sparc_bus_map == 0) { 547 printf("\npyro_bus_map: invalid parent"); 548 return (EINVAL); 549 } 550 551 if (flags & BUS_SPACE_MAP_PROMADDRESS) { 552 return ((*t->parent->sparc_bus_map) 553 (t, t0, offset, size, flags, hp)); 554 } 555 556 for (i = 0; i < pbm->pp_nrange; i++) { 557 bus_addr_t paddr; 558 559 if (((pbm->pp_range[i].cspace >> 24) & 0x03) != ss) 560 continue; 561 562 paddr = pbm->pp_range[i].phys_lo + offset; 563 paddr |= ((bus_addr_t)pbm->pp_range[i].phys_hi) << 32; 564 return ((*t->parent->sparc_bus_map) 565 (t, t0, paddr, size, flags, hp)); 566 } 567 568 return (EINVAL); 569 } 570 571 paddr_t 572 pyro_bus_mmap(bus_space_tag_t t, bus_space_tag_t t0, bus_addr_t paddr, 573 off_t off, int prot, int flags) 574 { 575 bus_addr_t offset = paddr; 576 struct pyro_pbm *pbm = t->cookie; 577 int i, ss; 578 579 ss = t->default_type; 580 581 DPRINTF(PDB_BUSMAP, ("pyro_bus_mmap: prot %d flags %d pa %qx\n", 582 prot, flags, (unsigned long long)paddr)); 583 584 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) { 585 printf("\npyro_bus_mmap: invalid parent"); 586 return (-1); 587 } 588 589 for (i = 0; i < pbm->pp_nrange; i++) { 590 bus_addr_t paddr; 591 592 if (((pbm->pp_range[i].cspace >> 24) & 0x03) != ss) 593 continue; 594 595 paddr = pbm->pp_range[i].phys_lo + offset; 596 paddr |= ((bus_addr_t)pbm->pp_range[i].phys_hi) << 32; 597 return ((*t->parent->sparc_bus_mmap) 598 (t, t0, paddr, off, prot, flags)); 599 } 600 601 return (-1); 602 } 603 604 void * 605 pyro_intr_establish(bus_space_tag_t t, bus_space_tag_t t0, int ihandle, 606 int level, int flags, int (*handler)(void *), void *arg, const char *what) 607 { 608 struct pyro_pbm *pbm = t->cookie; 609 struct pyro_softc *sc = pbm->pp_sc; 610 struct intrhand *ih = NULL; 611 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 612 int ino; 613 614 if (ihandle & PCI_INTR_MSI) { 615 pci_chipset_tag_t pc = pbm->pp_pc; 616 pcitag_t tag = ihandle & ~PCI_INTR_MSI; 617 int msinum = pbm->pp_msinum++; 618 u_int64_t reg; 619 620 ih = bus_intr_allocate(t0, handler, arg, ihandle, level, 621 NULL, NULL, what); 622 if (ih == NULL) 623 return (NULL); 624 625 if (ih->ih_name) 626 evcount_attach(&ih->ih_count, ih->ih_name, NULL); 627 else 628 evcount_attach(&ih->ih_count, "unknown", NULL); 629 630 ih->ih_ack = pyro_msi_ack; 631 632 pbm->pp_msi[msinum] = ih; 633 ih->ih_number = msinum; 634 635 if (flags & BUS_INTR_ESTABLISH_MPSAFE) 636 ih->ih_mpsafe = 1; 637 638 pci_msi_enable(pc, tag, pbm->pp_msiaddr, msinum); 639 640 /* Map MSI to the right EQ and mark it as valid. */ 641 reg = bus_space_read_8(sc->sc_bust, sc->sc_csrh, 642 FIRE_MSI_MAP + msinum * 8); 643 reg &= ~FIRE_MSI_MAP_EQNUM; 644 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 645 FIRE_MSI_MAP + msinum * 8, reg); 646 647 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 648 FIRE_MSI_CLEAR + msinum * 8, FIRE_MSI_CLEAR_EQWR_N); 649 650 reg = bus_space_read_8(sc->sc_bust, sc->sc_csrh, 651 FIRE_MSI_MAP + msinum * 8); 652 reg |= FIRE_MSI_MAP_V; 653 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 654 FIRE_MSI_MAP + msinum * 8, reg); 655 656 return (ih); 657 } 658 659 ino = INTINO(ihandle); 660 661 if (level == IPL_NONE) 662 level = INTLEV(ihandle); 663 if (level == IPL_NONE) { 664 printf(": no IPL, setting IPL 2.\n"); 665 level = 2; 666 } 667 668 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) == 0) { 669 u_int64_t *imap, *iclr; 670 671 imap = bus_space_vaddr(sc->sc_bust, sc->sc_csrh) + 0x1000; 672 iclr = bus_space_vaddr(sc->sc_bust, sc->sc_csrh) + 0x1400; 673 intrmapptr = &imap[ino]; 674 intrclrptr = &iclr[ino]; 675 ino |= INTVEC(ihandle); 676 } 677 678 ih = bus_intr_allocate(t0, handler, arg, ino, level, intrmapptr, 679 intrclrptr, what); 680 if (ih == NULL) 681 return (NULL); 682 683 if (flags & BUS_INTR_ESTABLISH_MPSAFE) 684 ih->ih_mpsafe = 1; 685 686 intr_establish(ih->ih_pil, ih); 687 688 if (intrmapptr != NULL) { 689 u_int64_t intrmap; 690 691 intrmap = *intrmapptr; 692 intrmap &= ~FIRE_INTRMAP_INT_CNTRL_NUM_MASK; 693 intrmap |= FIRE_INTRMAP_INT_CNTRL_NUM0; 694 if (sc->sc_oberon) { 695 intrmap &= ~OBERON_INTRMAP_T_DESTID_MASK; 696 intrmap |= CPU_JUPITERID << 697 OBERON_INTRMAP_T_DESTID_SHIFT; 698 } else { 699 intrmap &= ~FIRE_INTRMAP_T_JPID_MASK; 700 intrmap |= CPU_UPAID << FIRE_INTRMAP_T_JPID_SHIFT; 701 } 702 intrmap |= INTMAP_V; 703 *intrmapptr = intrmap; 704 intrmap = *intrmapptr; 705 ih->ih_number |= intrmap & INTMAP_INR; 706 } 707 708 return (ih); 709 } 710 711 void 712 pyro_msi_ack(struct intrhand *ih) 713 { 714 } 715 716 int 717 pyro_msi_eq_intr(void *arg) 718 { 719 struct pyro_pbm *pbm = arg; 720 struct pyro_softc *sc = pbm->pp_sc; 721 struct msi_eq *meq = pbm->pp_meq; 722 struct pyro_msi_msg *msg; 723 uint64_t head, tail; 724 struct intrhand *ih; 725 int msinum; 726 727 head = bus_space_read_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_HEAD); 728 tail = bus_space_read_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_TAIL); 729 730 if (head == tail) 731 return (0); 732 733 while (head != tail) { 734 msg = (struct pyro_msi_msg *)meq->meq_va; 735 736 if (msg[head].mm_type == 0) 737 break; 738 msg[head].mm_type = 0; 739 740 msinum = msg[head].mm_data; 741 ih = pbm->pp_msi[msinum]; 742 bus_space_write_8(sc->sc_bust, sc->sc_csrh, 743 FIRE_MSI_CLEAR + msinum * 8, FIRE_MSI_CLEAR_EQWR_N); 744 745 send_softint(-1, ih->ih_pil, ih); 746 747 head += 1; 748 head &= (meq->meq_nentries - 1); 749 } 750 751 bus_space_write_8(sc->sc_bust, sc->sc_csrh, FIRE_EQ_HEAD, head); 752 753 return (1); 754 } 755 756 #ifdef DDB 757 void 758 pyro_xir(void *arg, int cpu) 759 { 760 struct pyro_softc *sc = arg; 761 762 bus_space_write_8(sc->sc_bust, sc->sc_xbch, FIRE_RESET_GEN, 763 FIRE_RESET_GEN_XIR); 764 } 765 #endif 766 767 const struct cfattach pyro_ca = { 768 sizeof(struct pyro_softc), pyro_match, pyro_attach 769 }; 770 771 struct cfdriver pyro_cd = { 772 NULL, "pyro", DV_DULL 773 }; 774