1 /* $OpenBSD: creator.c,v 1.48 2014/07/12 18:44:43 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/types.h> 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/device.h> 34 #include <sys/conf.h> 35 #include <sys/malloc.h> 36 37 #include <machine/bus.h> 38 #include <machine/autoconf.h> 39 #include <machine/openfirm.h> 40 41 #include <dev/wscons/wsconsio.h> 42 #include <dev/wscons/wsdisplayvar.h> 43 #include <dev/rasops/rasops.h> 44 #include <machine/fbvar.h> 45 46 #include <sparc64/dev/creatorreg.h> 47 #include <sparc64/dev/creatorvar.h> 48 49 int creator_match(struct device *, void *, void *); 50 void creator_attach(struct device *, struct device *, void *); 51 int creator_ioctl(void *, u_long, caddr_t, int, struct proc *); 52 paddr_t creator_mmap(void *, off_t, int); 53 54 void creator_ras_fifo_wait(struct creator_softc *, int); 55 void creator_ras_wait(struct creator_softc *); 56 void creator_ras_init(struct creator_softc *); 57 int creator_ras_copyrows(void *, int, int, int); 58 int creator_ras_erasecols(void *, int, int, int, long int); 59 int creator_ras_eraserows(void *, int, int, long int); 60 void creator_ras_fill(struct creator_softc *); 61 void creator_ras_setfg(struct creator_softc *, int32_t); 62 63 int creator_setcursor(struct creator_softc *, struct wsdisplay_cursor *); 64 int creator_updatecursor(struct creator_softc *, u_int); 65 void creator_curs_enable(struct creator_softc *, u_int); 66 67 #ifndef SMALL_KERNEL 68 void creator_load_firmware(void *); 69 #endif /* SMALL_KERNEL */ 70 void creator_load_sram(struct creator_softc *, u_int32_t *, u_int32_t); 71 72 struct wsdisplay_accessops creator_accessops = { 73 .ioctl = creator_ioctl, 74 .mmap = creator_mmap 75 }; 76 77 struct cfdriver creator_cd = { 78 NULL, "creator", DV_DULL 79 }; 80 81 struct cfattach creator_ca = { 82 sizeof(struct creator_softc), creator_match, creator_attach 83 }; 84 85 int 86 creator_match(parent, match, aux) 87 struct device *parent; 88 void *match, *aux; 89 { 90 struct mainbus_attach_args *ma = aux; 91 92 if (strcmp(ma->ma_name, "SUNW,ffb") == 0 || 93 strcmp(ma->ma_name, "SUNW,afb") == 0) 94 return (1); 95 return (0); 96 } 97 98 void 99 creator_attach(parent, self, aux) 100 struct device *parent, *self; 101 void *aux; 102 { 103 struct creator_softc *sc = (struct creator_softc *)self; 104 struct mainbus_attach_args *ma = aux; 105 extern int fbnode; 106 int i, nregs; 107 char *model; 108 int btype; 109 110 sc->sc_bt = ma->ma_bustag; 111 112 nregs = min(ma->ma_nreg, FFB_NREGS); 113 114 if (nregs <= FFB_REG_DFB24) { 115 printf(": no dfb24 regs found\n"); 116 return; 117 } 118 119 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_DFB24].ur_paddr, 120 ma->ma_reg[FFB_REG_DFB24].ur_len, BUS_SPACE_MAP_LINEAR, 121 &sc->sc_pixel_h)) { 122 printf(": failed to map dfb24\n"); 123 return; 124 } 125 126 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_FBC].ur_paddr, 127 ma->ma_reg[FFB_REG_FBC].ur_len, 0, &sc->sc_fbc_h)) { 128 printf(": failed to map fbc\n"); 129 goto unmap_dfb24; 130 } 131 132 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_DAC].ur_paddr, 133 ma->ma_reg[FFB_REG_DAC].ur_len, 0, &sc->sc_dac_h)) { 134 printf(": failed to map dac\n"); 135 goto unmap_fbc; 136 } 137 138 for (i = 0; i < nregs; i++) { 139 sc->sc_addrs[i] = ma->ma_reg[i].ur_paddr; 140 sc->sc_sizes[i] = ma->ma_reg[i].ur_len; 141 } 142 sc->sc_nreg = nregs; 143 144 sc->sc_console = (fbnode == ma->ma_node); 145 sc->sc_node = ma->ma_node; 146 147 if (strcmp(ma->ma_name, "SUNW,afb") == 0) 148 sc->sc_type = FFB_AFB; 149 150 /* 151 * Prom reports only the length of the fcode header, we need 152 * the whole thing. 153 */ 154 sc->sc_sizes[0] = 0x00400000; 155 156 if (sc->sc_type == FFB_CREATOR) { 157 btype = getpropint(sc->sc_node, "board_type", 0); 158 if ((btype & 7) == 3) 159 printf(": Creator3D"); 160 else 161 printf(": Creator"); 162 } else 163 printf(": Elite3D"); 164 165 model = getpropstring(sc->sc_node, "model"); 166 if (model == NULL || strlen(model) == 0) 167 model = "unknown"; 168 169 DAC_WRITE(sc, FFB_DAC_TYPE, DAC_TYPE_GETREV); 170 sc->sc_dacrev = DAC_READ(sc, FFB_DAC_VALUE) >> 28; 171 172 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 173 174 if (sc->sc_type == FFB_AFB) 175 sc->sc_dacrev = 10; 176 177 fb_setsize(&sc->sc_sunfb, 32, 1152, 900, sc->sc_node, 0); 178 /* linesize has a fixed value, compensate */ 179 sc->sc_sunfb.sf_linebytes = 8192; 180 sc->sc_sunfb.sf_fbsize = sc->sc_sunfb.sf_height * 8192; 181 182 sc->sc_sunfb.sf_ro.ri_bits = (void *)bus_space_vaddr(sc->sc_bt, 183 sc->sc_pixel_h); 184 sc->sc_sunfb.sf_ro.ri_hw = sc; 185 fbwscons_init(&sc->sc_sunfb, 0, sc->sc_console); 186 187 if ((sc->sc_sunfb.sf_dev.dv_cfdata->cf_flags & CREATOR_CFFLAG_NOACCEL) 188 == 0) { 189 sc->sc_sunfb.sf_ro.ri_ops.eraserows = creator_ras_eraserows; 190 sc->sc_sunfb.sf_ro.ri_ops.erasecols = creator_ras_erasecols; 191 sc->sc_sunfb.sf_ro.ri_ops.copyrows = creator_ras_copyrows; 192 creator_ras_init(sc); 193 194 #ifndef SMALL_KERNEL 195 /* 196 * Elite3D cards need a firmware for accelerated X to 197 * work. Console framebuffer acceleration will work 198 * without it though, so doing this late should be 199 * fine. 200 */ 201 if (sc->sc_type == FFB_AFB) 202 mountroothook_establish(creator_load_firmware, sc); 203 #endif /* SMALL_KERNEL */ 204 } 205 206 if (sc->sc_console) 207 fbwscons_console_init(&sc->sc_sunfb, -1); 208 209 fbwscons_attach(&sc->sc_sunfb, &creator_accessops, sc->sc_console); 210 return; 211 212 unmap_fbc: 213 bus_space_unmap(sc->sc_bt, sc->sc_fbc_h, 214 ma->ma_reg[FFB_REG_FBC].ur_len); 215 unmap_dfb24: 216 bus_space_unmap(sc->sc_bt, sc->sc_pixel_h, 217 ma->ma_reg[FFB_REG_DFB24].ur_len); 218 } 219 220 int 221 creator_ioctl(v, cmd, data, flags, p) 222 void *v; 223 u_long cmd; 224 caddr_t data; 225 int flags; 226 struct proc *p; 227 { 228 struct creator_softc *sc = v; 229 struct wsdisplay_cursor *curs; 230 struct wsdisplay_fbinfo *wdf; 231 struct wsdisplay_curpos *pos; 232 u_char r[2], g[2], b[2]; 233 int error; 234 235 switch (cmd) { 236 case WSDISPLAYIO_GTYPE: 237 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 238 break; 239 case WSDISPLAYIO_SMODE: 240 sc->sc_mode = *(u_int *)data; 241 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 242 struct rasops_info *ri = &sc->sc_sunfb.sf_ro; 243 long attr; 244 245 if ((sc->sc_sunfb.sf_dev.dv_cfdata->cf_flags & 246 CREATOR_CFFLAG_NOACCEL) == 0) 247 creator_ras_init(sc); 248 249 /* Clear screen. */ 250 ri->ri_ops.alloc_attr(ri, 251 WSCOL_BLACK, WSCOL_WHITE, WSATTR_WSCOLORS, &attr); 252 ri->ri_ops.eraserows(ri, 0, ri->ri_rows, attr); 253 } 254 break; 255 case WSDISPLAYIO_GINFO: 256 wdf = (void *)data; 257 wdf->height = sc->sc_sunfb.sf_height; 258 wdf->width = sc->sc_sunfb.sf_width; 259 wdf->depth = 32; 260 wdf->cmsize = 0; 261 break; 262 case WSDISPLAYIO_GETSUPPORTEDDEPTH: 263 *(u_int *)data = WSDISPLAYIO_DEPTH_24_32; 264 break; 265 case WSDISPLAYIO_LINEBYTES: 266 *(u_int *)data = sc->sc_sunfb.sf_linebytes; 267 break; 268 case WSDISPLAYIO_GCURSOR: 269 curs = (struct wsdisplay_cursor *)data; 270 if (curs->which & WSDISPLAY_CURSOR_DOCUR) 271 curs->enable = sc->sc_curs_enabled; 272 if (curs->which & WSDISPLAY_CURSOR_DOPOS) { 273 curs->pos.x = sc->sc_curs_pos.x; 274 curs->pos.y = sc->sc_curs_pos.y; 275 } 276 if (curs->which & WSDISPLAY_CURSOR_DOHOT) { 277 curs->hot.x = sc->sc_curs_hot.x; 278 curs->hot.y = sc->sc_curs_hot.y; 279 } 280 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 281 curs->cmap.index = 0; 282 curs->cmap.count = 2; 283 r[0] = sc->sc_curs_fg >> 0; 284 g[0] = sc->sc_curs_fg >> 8; 285 b[0] = sc->sc_curs_fg >> 16; 286 r[1] = sc->sc_curs_bg >> 0; 287 g[1] = sc->sc_curs_bg >> 8; 288 b[1] = sc->sc_curs_bg >> 16; 289 error = copyout(r, curs->cmap.red, sizeof(r)); 290 if (error) 291 return (error); 292 error = copyout(g, curs->cmap.green, sizeof(g)); 293 if (error) 294 return (error); 295 error = copyout(b, curs->cmap.blue, sizeof(b)); 296 if (error) 297 return (error); 298 } 299 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 300 size_t l; 301 302 curs->size.x = sc->sc_curs_size.x; 303 curs->size.y = sc->sc_curs_size.y; 304 l = (sc->sc_curs_size.x * sc->sc_curs_size.y) / NBBY; 305 error = copyout(sc->sc_curs_image, curs->image, l); 306 if (error) 307 return (error); 308 error = copyout(sc->sc_curs_mask, curs->mask, l); 309 if (error) 310 return (error); 311 } 312 break; 313 case WSDISPLAYIO_SCURPOS: 314 pos = (struct wsdisplay_curpos *)data; 315 sc->sc_curs_pos.x = pos->x; 316 sc->sc_curs_pos.y = pos->y; 317 creator_updatecursor(sc, WSDISPLAY_CURSOR_DOPOS); 318 break; 319 case WSDISPLAYIO_GCURPOS: 320 pos = (struct wsdisplay_curpos *)data; 321 pos->x = sc->sc_curs_pos.x; 322 pos->y = sc->sc_curs_pos.y; 323 break; 324 case WSDISPLAYIO_SCURSOR: 325 curs = (struct wsdisplay_cursor *)data; 326 return (creator_setcursor(sc, curs)); 327 case WSDISPLAYIO_GCURMAX: 328 pos = (struct wsdisplay_curpos *)data; 329 pos->x = CREATOR_CURS_MAX; 330 pos->y = CREATOR_CURS_MAX; 331 break; 332 case WSDISPLAYIO_SVIDEO: 333 case WSDISPLAYIO_GVIDEO: 334 break; 335 336 case WSDISPLAYIO_GETCMAP: 337 case WSDISPLAYIO_PUTCMAP: 338 default: 339 return -1; /* not supported yet */ 340 } 341 342 return (0); 343 } 344 345 int 346 creator_setcursor(struct creator_softc *sc, struct wsdisplay_cursor *curs) 347 { 348 u_int8_t r[2], g[2], b[2], image[128], mask[128]; 349 int error; 350 size_t imcount; 351 352 /* 353 * Do stuff that can generate errors first, then we'll blast it 354 * all at once. 355 */ 356 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 357 if (curs->cmap.count < 2) 358 return (EINVAL); 359 error = copyin(curs->cmap.red, r, sizeof(r)); 360 if (error) 361 return (error); 362 error = copyin(curs->cmap.green, g, sizeof(g)); 363 if (error) 364 return (error); 365 error = copyin(curs->cmap.blue, b, sizeof(b)); 366 if (error) 367 return (error); 368 } 369 370 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 371 if (curs->size.x > CREATOR_CURS_MAX || 372 curs->size.y > CREATOR_CURS_MAX) 373 return (EINVAL); 374 imcount = (curs->size.x * curs->size.y) / NBBY; 375 error = copyin(curs->image, image, imcount); 376 if (error) 377 return (error); 378 error = copyin(curs->mask, mask, imcount); 379 if (error) 380 return (error); 381 } 382 383 /* 384 * Ok, everything is in kernel space and sane, update state. 385 */ 386 387 if (curs->which & WSDISPLAY_CURSOR_DOCUR) 388 sc->sc_curs_enabled = curs->enable; 389 if (curs->which & WSDISPLAY_CURSOR_DOPOS) { 390 sc->sc_curs_pos.x = curs->pos.x; 391 sc->sc_curs_pos.y = curs->pos.y; 392 } 393 if (curs->which & WSDISPLAY_CURSOR_DOHOT) { 394 sc->sc_curs_hot.x = curs->hot.x; 395 sc->sc_curs_hot.y = curs->hot.y; 396 } 397 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 398 sc->sc_curs_fg = ((r[0] << 0) | (g[0] << 8) | (b[0] << 16)); 399 sc->sc_curs_bg = ((r[1] << 0) | (g[1] << 8) | (b[1] << 16)); 400 } 401 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 402 sc->sc_curs_size.x = curs->size.x; 403 sc->sc_curs_size.y = curs->size.y; 404 bcopy(image, sc->sc_curs_image, imcount); 405 bcopy(mask, sc->sc_curs_mask, imcount); 406 } 407 408 creator_updatecursor(sc, curs->which); 409 410 return (0); 411 } 412 413 void 414 creator_curs_enable(struct creator_softc *sc, u_int ena) 415 { 416 u_int32_t v; 417 418 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSENAB); 419 if (sc->sc_dacrev <= 2) 420 v = ena ? 3 : 0; 421 else 422 v = ena ? 0 : 3; 423 DAC_WRITE(sc, FFB_DAC_VALUE2, v); 424 } 425 426 int 427 creator_updatecursor(struct creator_softc *sc, u_int which) 428 { 429 creator_curs_enable(sc, 0); 430 431 if (which & WSDISPLAY_CURSOR_DOCMAP) { 432 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSCMAP); 433 DAC_WRITE(sc, FFB_DAC_VALUE2, sc->sc_curs_fg); 434 DAC_WRITE(sc, FFB_DAC_VALUE2, sc->sc_curs_bg); 435 } 436 437 if (which & (WSDISPLAY_CURSOR_DOPOS | WSDISPLAY_CURSOR_DOHOT)) { 438 u_int32_t x, y; 439 440 x = sc->sc_curs_pos.x + CREATOR_CURS_MAX - sc->sc_curs_hot.x; 441 y = sc->sc_curs_pos.y + CREATOR_CURS_MAX - sc->sc_curs_hot.y; 442 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSPOS); 443 DAC_WRITE(sc, FFB_DAC_VALUE2, 444 ((x & 0xffff) << 16) | (y & 0xffff)); 445 } 446 447 if (which & WSDISPLAY_CURSOR_DOCUR) 448 creator_curs_enable(sc, sc->sc_curs_enabled); 449 450 return (0); 451 } 452 453 const struct creator_mappings { 454 bus_addr_t uoff; 455 bus_addr_t poff; 456 bus_size_t ulen; 457 } creator_map[] = { 458 { FFB_VOFF_SFB8R, FFB_POFF_SFB8R, FFB_VLEN_SFB8R }, 459 { FFB_VOFF_SFB8G, FFB_POFF_SFB8G, FFB_VLEN_SFB8G }, 460 { FFB_VOFF_SFB8B, FFB_POFF_SFB8B, FFB_VLEN_SFB8B }, 461 { FFB_VOFF_SFB8X, FFB_POFF_SFB8X, FFB_VLEN_SFB8X }, 462 { FFB_VOFF_SFB32, FFB_POFF_SFB32, FFB_VLEN_SFB32 }, 463 { FFB_VOFF_SFB64, FFB_POFF_SFB64, FFB_VLEN_SFB64 }, 464 { FFB_VOFF_FBC_REGS, FFB_POFF_FBC_REGS, FFB_VLEN_FBC_REGS }, 465 { FFB_VOFF_BM_FBC_REGS, FFB_POFF_BM_FBC_REGS, FFB_VLEN_BM_FBC_REGS }, 466 { FFB_VOFF_DFB8R, FFB_POFF_DFB8R, FFB_VLEN_DFB8R }, 467 { FFB_VOFF_DFB8G, FFB_POFF_DFB8G, FFB_VLEN_DFB8G }, 468 { FFB_VOFF_DFB8B, FFB_POFF_DFB8B, FFB_VLEN_DFB8B }, 469 { FFB_VOFF_DFB8X, FFB_POFF_DFB8X, FFB_VLEN_DFB8X }, 470 { FFB_VOFF_DFB24, FFB_POFF_DFB24, FFB_VLEN_DFB24 }, 471 { FFB_VOFF_DFB32, FFB_POFF_DFB32, FFB_VLEN_DFB32 }, 472 { FFB_VOFF_DFB422A, FFB_POFF_DFB422A, FFB_VLEN_DFB422A }, 473 { FFB_VOFF_DFB422AD, FFB_POFF_DFB422AD, FFB_VLEN_DFB422AD }, 474 { FFB_VOFF_DFB24B, FFB_POFF_DFB24B, FFB_VLEN_DFB24B }, 475 { FFB_VOFF_DFB422B, FFB_POFF_DFB422B, FFB_VLEN_DFB422B }, 476 { FFB_VOFF_DFB422BD, FFB_POFF_DFB422BD, FFB_VLEN_DFB422BD }, 477 { FFB_VOFF_SFB16Z, FFB_POFF_SFB16Z, FFB_VLEN_SFB16Z }, 478 { FFB_VOFF_SFB8Z, FFB_POFF_SFB8Z, FFB_VLEN_SFB8Z }, 479 { FFB_VOFF_SFB422, FFB_POFF_SFB422, FFB_VLEN_SFB422 }, 480 { FFB_VOFF_SFB422D, FFB_POFF_SFB422D, FFB_VLEN_SFB422D }, 481 { FFB_VOFF_FBC_KREGS, FFB_POFF_FBC_KREGS, FFB_VLEN_FBC_KREGS }, 482 { FFB_VOFF_DAC, FFB_POFF_DAC, FFB_VLEN_DAC }, 483 { FFB_VOFF_PROM, FFB_POFF_PROM, FFB_VLEN_PROM }, 484 { FFB_VOFF_EXP, FFB_POFF_EXP, FFB_VLEN_EXP }, 485 }; 486 #define CREATOR_NMAPPINGS nitems(creator_map) 487 488 paddr_t 489 creator_mmap(vsc, off, prot) 490 void *vsc; 491 off_t off; 492 int prot; 493 { 494 paddr_t x; 495 struct creator_softc *sc = vsc; 496 int i; 497 498 switch (sc->sc_mode) { 499 case WSDISPLAYIO_MODE_MAPPED: 500 /* Turn virtual offset into physical offset */ 501 for (i = 0; i < CREATOR_NMAPPINGS; i++) { 502 if (off >= creator_map[i].uoff && 503 off < (creator_map[i].uoff + creator_map[i].ulen)) 504 break; 505 } 506 if (i == CREATOR_NMAPPINGS) 507 break; 508 509 off -= creator_map[i].uoff; 510 off += creator_map[i].poff; 511 off += sc->sc_addrs[0]; 512 513 /* Map based on physical offset */ 514 for (i = 0; i < sc->sc_nreg; i++) { 515 /* Before this set? */ 516 if (off < sc->sc_addrs[i]) 517 continue; 518 /* After this set? */ 519 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 520 continue; 521 522 x = bus_space_mmap(sc->sc_bt, 0, off, prot, 523 BUS_SPACE_MAP_LINEAR); 524 return (x); 525 } 526 break; 527 case WSDISPLAYIO_MODE_DUMBFB: 528 if (sc->sc_nreg <= FFB_REG_DFB24) 529 break; 530 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 531 return (bus_space_mmap(sc->sc_bt, 532 sc->sc_addrs[FFB_REG_DFB24], off, prot, 533 BUS_SPACE_MAP_LINEAR)); 534 break; 535 } 536 537 return (-1); 538 } 539 540 void 541 creator_ras_fifo_wait(sc, n) 542 struct creator_softc *sc; 543 int n; 544 { 545 int32_t cache = sc->sc_fifo_cache; 546 547 if (cache < n) { 548 do { 549 cache = FBC_READ(sc, FFB_FBC_UCSR); 550 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 551 } while (cache < n); 552 } 553 sc->sc_fifo_cache = cache - n; 554 } 555 556 void 557 creator_ras_wait(sc) 558 struct creator_softc *sc; 559 { 560 u_int32_t ucsr, r; 561 562 while (1) { 563 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 564 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 565 break; 566 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 567 if (r != 0) 568 FBC_WRITE(sc, FFB_FBC_UCSR, r); 569 } 570 } 571 572 void 573 creator_ras_init(sc) 574 struct creator_softc *sc; 575 { 576 creator_ras_fifo_wait(sc, 7); 577 FBC_WRITE(sc, FFB_FBC_PPC, 578 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | 579 FBC_PPC_APE_DIS | FBC_PPC_CS_CONST); 580 FBC_WRITE(sc, FFB_FBC_FBC, 581 FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 582 FFB_FBC_XE_OFF | FFB_FBC_RGBE_MASK); 583 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 584 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 585 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 586 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 587 sc->sc_fg_cache = 0; 588 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 589 creator_ras_wait(sc); 590 } 591 592 int 593 creator_ras_eraserows(cookie, row, n, attr) 594 void *cookie; 595 int row, n; 596 long int attr; 597 { 598 struct rasops_info *ri = cookie; 599 struct creator_softc *sc = ri->ri_hw; 600 int bg, fg; 601 602 if (row < 0) { 603 n += row; 604 row = 0; 605 } 606 if (row + n > ri->ri_rows) 607 n = ri->ri_rows - row; 608 if (n <= 0) 609 return 0; 610 611 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 612 creator_ras_fill(sc); 613 creator_ras_setfg(sc, ri->ri_devcmap[bg]); 614 creator_ras_fifo_wait(sc, 4); 615 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 616 FBC_WRITE(sc, FFB_FBC_BY, 0); 617 FBC_WRITE(sc, FFB_FBC_BX, 0); 618 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 619 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 620 } else { 621 row *= ri->ri_font->fontheight; 622 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 623 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 624 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 625 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 626 } 627 creator_ras_wait(sc); 628 629 return 0; 630 } 631 632 int 633 creator_ras_erasecols(cookie, row, col, n, attr) 634 void *cookie; 635 int row, col, n; 636 long int attr; 637 { 638 struct rasops_info *ri = cookie; 639 struct creator_softc *sc = ri->ri_hw; 640 int fg, bg; 641 642 if ((row < 0) || (row >= ri->ri_rows)) 643 return 0; 644 if (col < 0) { 645 n += col; 646 col = 0; 647 } 648 if (col + n > ri->ri_cols) 649 n = ri->ri_cols - col; 650 if (n <= 0) 651 return 0; 652 n *= ri->ri_font->fontwidth; 653 col *= ri->ri_font->fontwidth; 654 row *= ri->ri_font->fontheight; 655 656 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 657 creator_ras_fill(sc); 658 creator_ras_setfg(sc, ri->ri_devcmap[bg]); 659 creator_ras_fifo_wait(sc, 4); 660 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 661 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 662 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 663 FBC_WRITE(sc, FFB_FBC_BW, n - 1); 664 creator_ras_wait(sc); 665 666 return 0; 667 } 668 669 void 670 creator_ras_fill(sc) 671 struct creator_softc *sc; 672 { 673 creator_ras_fifo_wait(sc, 2); 674 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 675 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 676 creator_ras_wait(sc); 677 } 678 679 int 680 creator_ras_copyrows(cookie, src, dst, n) 681 void *cookie; 682 int src, dst, n; 683 { 684 struct rasops_info *ri = cookie; 685 struct creator_softc *sc = ri->ri_hw; 686 687 if (dst == src) 688 return 0; 689 if (src < 0) { 690 n += src; 691 src = 0; 692 } 693 if ((src + n) > ri->ri_rows) 694 n = ri->ri_rows - src; 695 if (dst < 0) { 696 n += dst; 697 dst = 0; 698 } 699 if ((dst + n) > ri->ri_rows) 700 n = ri->ri_rows - dst; 701 if (n <= 0) 702 return 0; 703 n *= ri->ri_font->fontheight; 704 src *= ri->ri_font->fontheight; 705 dst *= ri->ri_font->fontheight; 706 707 creator_ras_fifo_wait(sc, 8); 708 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 709 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 710 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 711 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 712 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 713 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 714 FBC_WRITE(sc, FFB_FBC_BH, n); 715 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 716 creator_ras_wait(sc); 717 718 return 0; 719 } 720 721 void 722 creator_ras_setfg(sc, fg) 723 struct creator_softc *sc; 724 int32_t fg; 725 { 726 creator_ras_fifo_wait(sc, 1); 727 if (fg == sc->sc_fg_cache) 728 return; 729 sc->sc_fg_cache = fg; 730 FBC_WRITE(sc, FFB_FBC_FG, fg); 731 creator_ras_wait(sc); 732 } 733 734 #ifndef SMALL_KERNEL 735 struct creator_firmware { 736 char fw_ident[8]; 737 u_int32_t fw_size; 738 u_int32_t fw_reserved[2]; 739 u_int32_t fw_ucode[0]; 740 }; 741 742 #define CREATOR_FIRMWARE_REV 0x101 743 744 void 745 creator_load_firmware(void *vsc) 746 { 747 struct creator_softc *sc = vsc; 748 struct creator_firmware *fw; 749 u_int32_t ascr; 750 size_t buflen; 751 u_char *buf; 752 int error; 753 754 error = loadfirmware("afb", &buf, &buflen); 755 if (error) { 756 printf("%s: error %d, could not read firmware %s\n", 757 sc->sc_sunfb.sf_dev.dv_xname, error, "afb"); 758 return; 759 } 760 761 fw = (struct creator_firmware *)buf; 762 if (sizeof(*fw) > buflen || 763 fw->fw_size * sizeof(u_int32_t) > (buflen - sizeof(*fw))) { 764 printf("%s: corrupt firmware\n", sc->sc_sunfb.sf_dev.dv_xname); 765 free(buf, M_DEVBUF, 0); 766 return; 767 } 768 769 printf("%s: firmware rev %d.%d.%d\n", sc->sc_sunfb.sf_dev.dv_xname, 770 (fw->fw_ucode[CREATOR_FIRMWARE_REV] >> 16) & 0xff, 771 (fw->fw_ucode[CREATOR_FIRMWARE_REV] >> 8) & 0xff, 772 fw->fw_ucode[CREATOR_FIRMWARE_REV] & 0xff); 773 774 ascr = FBC_READ(sc, FFB_FBC_ASCR); 775 776 /* Stop all floats. */ 777 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3f); 778 FBC_WRITE(sc, FFB_FBC_ASCR, FBC_ASCR_STOP); 779 780 creator_ras_wait(sc); 781 782 /* Load firmware into all secondary floats. */ 783 if (ascr & 0x3e) { 784 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3e); 785 creator_load_sram(sc, fw->fw_ucode, fw->fw_size); 786 } 787 788 /* Load firmware into primary float. */ 789 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x01); 790 creator_load_sram(sc, fw->fw_ucode, fw->fw_size); 791 792 /* Restart all floats. */ 793 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3f); 794 FBC_WRITE(sc, FFB_FBC_ASCR, FBC_ASCR_RESTART); 795 796 creator_ras_wait(sc); 797 798 free(buf, M_DEVBUF, 0); 799 } 800 #endif /* SMALL_KERNEL */ 801 802 void 803 creator_load_sram(struct creator_softc *sc, u_int32_t *ucode, u_int32_t size) 804 { 805 uint64_t pstate, fprs; 806 caddr_t sram; 807 808 sram = bus_space_vaddr(sc->sc_bt, sc->sc_fbc_h) + FFB_FBC_SRAM36; 809 810 /* 811 * Apparently, loading the firmware into SRAM needs to be done 812 * using block copies. And block copies use the 813 * floating-point registers. Generally, using the FPU in the 814 * kernel is verboten. But since we load the firmware before 815 * userland processes are started, thrashing the 816 * floating-point registers is fine. We do need to enable the 817 * FPU before we access them though, otherwise we'll trap. 818 */ 819 pstate = sparc_rdpr(pstate); 820 sparc_wrpr(pstate, pstate | PSTATE_PEF, 0); 821 fprs = sparc_rd(fprs); 822 sparc_wr(fprs, FPRS_FEF, 0); 823 824 FBC_WRITE(sc, FFB_FBC_SRAMAR, 0); 825 826 while (size > 0) { 827 creator_ras_fifo_wait(sc, 16); 828 829 __asm__ volatile("ld [%0 + 0x00], %%f1\n\t" 830 "ld [%0 + 0x04], %%f0\n\t" 831 "ld [%0 + 0x08], %%f3\n\t" 832 "ld [%0 + 0x0c], %%f2\n\t" 833 "ld [%0 + 0x10], %%f5\n\t" 834 "ld [%0 + 0x14], %%f4\n\t" 835 "ld [%0 + 0x18], %%f7\n\t" 836 "ld [%0 + 0x1c], %%f6\n\t" 837 "ld [%0 + 0x20], %%f9\n\t" 838 "ld [%0 + 0x24], %%f8\n\t" 839 "ld [%0 + 0x28], %%f11\n\t" 840 "ld [%0 + 0x2c], %%f10\n\t" 841 "ld [%0 + 0x30], %%f13\n\t" 842 "ld [%0 + 0x34], %%f12\n\t" 843 "ld [%0 + 0x38], %%f15\n\t" 844 "ld [%0 + 0x3c], %%f14\n\t" 845 "membar #Sync\n\t" 846 "stda %%f0, [%1] 240\n\t" 847 "membar #Sync" 848 : : "r" (ucode), "r" (sram)); 849 850 ucode += 16; 851 size -= 16; 852 } 853 854 sparc_wr(fprs, fprs, 0); 855 sparc_wrpr(pstate, pstate, 0); 856 857 creator_ras_wait(sc); 858 } 859