1 /* $OpenBSD: creator.c,v 1.55 2022/07/15 17:57:26 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/device.h> 33 #include <sys/conf.h> 34 #include <sys/malloc.h> 35 36 #include <machine/bus.h> 37 #include <machine/autoconf.h> 38 #include <machine/openfirm.h> 39 40 #include <dev/wscons/wsconsio.h> 41 #include <dev/wscons/wsdisplayvar.h> 42 #include <dev/rasops/rasops.h> 43 #include <machine/fbvar.h> 44 45 #include <sparc64/dev/creatorreg.h> 46 #include <sparc64/dev/creatorvar.h> 47 48 int creator_match(struct device *, void *, void *); 49 void creator_attach(struct device *, struct device *, void *); 50 int creator_ioctl(void *, u_long, caddr_t, int, struct proc *); 51 paddr_t creator_mmap(void *, off_t, int); 52 53 void creator_ras_fifo_wait(struct creator_softc *, int); 54 void creator_ras_wait(struct creator_softc *); 55 void creator_ras_init(struct creator_softc *); 56 int creator_ras_copyrows(void *, int, int, int); 57 int creator_ras_erasecols(void *, int, int, int, uint32_t); 58 int creator_ras_eraserows(void *, int, int, uint32_t); 59 void creator_ras_fill(struct creator_softc *); 60 void creator_ras_setfg(struct creator_softc *, int32_t); 61 62 int creator_setcursor(struct creator_softc *, struct wsdisplay_cursor *); 63 int creator_updatecursor(struct creator_softc *, u_int); 64 void creator_curs_enable(struct creator_softc *, u_int); 65 66 #ifndef SMALL_KERNEL 67 void creator_load_firmware(struct device *); 68 #endif /* SMALL_KERNEL */ 69 void creator_load_sram(struct creator_softc *, u_int32_t *, u_int32_t); 70 71 struct wsdisplay_accessops creator_accessops = { 72 .ioctl = creator_ioctl, 73 .mmap = creator_mmap 74 }; 75 76 struct cfdriver creator_cd = { 77 NULL, "creator", DV_DULL 78 }; 79 80 const struct cfattach creator_ca = { 81 sizeof(struct creator_softc), creator_match, creator_attach 82 }; 83 84 int 85 creator_match(parent, match, aux) 86 struct device *parent; 87 void *match, *aux; 88 { 89 struct mainbus_attach_args *ma = aux; 90 91 if (strcmp(ma->ma_name, "SUNW,ffb") == 0 || 92 strcmp(ma->ma_name, "SUNW,afb") == 0) 93 return (1); 94 return (0); 95 } 96 97 void 98 creator_attach(parent, self, aux) 99 struct device *parent, *self; 100 void *aux; 101 { 102 struct creator_softc *sc = (struct creator_softc *)self; 103 struct mainbus_attach_args *ma = aux; 104 extern int fbnode; 105 int i, nregs; 106 char *model; 107 int btype; 108 109 sc->sc_bt = ma->ma_bustag; 110 111 nregs = min(ma->ma_nreg, FFB_NREGS); 112 113 if (nregs <= FFB_REG_DFB24) { 114 printf(": no dfb24 regs found\n"); 115 return; 116 } 117 118 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_DFB24].ur_paddr, 119 ma->ma_reg[FFB_REG_DFB24].ur_len, BUS_SPACE_MAP_LINEAR, 120 &sc->sc_pixel_h)) { 121 printf(": failed to map dfb24\n"); 122 return; 123 } 124 125 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_FBC].ur_paddr, 126 ma->ma_reg[FFB_REG_FBC].ur_len, 0, &sc->sc_fbc_h)) { 127 printf(": failed to map fbc\n"); 128 goto unmap_dfb24; 129 } 130 131 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_DAC].ur_paddr, 132 ma->ma_reg[FFB_REG_DAC].ur_len, 0, &sc->sc_dac_h)) { 133 printf(": failed to map dac\n"); 134 goto unmap_fbc; 135 } 136 137 for (i = 0; i < nregs; i++) { 138 sc->sc_addrs[i] = ma->ma_reg[i].ur_paddr; 139 sc->sc_sizes[i] = ma->ma_reg[i].ur_len; 140 } 141 sc->sc_nreg = nregs; 142 143 sc->sc_console = (fbnode == ma->ma_node); 144 sc->sc_node = ma->ma_node; 145 146 if (strcmp(ma->ma_name, "SUNW,afb") == 0) 147 sc->sc_type = FFB_AFB; 148 149 /* 150 * Prom reports only the length of the fcode header, we need 151 * the whole thing. 152 */ 153 sc->sc_sizes[0] = 0x00400000; 154 155 if (sc->sc_type == FFB_CREATOR) { 156 btype = getpropint(sc->sc_node, "board_type", 0); 157 if ((btype & 7) == 3) 158 printf(": Creator3D"); 159 else 160 printf(": Creator"); 161 } else 162 printf(": Elite3D"); 163 164 model = getpropstring(sc->sc_node, "model"); 165 if (model == NULL || strlen(model) == 0) 166 model = "unknown"; 167 168 DAC_WRITE(sc, FFB_DAC_TYPE, DAC_TYPE_GETREV); 169 sc->sc_dacrev = DAC_READ(sc, FFB_DAC_VALUE) >> 28; 170 171 printf(", model %s, dac %u", model, sc->sc_dacrev); 172 173 if (sc->sc_type == FFB_AFB) 174 sc->sc_dacrev = 10; 175 176 fb_setsize(&sc->sc_sunfb, 32, 1152, 900, sc->sc_node, 0); 177 /* linesize has a fixed value, compensate */ 178 sc->sc_sunfb.sf_linebytes = 8192; 179 sc->sc_sunfb.sf_fbsize = sc->sc_sunfb.sf_height * 8192; 180 181 printf(", %dx%d\n", sc->sc_sunfb.sf_width, sc->sc_sunfb.sf_height); 182 183 sc->sc_sunfb.sf_ro.ri_bits = (void *)bus_space_vaddr(sc->sc_bt, 184 sc->sc_pixel_h); 185 sc->sc_sunfb.sf_ro.ri_hw = sc; 186 fbwscons_init(&sc->sc_sunfb, 0, sc->sc_console); 187 188 if ((sc->sc_sunfb.sf_dev.dv_cfdata->cf_flags & CREATOR_CFFLAG_NOACCEL) 189 == 0) { 190 sc->sc_sunfb.sf_ro.ri_ops.eraserows = creator_ras_eraserows; 191 sc->sc_sunfb.sf_ro.ri_ops.erasecols = creator_ras_erasecols; 192 sc->sc_sunfb.sf_ro.ri_ops.copyrows = creator_ras_copyrows; 193 creator_ras_init(sc); 194 195 #ifndef SMALL_KERNEL 196 /* 197 * Elite3D cards need a firmware for accelerated X to 198 * work. Console framebuffer acceleration will work 199 * without it though, so doing this late should be 200 * fine. 201 */ 202 if (sc->sc_type == FFB_AFB) 203 config_mountroot(self, creator_load_firmware); 204 #endif /* SMALL_KERNEL */ 205 } 206 207 if (sc->sc_console) 208 fbwscons_console_init(&sc->sc_sunfb, -1); 209 210 fbwscons_attach(&sc->sc_sunfb, &creator_accessops, sc->sc_console); 211 return; 212 213 unmap_fbc: 214 bus_space_unmap(sc->sc_bt, sc->sc_fbc_h, 215 ma->ma_reg[FFB_REG_FBC].ur_len); 216 unmap_dfb24: 217 bus_space_unmap(sc->sc_bt, sc->sc_pixel_h, 218 ma->ma_reg[FFB_REG_DFB24].ur_len); 219 } 220 221 int 222 creator_ioctl(v, cmd, data, flags, p) 223 void *v; 224 u_long cmd; 225 caddr_t data; 226 int flags; 227 struct proc *p; 228 { 229 struct creator_softc *sc = v; 230 struct wsdisplay_cursor *curs; 231 struct wsdisplay_fbinfo *wdf; 232 struct wsdisplay_curpos *pos; 233 u_char r[2], g[2], b[2]; 234 int error; 235 236 switch (cmd) { 237 case WSDISPLAYIO_GTYPE: 238 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 239 break; 240 case WSDISPLAYIO_SMODE: 241 sc->sc_mode = *(u_int *)data; 242 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 243 struct rasops_info *ri = &sc->sc_sunfb.sf_ro; 244 uint32_t attr; 245 246 if ((sc->sc_sunfb.sf_dev.dv_cfdata->cf_flags & 247 CREATOR_CFFLAG_NOACCEL) == 0) 248 creator_ras_init(sc); 249 250 /* Clear screen. */ 251 ri->ri_ops.pack_attr(ri, 252 WSCOL_BLACK, WSCOL_WHITE, WSATTR_WSCOLORS, &attr); 253 ri->ri_ops.eraserows(ri, 0, ri->ri_rows, attr); 254 } 255 break; 256 case WSDISPLAYIO_GINFO: 257 wdf = (void *)data; 258 wdf->height = sc->sc_sunfb.sf_height; 259 wdf->width = sc->sc_sunfb.sf_width; 260 wdf->depth = 32; 261 wdf->stride = sc->sc_sunfb.sf_linebytes; 262 wdf->offset = 0; 263 wdf->cmsize = 0; 264 break; 265 case WSDISPLAYIO_GETSUPPORTEDDEPTH: 266 *(u_int *)data = WSDISPLAYIO_DEPTH_24_32; 267 break; 268 case WSDISPLAYIO_LINEBYTES: 269 *(u_int *)data = sc->sc_sunfb.sf_linebytes; 270 break; 271 case WSDISPLAYIO_GCURSOR: 272 curs = (struct wsdisplay_cursor *)data; 273 if (curs->which & WSDISPLAY_CURSOR_DOCUR) 274 curs->enable = sc->sc_curs_enabled; 275 if (curs->which & WSDISPLAY_CURSOR_DOPOS) { 276 curs->pos.x = sc->sc_curs_pos.x; 277 curs->pos.y = sc->sc_curs_pos.y; 278 } 279 if (curs->which & WSDISPLAY_CURSOR_DOHOT) { 280 curs->hot.x = sc->sc_curs_hot.x; 281 curs->hot.y = sc->sc_curs_hot.y; 282 } 283 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 284 curs->cmap.index = 0; 285 curs->cmap.count = 2; 286 r[0] = sc->sc_curs_fg >> 0; 287 g[0] = sc->sc_curs_fg >> 8; 288 b[0] = sc->sc_curs_fg >> 16; 289 r[1] = sc->sc_curs_bg >> 0; 290 g[1] = sc->sc_curs_bg >> 8; 291 b[1] = sc->sc_curs_bg >> 16; 292 error = copyout(r, curs->cmap.red, sizeof(r)); 293 if (error) 294 return (error); 295 error = copyout(g, curs->cmap.green, sizeof(g)); 296 if (error) 297 return (error); 298 error = copyout(b, curs->cmap.blue, sizeof(b)); 299 if (error) 300 return (error); 301 } 302 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 303 size_t l; 304 305 curs->size.x = sc->sc_curs_size.x; 306 curs->size.y = sc->sc_curs_size.y; 307 l = (sc->sc_curs_size.x * sc->sc_curs_size.y) / NBBY; 308 error = copyout(sc->sc_curs_image, curs->image, l); 309 if (error) 310 return (error); 311 error = copyout(sc->sc_curs_mask, curs->mask, l); 312 if (error) 313 return (error); 314 } 315 break; 316 case WSDISPLAYIO_SCURPOS: 317 pos = (struct wsdisplay_curpos *)data; 318 sc->sc_curs_pos.x = pos->x; 319 sc->sc_curs_pos.y = pos->y; 320 creator_updatecursor(sc, WSDISPLAY_CURSOR_DOPOS); 321 break; 322 case WSDISPLAYIO_GCURPOS: 323 pos = (struct wsdisplay_curpos *)data; 324 pos->x = sc->sc_curs_pos.x; 325 pos->y = sc->sc_curs_pos.y; 326 break; 327 case WSDISPLAYIO_SCURSOR: 328 curs = (struct wsdisplay_cursor *)data; 329 return (creator_setcursor(sc, curs)); 330 case WSDISPLAYIO_GCURMAX: 331 pos = (struct wsdisplay_curpos *)data; 332 pos->x = CREATOR_CURS_MAX; 333 pos->y = CREATOR_CURS_MAX; 334 break; 335 case WSDISPLAYIO_SVIDEO: 336 case WSDISPLAYIO_GVIDEO: 337 break; 338 339 case WSDISPLAYIO_GETCMAP: 340 case WSDISPLAYIO_PUTCMAP: 341 default: 342 return -1; /* not supported yet */ 343 } 344 345 return (0); 346 } 347 348 int 349 creator_setcursor(struct creator_softc *sc, struct wsdisplay_cursor *curs) 350 { 351 u_int8_t r[2], g[2], b[2], image[128], mask[128]; 352 int error; 353 size_t imcount; 354 355 /* 356 * Do stuff that can generate errors first, then we'll blast it 357 * all at once. 358 */ 359 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 360 if (curs->cmap.count < 2) 361 return (EINVAL); 362 error = copyin(curs->cmap.red, r, sizeof(r)); 363 if (error) 364 return (error); 365 error = copyin(curs->cmap.green, g, sizeof(g)); 366 if (error) 367 return (error); 368 error = copyin(curs->cmap.blue, b, sizeof(b)); 369 if (error) 370 return (error); 371 } 372 373 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 374 if (curs->size.x > CREATOR_CURS_MAX || 375 curs->size.y > CREATOR_CURS_MAX) 376 return (EINVAL); 377 imcount = (curs->size.x * curs->size.y) / NBBY; 378 error = copyin(curs->image, image, imcount); 379 if (error) 380 return (error); 381 error = copyin(curs->mask, mask, imcount); 382 if (error) 383 return (error); 384 } 385 386 /* 387 * Ok, everything is in kernel space and sane, update state. 388 */ 389 390 if (curs->which & WSDISPLAY_CURSOR_DOCUR) 391 sc->sc_curs_enabled = curs->enable; 392 if (curs->which & WSDISPLAY_CURSOR_DOPOS) { 393 sc->sc_curs_pos.x = curs->pos.x; 394 sc->sc_curs_pos.y = curs->pos.y; 395 } 396 if (curs->which & WSDISPLAY_CURSOR_DOHOT) { 397 sc->sc_curs_hot.x = curs->hot.x; 398 sc->sc_curs_hot.y = curs->hot.y; 399 } 400 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 401 sc->sc_curs_fg = ((r[0] << 0) | (g[0] << 8) | (b[0] << 16)); 402 sc->sc_curs_bg = ((r[1] << 0) | (g[1] << 8) | (b[1] << 16)); 403 } 404 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 405 sc->sc_curs_size.x = curs->size.x; 406 sc->sc_curs_size.y = curs->size.y; 407 bcopy(image, sc->sc_curs_image, imcount); 408 bcopy(mask, sc->sc_curs_mask, imcount); 409 } 410 411 creator_updatecursor(sc, curs->which); 412 413 return (0); 414 } 415 416 void 417 creator_curs_enable(struct creator_softc *sc, u_int ena) 418 { 419 u_int32_t v; 420 421 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSENAB); 422 if (sc->sc_dacrev <= 2) 423 v = ena ? 3 : 0; 424 else 425 v = ena ? 0 : 3; 426 DAC_WRITE(sc, FFB_DAC_VALUE2, v); 427 } 428 429 int 430 creator_updatecursor(struct creator_softc *sc, u_int which) 431 { 432 creator_curs_enable(sc, 0); 433 434 if (which & WSDISPLAY_CURSOR_DOCMAP) { 435 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSCMAP); 436 DAC_WRITE(sc, FFB_DAC_VALUE2, sc->sc_curs_fg); 437 DAC_WRITE(sc, FFB_DAC_VALUE2, sc->sc_curs_bg); 438 } 439 440 if (which & (WSDISPLAY_CURSOR_DOPOS | WSDISPLAY_CURSOR_DOHOT)) { 441 u_int32_t x, y; 442 443 x = sc->sc_curs_pos.x + CREATOR_CURS_MAX - sc->sc_curs_hot.x; 444 y = sc->sc_curs_pos.y + CREATOR_CURS_MAX - sc->sc_curs_hot.y; 445 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSPOS); 446 DAC_WRITE(sc, FFB_DAC_VALUE2, 447 ((x & 0xffff) << 16) | (y & 0xffff)); 448 } 449 450 if (which & WSDISPLAY_CURSOR_DOCUR) 451 creator_curs_enable(sc, sc->sc_curs_enabled); 452 453 return (0); 454 } 455 456 const struct creator_mappings { 457 bus_addr_t uoff; 458 bus_addr_t poff; 459 bus_size_t ulen; 460 } creator_map[] = { 461 { FFB_VOFF_SFB8R, FFB_POFF_SFB8R, FFB_VLEN_SFB8R }, 462 { FFB_VOFF_SFB8G, FFB_POFF_SFB8G, FFB_VLEN_SFB8G }, 463 { FFB_VOFF_SFB8B, FFB_POFF_SFB8B, FFB_VLEN_SFB8B }, 464 { FFB_VOFF_SFB8X, FFB_POFF_SFB8X, FFB_VLEN_SFB8X }, 465 { FFB_VOFF_SFB32, FFB_POFF_SFB32, FFB_VLEN_SFB32 }, 466 { FFB_VOFF_SFB64, FFB_POFF_SFB64, FFB_VLEN_SFB64 }, 467 { FFB_VOFF_FBC_REGS, FFB_POFF_FBC_REGS, FFB_VLEN_FBC_REGS }, 468 { FFB_VOFF_BM_FBC_REGS, FFB_POFF_BM_FBC_REGS, FFB_VLEN_BM_FBC_REGS }, 469 { FFB_VOFF_DFB8R, FFB_POFF_DFB8R, FFB_VLEN_DFB8R }, 470 { FFB_VOFF_DFB8G, FFB_POFF_DFB8G, FFB_VLEN_DFB8G }, 471 { FFB_VOFF_DFB8B, FFB_POFF_DFB8B, FFB_VLEN_DFB8B }, 472 { FFB_VOFF_DFB8X, FFB_POFF_DFB8X, FFB_VLEN_DFB8X }, 473 { FFB_VOFF_DFB24, FFB_POFF_DFB24, FFB_VLEN_DFB24 }, 474 { FFB_VOFF_DFB32, FFB_POFF_DFB32, FFB_VLEN_DFB32 }, 475 { FFB_VOFF_DFB422A, FFB_POFF_DFB422A, FFB_VLEN_DFB422A }, 476 { FFB_VOFF_DFB422AD, FFB_POFF_DFB422AD, FFB_VLEN_DFB422AD }, 477 { FFB_VOFF_DFB24B, FFB_POFF_DFB24B, FFB_VLEN_DFB24B }, 478 { FFB_VOFF_DFB422B, FFB_POFF_DFB422B, FFB_VLEN_DFB422B }, 479 { FFB_VOFF_DFB422BD, FFB_POFF_DFB422BD, FFB_VLEN_DFB422BD }, 480 { FFB_VOFF_SFB16Z, FFB_POFF_SFB16Z, FFB_VLEN_SFB16Z }, 481 { FFB_VOFF_SFB8Z, FFB_POFF_SFB8Z, FFB_VLEN_SFB8Z }, 482 { FFB_VOFF_SFB422, FFB_POFF_SFB422, FFB_VLEN_SFB422 }, 483 { FFB_VOFF_SFB422D, FFB_POFF_SFB422D, FFB_VLEN_SFB422D }, 484 { FFB_VOFF_FBC_KREGS, FFB_POFF_FBC_KREGS, FFB_VLEN_FBC_KREGS }, 485 { FFB_VOFF_DAC, FFB_POFF_DAC, FFB_VLEN_DAC }, 486 { FFB_VOFF_PROM, FFB_POFF_PROM, FFB_VLEN_PROM }, 487 { FFB_VOFF_EXP, FFB_POFF_EXP, FFB_VLEN_EXP }, 488 }; 489 #define CREATOR_NMAPPINGS nitems(creator_map) 490 491 paddr_t 492 creator_mmap(vsc, off, prot) 493 void *vsc; 494 off_t off; 495 int prot; 496 { 497 paddr_t x; 498 struct creator_softc *sc = vsc; 499 int i; 500 501 switch (sc->sc_mode) { 502 case WSDISPLAYIO_MODE_MAPPED: 503 /* Turn virtual offset into physical offset */ 504 for (i = 0; i < CREATOR_NMAPPINGS; i++) { 505 if (off >= creator_map[i].uoff && 506 off < (creator_map[i].uoff + creator_map[i].ulen)) 507 break; 508 } 509 if (i == CREATOR_NMAPPINGS) 510 break; 511 512 off -= creator_map[i].uoff; 513 off += creator_map[i].poff; 514 off += sc->sc_addrs[0]; 515 516 /* Map based on physical offset */ 517 for (i = 0; i < sc->sc_nreg; i++) { 518 /* Before this set? */ 519 if (off < sc->sc_addrs[i]) 520 continue; 521 /* After this set? */ 522 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 523 continue; 524 525 x = bus_space_mmap(sc->sc_bt, 0, off, prot, 526 BUS_SPACE_MAP_LINEAR); 527 return (x); 528 } 529 break; 530 case WSDISPLAYIO_MODE_DUMBFB: 531 if (sc->sc_nreg <= FFB_REG_DFB24) 532 break; 533 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 534 return (bus_space_mmap(sc->sc_bt, 535 sc->sc_addrs[FFB_REG_DFB24], off, prot, 536 BUS_SPACE_MAP_LINEAR)); 537 break; 538 } 539 540 return (-1); 541 } 542 543 void 544 creator_ras_fifo_wait(sc, n) 545 struct creator_softc *sc; 546 int n; 547 { 548 int32_t cache = sc->sc_fifo_cache; 549 550 if (cache < n) { 551 do { 552 cache = FBC_READ(sc, FFB_FBC_UCSR); 553 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 554 } while (cache < n); 555 } 556 sc->sc_fifo_cache = cache - n; 557 } 558 559 void 560 creator_ras_wait(sc) 561 struct creator_softc *sc; 562 { 563 u_int32_t ucsr, r; 564 565 while (1) { 566 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 567 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 568 break; 569 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 570 if (r != 0) 571 FBC_WRITE(sc, FFB_FBC_UCSR, r); 572 } 573 } 574 575 void 576 creator_ras_init(sc) 577 struct creator_softc *sc; 578 { 579 creator_ras_fifo_wait(sc, 7); 580 FBC_WRITE(sc, FFB_FBC_PPC, 581 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | 582 FBC_PPC_APE_DIS | FBC_PPC_CS_CONST); 583 FBC_WRITE(sc, FFB_FBC_FBC, 584 FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 585 FFB_FBC_XE_OFF | FFB_FBC_RGBE_MASK); 586 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 587 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 588 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 589 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 590 sc->sc_fg_cache = 0; 591 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 592 creator_ras_wait(sc); 593 } 594 595 int 596 creator_ras_eraserows(cookie, row, n, attr) 597 void *cookie; 598 int row, n; 599 uint32_t attr; 600 { 601 struct rasops_info *ri = cookie; 602 struct creator_softc *sc = ri->ri_hw; 603 int bg, fg; 604 605 if (row < 0) { 606 n += row; 607 row = 0; 608 } 609 if (row + n > ri->ri_rows) 610 n = ri->ri_rows - row; 611 if (n <= 0) 612 return 0; 613 614 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 615 creator_ras_fill(sc); 616 creator_ras_setfg(sc, ri->ri_devcmap[bg]); 617 creator_ras_fifo_wait(sc, 4); 618 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 619 FBC_WRITE(sc, FFB_FBC_BY, 0); 620 FBC_WRITE(sc, FFB_FBC_BX, 0); 621 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 622 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 623 } else { 624 row *= ri->ri_font->fontheight; 625 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 626 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 627 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 628 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 629 } 630 creator_ras_wait(sc); 631 632 return 0; 633 } 634 635 int 636 creator_ras_erasecols(cookie, row, col, n, attr) 637 void *cookie; 638 int row, col, n; 639 uint32_t attr; 640 { 641 struct rasops_info *ri = cookie; 642 struct creator_softc *sc = ri->ri_hw; 643 int fg, bg; 644 645 if ((row < 0) || (row >= ri->ri_rows)) 646 return 0; 647 if (col < 0) { 648 n += col; 649 col = 0; 650 } 651 if (col + n > ri->ri_cols) 652 n = ri->ri_cols - col; 653 if (n <= 0) 654 return 0; 655 n *= ri->ri_font->fontwidth; 656 col *= ri->ri_font->fontwidth; 657 row *= ri->ri_font->fontheight; 658 659 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 660 creator_ras_fill(sc); 661 creator_ras_setfg(sc, ri->ri_devcmap[bg]); 662 creator_ras_fifo_wait(sc, 4); 663 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 664 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 665 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 666 FBC_WRITE(sc, FFB_FBC_BW, n - 1); 667 creator_ras_wait(sc); 668 669 return 0; 670 } 671 672 void 673 creator_ras_fill(sc) 674 struct creator_softc *sc; 675 { 676 creator_ras_fifo_wait(sc, 2); 677 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 678 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 679 creator_ras_wait(sc); 680 } 681 682 int 683 creator_ras_copyrows(cookie, src, dst, n) 684 void *cookie; 685 int src, dst, n; 686 { 687 struct rasops_info *ri = cookie; 688 struct creator_softc *sc = ri->ri_hw; 689 690 if (dst == src) 691 return 0; 692 if (src < 0) { 693 n += src; 694 src = 0; 695 } 696 if ((src + n) > ri->ri_rows) 697 n = ri->ri_rows - src; 698 if (dst < 0) { 699 n += dst; 700 dst = 0; 701 } 702 if ((dst + n) > ri->ri_rows) 703 n = ri->ri_rows - dst; 704 if (n <= 0) 705 return 0; 706 n *= ri->ri_font->fontheight; 707 src *= ri->ri_font->fontheight; 708 dst *= ri->ri_font->fontheight; 709 710 creator_ras_fifo_wait(sc, 8); 711 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 712 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 713 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 714 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 715 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 716 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 717 FBC_WRITE(sc, FFB_FBC_BH, n); 718 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 719 creator_ras_wait(sc); 720 721 return 0; 722 } 723 724 void 725 creator_ras_setfg(sc, fg) 726 struct creator_softc *sc; 727 int32_t fg; 728 { 729 creator_ras_fifo_wait(sc, 1); 730 if (fg == sc->sc_fg_cache) 731 return; 732 sc->sc_fg_cache = fg; 733 FBC_WRITE(sc, FFB_FBC_FG, fg); 734 creator_ras_wait(sc); 735 } 736 737 #ifndef SMALL_KERNEL 738 struct creator_firmware { 739 char fw_ident[8]; 740 u_int32_t fw_size; 741 u_int32_t fw_reserved[2]; 742 u_int32_t fw_ucode[0]; 743 }; 744 745 #define CREATOR_FIRMWARE_REV 0x101 746 747 void 748 creator_load_firmware(struct device *self) 749 { 750 struct creator_softc *sc = (struct creator_softc *)self; 751 struct creator_firmware *fw; 752 u_int32_t ascr; 753 size_t buflen; 754 u_char *buf; 755 int error; 756 757 error = loadfirmware("afb", &buf, &buflen); 758 if (error) { 759 printf("%s: error %d, could not read firmware %s\n", 760 sc->sc_sunfb.sf_dev.dv_xname, error, "afb"); 761 return; 762 } 763 764 fw = (struct creator_firmware *)buf; 765 if (sizeof(*fw) > buflen || 766 fw->fw_size * sizeof(u_int32_t) > (buflen - sizeof(*fw))) { 767 printf("%s: corrupt firmware\n", sc->sc_sunfb.sf_dev.dv_xname); 768 free(buf, M_DEVBUF, 0); 769 return; 770 } 771 772 printf("%s: firmware rev %d.%d.%d\n", sc->sc_sunfb.sf_dev.dv_xname, 773 (fw->fw_ucode[CREATOR_FIRMWARE_REV] >> 16) & 0xff, 774 (fw->fw_ucode[CREATOR_FIRMWARE_REV] >> 8) & 0xff, 775 fw->fw_ucode[CREATOR_FIRMWARE_REV] & 0xff); 776 777 ascr = FBC_READ(sc, FFB_FBC_ASCR); 778 779 /* Stop all floats. */ 780 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3f); 781 FBC_WRITE(sc, FFB_FBC_ASCR, FBC_ASCR_STOP); 782 783 creator_ras_wait(sc); 784 785 /* Load firmware into all secondary floats. */ 786 if (ascr & 0x3e) { 787 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3e); 788 creator_load_sram(sc, fw->fw_ucode, fw->fw_size); 789 } 790 791 /* Load firmware into primary float. */ 792 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x01); 793 creator_load_sram(sc, fw->fw_ucode, fw->fw_size); 794 795 /* Restart all floats. */ 796 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3f); 797 FBC_WRITE(sc, FFB_FBC_ASCR, FBC_ASCR_RESTART); 798 799 creator_ras_wait(sc); 800 801 free(buf, M_DEVBUF, 0); 802 } 803 #endif /* SMALL_KERNEL */ 804 805 void 806 creator_load_sram(struct creator_softc *sc, u_int32_t *ucode, u_int32_t size) 807 { 808 uint64_t pstate, fprs; 809 caddr_t sram; 810 811 sram = bus_space_vaddr(sc->sc_bt, sc->sc_fbc_h) + FFB_FBC_SRAM36; 812 813 /* 814 * Apparently, loading the firmware into SRAM needs to be done 815 * using block copies. And block copies use the 816 * floating-point registers. Generally, using the FPU in the 817 * kernel is verboten. But since we load the firmware before 818 * userland processes are started, thrashing the 819 * floating-point registers is fine. We do need to enable the 820 * FPU before we access them though, otherwise we'll trap. 821 */ 822 pstate = sparc_rdpr(pstate); 823 sparc_wrpr(pstate, pstate | PSTATE_PEF, 0); 824 fprs = sparc_rd(fprs); 825 sparc_wr(fprs, FPRS_FEF, 0); 826 827 FBC_WRITE(sc, FFB_FBC_SRAMAR, 0); 828 829 while (size > 0) { 830 creator_ras_fifo_wait(sc, 16); 831 832 __asm__ volatile("ld [%0 + 0x00], %%f1\n\t" 833 "ld [%0 + 0x04], %%f0\n\t" 834 "ld [%0 + 0x08], %%f3\n\t" 835 "ld [%0 + 0x0c], %%f2\n\t" 836 "ld [%0 + 0x10], %%f5\n\t" 837 "ld [%0 + 0x14], %%f4\n\t" 838 "ld [%0 + 0x18], %%f7\n\t" 839 "ld [%0 + 0x1c], %%f6\n\t" 840 "ld [%0 + 0x20], %%f9\n\t" 841 "ld [%0 + 0x24], %%f8\n\t" 842 "ld [%0 + 0x28], %%f11\n\t" 843 "ld [%0 + 0x2c], %%f10\n\t" 844 "ld [%0 + 0x30], %%f13\n\t" 845 "ld [%0 + 0x34], %%f12\n\t" 846 "ld [%0 + 0x38], %%f15\n\t" 847 "ld [%0 + 0x3c], %%f14\n\t" 848 "membar #Sync\n\t" 849 "stda %%f0, [%1] 240\n\t" 850 "membar #Sync" 851 : : "r" (ucode), "r" (sram)); 852 853 ucode += 16; 854 size -= 16; 855 } 856 857 sparc_wr(fprs, fprs, 0); 858 sparc_wrpr(pstate, pstate, 0); 859 860 creator_ras_wait(sc); 861 } 862