1 /* $OpenBSD: creator.c,v 1.50 2015/12/11 16:07:01 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/types.h> 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/device.h> 34 #include <sys/conf.h> 35 #include <sys/malloc.h> 36 37 #include <machine/bus.h> 38 #include <machine/autoconf.h> 39 #include <machine/openfirm.h> 40 41 #include <dev/wscons/wsconsio.h> 42 #include <dev/wscons/wsdisplayvar.h> 43 #include <dev/rasops/rasops.h> 44 #include <machine/fbvar.h> 45 46 #include <sparc64/dev/creatorreg.h> 47 #include <sparc64/dev/creatorvar.h> 48 49 int creator_match(struct device *, void *, void *); 50 void creator_attach(struct device *, struct device *, void *); 51 int creator_ioctl(void *, u_long, caddr_t, int, struct proc *); 52 paddr_t creator_mmap(void *, off_t, int); 53 54 void creator_ras_fifo_wait(struct creator_softc *, int); 55 void creator_ras_wait(struct creator_softc *); 56 void creator_ras_init(struct creator_softc *); 57 int creator_ras_copyrows(void *, int, int, int); 58 int creator_ras_erasecols(void *, int, int, int, long int); 59 int creator_ras_eraserows(void *, int, int, long int); 60 void creator_ras_fill(struct creator_softc *); 61 void creator_ras_setfg(struct creator_softc *, int32_t); 62 63 int creator_setcursor(struct creator_softc *, struct wsdisplay_cursor *); 64 int creator_updatecursor(struct creator_softc *, u_int); 65 void creator_curs_enable(struct creator_softc *, u_int); 66 67 #ifndef SMALL_KERNEL 68 void creator_load_firmware(struct device *); 69 #endif /* SMALL_KERNEL */ 70 void creator_load_sram(struct creator_softc *, u_int32_t *, u_int32_t); 71 72 struct wsdisplay_accessops creator_accessops = { 73 .ioctl = creator_ioctl, 74 .mmap = creator_mmap 75 }; 76 77 struct cfdriver creator_cd = { 78 NULL, "creator", DV_DULL 79 }; 80 81 struct cfattach creator_ca = { 82 sizeof(struct creator_softc), creator_match, creator_attach 83 }; 84 85 int 86 creator_match(parent, match, aux) 87 struct device *parent; 88 void *match, *aux; 89 { 90 struct mainbus_attach_args *ma = aux; 91 92 if (strcmp(ma->ma_name, "SUNW,ffb") == 0 || 93 strcmp(ma->ma_name, "SUNW,afb") == 0) 94 return (1); 95 return (0); 96 } 97 98 void 99 creator_attach(parent, self, aux) 100 struct device *parent, *self; 101 void *aux; 102 { 103 struct creator_softc *sc = (struct creator_softc *)self; 104 struct mainbus_attach_args *ma = aux; 105 extern int fbnode; 106 int i, nregs; 107 char *model; 108 int btype; 109 110 sc->sc_bt = ma->ma_bustag; 111 112 nregs = min(ma->ma_nreg, FFB_NREGS); 113 114 if (nregs <= FFB_REG_DFB24) { 115 printf(": no dfb24 regs found\n"); 116 return; 117 } 118 119 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_DFB24].ur_paddr, 120 ma->ma_reg[FFB_REG_DFB24].ur_len, BUS_SPACE_MAP_LINEAR, 121 &sc->sc_pixel_h)) { 122 printf(": failed to map dfb24\n"); 123 return; 124 } 125 126 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_FBC].ur_paddr, 127 ma->ma_reg[FFB_REG_FBC].ur_len, 0, &sc->sc_fbc_h)) { 128 printf(": failed to map fbc\n"); 129 goto unmap_dfb24; 130 } 131 132 if (bus_space_map(sc->sc_bt, ma->ma_reg[FFB_REG_DAC].ur_paddr, 133 ma->ma_reg[FFB_REG_DAC].ur_len, 0, &sc->sc_dac_h)) { 134 printf(": failed to map dac\n"); 135 goto unmap_fbc; 136 } 137 138 for (i = 0; i < nregs; i++) { 139 sc->sc_addrs[i] = ma->ma_reg[i].ur_paddr; 140 sc->sc_sizes[i] = ma->ma_reg[i].ur_len; 141 } 142 sc->sc_nreg = nregs; 143 144 sc->sc_console = (fbnode == ma->ma_node); 145 sc->sc_node = ma->ma_node; 146 147 if (strcmp(ma->ma_name, "SUNW,afb") == 0) 148 sc->sc_type = FFB_AFB; 149 150 /* 151 * Prom reports only the length of the fcode header, we need 152 * the whole thing. 153 */ 154 sc->sc_sizes[0] = 0x00400000; 155 156 if (sc->sc_type == FFB_CREATOR) { 157 btype = getpropint(sc->sc_node, "board_type", 0); 158 if ((btype & 7) == 3) 159 printf(": Creator3D"); 160 else 161 printf(": Creator"); 162 } else 163 printf(": Elite3D"); 164 165 model = getpropstring(sc->sc_node, "model"); 166 if (model == NULL || strlen(model) == 0) 167 model = "unknown"; 168 169 DAC_WRITE(sc, FFB_DAC_TYPE, DAC_TYPE_GETREV); 170 sc->sc_dacrev = DAC_READ(sc, FFB_DAC_VALUE) >> 28; 171 172 printf(", model %s, dac %u", model, sc->sc_dacrev); 173 174 if (sc->sc_type == FFB_AFB) 175 sc->sc_dacrev = 10; 176 177 fb_setsize(&sc->sc_sunfb, 32, 1152, 900, sc->sc_node, 0); 178 /* linesize has a fixed value, compensate */ 179 sc->sc_sunfb.sf_linebytes = 8192; 180 sc->sc_sunfb.sf_fbsize = sc->sc_sunfb.sf_height * 8192; 181 182 printf(", %dx%d\n", sc->sc_sunfb.sf_width, sc->sc_sunfb.sf_height); 183 184 sc->sc_sunfb.sf_ro.ri_bits = (void *)bus_space_vaddr(sc->sc_bt, 185 sc->sc_pixel_h); 186 sc->sc_sunfb.sf_ro.ri_hw = sc; 187 fbwscons_init(&sc->sc_sunfb, 0, sc->sc_console); 188 189 if ((sc->sc_sunfb.sf_dev.dv_cfdata->cf_flags & CREATOR_CFFLAG_NOACCEL) 190 == 0) { 191 sc->sc_sunfb.sf_ro.ri_ops.eraserows = creator_ras_eraserows; 192 sc->sc_sunfb.sf_ro.ri_ops.erasecols = creator_ras_erasecols; 193 sc->sc_sunfb.sf_ro.ri_ops.copyrows = creator_ras_copyrows; 194 creator_ras_init(sc); 195 196 #ifndef SMALL_KERNEL 197 /* 198 * Elite3D cards need a firmware for accelerated X to 199 * work. Console framebuffer acceleration will work 200 * without it though, so doing this late should be 201 * fine. 202 */ 203 if (sc->sc_type == FFB_AFB) 204 config_mountroot(self, creator_load_firmware); 205 #endif /* SMALL_KERNEL */ 206 } 207 208 if (sc->sc_console) 209 fbwscons_console_init(&sc->sc_sunfb, -1); 210 211 fbwscons_attach(&sc->sc_sunfb, &creator_accessops, sc->sc_console); 212 return; 213 214 unmap_fbc: 215 bus_space_unmap(sc->sc_bt, sc->sc_fbc_h, 216 ma->ma_reg[FFB_REG_FBC].ur_len); 217 unmap_dfb24: 218 bus_space_unmap(sc->sc_bt, sc->sc_pixel_h, 219 ma->ma_reg[FFB_REG_DFB24].ur_len); 220 } 221 222 int 223 creator_ioctl(v, cmd, data, flags, p) 224 void *v; 225 u_long cmd; 226 caddr_t data; 227 int flags; 228 struct proc *p; 229 { 230 struct creator_softc *sc = v; 231 struct wsdisplay_cursor *curs; 232 struct wsdisplay_fbinfo *wdf; 233 struct wsdisplay_curpos *pos; 234 u_char r[2], g[2], b[2]; 235 int error; 236 237 switch (cmd) { 238 case WSDISPLAYIO_GTYPE: 239 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 240 break; 241 case WSDISPLAYIO_SMODE: 242 sc->sc_mode = *(u_int *)data; 243 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 244 struct rasops_info *ri = &sc->sc_sunfb.sf_ro; 245 long attr; 246 247 if ((sc->sc_sunfb.sf_dev.dv_cfdata->cf_flags & 248 CREATOR_CFFLAG_NOACCEL) == 0) 249 creator_ras_init(sc); 250 251 /* Clear screen. */ 252 ri->ri_ops.alloc_attr(ri, 253 WSCOL_BLACK, WSCOL_WHITE, WSATTR_WSCOLORS, &attr); 254 ri->ri_ops.eraserows(ri, 0, ri->ri_rows, attr); 255 } 256 break; 257 case WSDISPLAYIO_GINFO: 258 wdf = (void *)data; 259 wdf->height = sc->sc_sunfb.sf_height; 260 wdf->width = sc->sc_sunfb.sf_width; 261 wdf->depth = 32; 262 wdf->cmsize = 0; 263 break; 264 case WSDISPLAYIO_GETSUPPORTEDDEPTH: 265 *(u_int *)data = WSDISPLAYIO_DEPTH_24_32; 266 break; 267 case WSDISPLAYIO_LINEBYTES: 268 *(u_int *)data = sc->sc_sunfb.sf_linebytes; 269 break; 270 case WSDISPLAYIO_GCURSOR: 271 curs = (struct wsdisplay_cursor *)data; 272 if (curs->which & WSDISPLAY_CURSOR_DOCUR) 273 curs->enable = sc->sc_curs_enabled; 274 if (curs->which & WSDISPLAY_CURSOR_DOPOS) { 275 curs->pos.x = sc->sc_curs_pos.x; 276 curs->pos.y = sc->sc_curs_pos.y; 277 } 278 if (curs->which & WSDISPLAY_CURSOR_DOHOT) { 279 curs->hot.x = sc->sc_curs_hot.x; 280 curs->hot.y = sc->sc_curs_hot.y; 281 } 282 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 283 curs->cmap.index = 0; 284 curs->cmap.count = 2; 285 r[0] = sc->sc_curs_fg >> 0; 286 g[0] = sc->sc_curs_fg >> 8; 287 b[0] = sc->sc_curs_fg >> 16; 288 r[1] = sc->sc_curs_bg >> 0; 289 g[1] = sc->sc_curs_bg >> 8; 290 b[1] = sc->sc_curs_bg >> 16; 291 error = copyout(r, curs->cmap.red, sizeof(r)); 292 if (error) 293 return (error); 294 error = copyout(g, curs->cmap.green, sizeof(g)); 295 if (error) 296 return (error); 297 error = copyout(b, curs->cmap.blue, sizeof(b)); 298 if (error) 299 return (error); 300 } 301 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 302 size_t l; 303 304 curs->size.x = sc->sc_curs_size.x; 305 curs->size.y = sc->sc_curs_size.y; 306 l = (sc->sc_curs_size.x * sc->sc_curs_size.y) / NBBY; 307 error = copyout(sc->sc_curs_image, curs->image, l); 308 if (error) 309 return (error); 310 error = copyout(sc->sc_curs_mask, curs->mask, l); 311 if (error) 312 return (error); 313 } 314 break; 315 case WSDISPLAYIO_SCURPOS: 316 pos = (struct wsdisplay_curpos *)data; 317 sc->sc_curs_pos.x = pos->x; 318 sc->sc_curs_pos.y = pos->y; 319 creator_updatecursor(sc, WSDISPLAY_CURSOR_DOPOS); 320 break; 321 case WSDISPLAYIO_GCURPOS: 322 pos = (struct wsdisplay_curpos *)data; 323 pos->x = sc->sc_curs_pos.x; 324 pos->y = sc->sc_curs_pos.y; 325 break; 326 case WSDISPLAYIO_SCURSOR: 327 curs = (struct wsdisplay_cursor *)data; 328 return (creator_setcursor(sc, curs)); 329 case WSDISPLAYIO_GCURMAX: 330 pos = (struct wsdisplay_curpos *)data; 331 pos->x = CREATOR_CURS_MAX; 332 pos->y = CREATOR_CURS_MAX; 333 break; 334 case WSDISPLAYIO_SVIDEO: 335 case WSDISPLAYIO_GVIDEO: 336 break; 337 338 case WSDISPLAYIO_GETCMAP: 339 case WSDISPLAYIO_PUTCMAP: 340 default: 341 return -1; /* not supported yet */ 342 } 343 344 return (0); 345 } 346 347 int 348 creator_setcursor(struct creator_softc *sc, struct wsdisplay_cursor *curs) 349 { 350 u_int8_t r[2], g[2], b[2], image[128], mask[128]; 351 int error; 352 size_t imcount; 353 354 /* 355 * Do stuff that can generate errors first, then we'll blast it 356 * all at once. 357 */ 358 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 359 if (curs->cmap.count < 2) 360 return (EINVAL); 361 error = copyin(curs->cmap.red, r, sizeof(r)); 362 if (error) 363 return (error); 364 error = copyin(curs->cmap.green, g, sizeof(g)); 365 if (error) 366 return (error); 367 error = copyin(curs->cmap.blue, b, sizeof(b)); 368 if (error) 369 return (error); 370 } 371 372 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 373 if (curs->size.x > CREATOR_CURS_MAX || 374 curs->size.y > CREATOR_CURS_MAX) 375 return (EINVAL); 376 imcount = (curs->size.x * curs->size.y) / NBBY; 377 error = copyin(curs->image, image, imcount); 378 if (error) 379 return (error); 380 error = copyin(curs->mask, mask, imcount); 381 if (error) 382 return (error); 383 } 384 385 /* 386 * Ok, everything is in kernel space and sane, update state. 387 */ 388 389 if (curs->which & WSDISPLAY_CURSOR_DOCUR) 390 sc->sc_curs_enabled = curs->enable; 391 if (curs->which & WSDISPLAY_CURSOR_DOPOS) { 392 sc->sc_curs_pos.x = curs->pos.x; 393 sc->sc_curs_pos.y = curs->pos.y; 394 } 395 if (curs->which & WSDISPLAY_CURSOR_DOHOT) { 396 sc->sc_curs_hot.x = curs->hot.x; 397 sc->sc_curs_hot.y = curs->hot.y; 398 } 399 if (curs->which & WSDISPLAY_CURSOR_DOCMAP) { 400 sc->sc_curs_fg = ((r[0] << 0) | (g[0] << 8) | (b[0] << 16)); 401 sc->sc_curs_bg = ((r[1] << 0) | (g[1] << 8) | (b[1] << 16)); 402 } 403 if (curs->which & WSDISPLAY_CURSOR_DOSHAPE) { 404 sc->sc_curs_size.x = curs->size.x; 405 sc->sc_curs_size.y = curs->size.y; 406 bcopy(image, sc->sc_curs_image, imcount); 407 bcopy(mask, sc->sc_curs_mask, imcount); 408 } 409 410 creator_updatecursor(sc, curs->which); 411 412 return (0); 413 } 414 415 void 416 creator_curs_enable(struct creator_softc *sc, u_int ena) 417 { 418 u_int32_t v; 419 420 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSENAB); 421 if (sc->sc_dacrev <= 2) 422 v = ena ? 3 : 0; 423 else 424 v = ena ? 0 : 3; 425 DAC_WRITE(sc, FFB_DAC_VALUE2, v); 426 } 427 428 int 429 creator_updatecursor(struct creator_softc *sc, u_int which) 430 { 431 creator_curs_enable(sc, 0); 432 433 if (which & WSDISPLAY_CURSOR_DOCMAP) { 434 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSCMAP); 435 DAC_WRITE(sc, FFB_DAC_VALUE2, sc->sc_curs_fg); 436 DAC_WRITE(sc, FFB_DAC_VALUE2, sc->sc_curs_bg); 437 } 438 439 if (which & (WSDISPLAY_CURSOR_DOPOS | WSDISPLAY_CURSOR_DOHOT)) { 440 u_int32_t x, y; 441 442 x = sc->sc_curs_pos.x + CREATOR_CURS_MAX - sc->sc_curs_hot.x; 443 y = sc->sc_curs_pos.y + CREATOR_CURS_MAX - sc->sc_curs_hot.y; 444 DAC_WRITE(sc, FFB_DAC_TYPE2, DAC_TYPE2_CURSPOS); 445 DAC_WRITE(sc, FFB_DAC_VALUE2, 446 ((x & 0xffff) << 16) | (y & 0xffff)); 447 } 448 449 if (which & WSDISPLAY_CURSOR_DOCUR) 450 creator_curs_enable(sc, sc->sc_curs_enabled); 451 452 return (0); 453 } 454 455 const struct creator_mappings { 456 bus_addr_t uoff; 457 bus_addr_t poff; 458 bus_size_t ulen; 459 } creator_map[] = { 460 { FFB_VOFF_SFB8R, FFB_POFF_SFB8R, FFB_VLEN_SFB8R }, 461 { FFB_VOFF_SFB8G, FFB_POFF_SFB8G, FFB_VLEN_SFB8G }, 462 { FFB_VOFF_SFB8B, FFB_POFF_SFB8B, FFB_VLEN_SFB8B }, 463 { FFB_VOFF_SFB8X, FFB_POFF_SFB8X, FFB_VLEN_SFB8X }, 464 { FFB_VOFF_SFB32, FFB_POFF_SFB32, FFB_VLEN_SFB32 }, 465 { FFB_VOFF_SFB64, FFB_POFF_SFB64, FFB_VLEN_SFB64 }, 466 { FFB_VOFF_FBC_REGS, FFB_POFF_FBC_REGS, FFB_VLEN_FBC_REGS }, 467 { FFB_VOFF_BM_FBC_REGS, FFB_POFF_BM_FBC_REGS, FFB_VLEN_BM_FBC_REGS }, 468 { FFB_VOFF_DFB8R, FFB_POFF_DFB8R, FFB_VLEN_DFB8R }, 469 { FFB_VOFF_DFB8G, FFB_POFF_DFB8G, FFB_VLEN_DFB8G }, 470 { FFB_VOFF_DFB8B, FFB_POFF_DFB8B, FFB_VLEN_DFB8B }, 471 { FFB_VOFF_DFB8X, FFB_POFF_DFB8X, FFB_VLEN_DFB8X }, 472 { FFB_VOFF_DFB24, FFB_POFF_DFB24, FFB_VLEN_DFB24 }, 473 { FFB_VOFF_DFB32, FFB_POFF_DFB32, FFB_VLEN_DFB32 }, 474 { FFB_VOFF_DFB422A, FFB_POFF_DFB422A, FFB_VLEN_DFB422A }, 475 { FFB_VOFF_DFB422AD, FFB_POFF_DFB422AD, FFB_VLEN_DFB422AD }, 476 { FFB_VOFF_DFB24B, FFB_POFF_DFB24B, FFB_VLEN_DFB24B }, 477 { FFB_VOFF_DFB422B, FFB_POFF_DFB422B, FFB_VLEN_DFB422B }, 478 { FFB_VOFF_DFB422BD, FFB_POFF_DFB422BD, FFB_VLEN_DFB422BD }, 479 { FFB_VOFF_SFB16Z, FFB_POFF_SFB16Z, FFB_VLEN_SFB16Z }, 480 { FFB_VOFF_SFB8Z, FFB_POFF_SFB8Z, FFB_VLEN_SFB8Z }, 481 { FFB_VOFF_SFB422, FFB_POFF_SFB422, FFB_VLEN_SFB422 }, 482 { FFB_VOFF_SFB422D, FFB_POFF_SFB422D, FFB_VLEN_SFB422D }, 483 { FFB_VOFF_FBC_KREGS, FFB_POFF_FBC_KREGS, FFB_VLEN_FBC_KREGS }, 484 { FFB_VOFF_DAC, FFB_POFF_DAC, FFB_VLEN_DAC }, 485 { FFB_VOFF_PROM, FFB_POFF_PROM, FFB_VLEN_PROM }, 486 { FFB_VOFF_EXP, FFB_POFF_EXP, FFB_VLEN_EXP }, 487 }; 488 #define CREATOR_NMAPPINGS nitems(creator_map) 489 490 paddr_t 491 creator_mmap(vsc, off, prot) 492 void *vsc; 493 off_t off; 494 int prot; 495 { 496 paddr_t x; 497 struct creator_softc *sc = vsc; 498 int i; 499 500 switch (sc->sc_mode) { 501 case WSDISPLAYIO_MODE_MAPPED: 502 /* Turn virtual offset into physical offset */ 503 for (i = 0; i < CREATOR_NMAPPINGS; i++) { 504 if (off >= creator_map[i].uoff && 505 off < (creator_map[i].uoff + creator_map[i].ulen)) 506 break; 507 } 508 if (i == CREATOR_NMAPPINGS) 509 break; 510 511 off -= creator_map[i].uoff; 512 off += creator_map[i].poff; 513 off += sc->sc_addrs[0]; 514 515 /* Map based on physical offset */ 516 for (i = 0; i < sc->sc_nreg; i++) { 517 /* Before this set? */ 518 if (off < sc->sc_addrs[i]) 519 continue; 520 /* After this set? */ 521 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 522 continue; 523 524 x = bus_space_mmap(sc->sc_bt, 0, off, prot, 525 BUS_SPACE_MAP_LINEAR); 526 return (x); 527 } 528 break; 529 case WSDISPLAYIO_MODE_DUMBFB: 530 if (sc->sc_nreg <= FFB_REG_DFB24) 531 break; 532 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 533 return (bus_space_mmap(sc->sc_bt, 534 sc->sc_addrs[FFB_REG_DFB24], off, prot, 535 BUS_SPACE_MAP_LINEAR)); 536 break; 537 } 538 539 return (-1); 540 } 541 542 void 543 creator_ras_fifo_wait(sc, n) 544 struct creator_softc *sc; 545 int n; 546 { 547 int32_t cache = sc->sc_fifo_cache; 548 549 if (cache < n) { 550 do { 551 cache = FBC_READ(sc, FFB_FBC_UCSR); 552 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 553 } while (cache < n); 554 } 555 sc->sc_fifo_cache = cache - n; 556 } 557 558 void 559 creator_ras_wait(sc) 560 struct creator_softc *sc; 561 { 562 u_int32_t ucsr, r; 563 564 while (1) { 565 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 566 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 567 break; 568 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 569 if (r != 0) 570 FBC_WRITE(sc, FFB_FBC_UCSR, r); 571 } 572 } 573 574 void 575 creator_ras_init(sc) 576 struct creator_softc *sc; 577 { 578 creator_ras_fifo_wait(sc, 7); 579 FBC_WRITE(sc, FFB_FBC_PPC, 580 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | 581 FBC_PPC_APE_DIS | FBC_PPC_CS_CONST); 582 FBC_WRITE(sc, FFB_FBC_FBC, 583 FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 584 FFB_FBC_XE_OFF | FFB_FBC_RGBE_MASK); 585 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 586 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 587 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 588 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 589 sc->sc_fg_cache = 0; 590 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 591 creator_ras_wait(sc); 592 } 593 594 int 595 creator_ras_eraserows(cookie, row, n, attr) 596 void *cookie; 597 int row, n; 598 long int attr; 599 { 600 struct rasops_info *ri = cookie; 601 struct creator_softc *sc = ri->ri_hw; 602 int bg, fg; 603 604 if (row < 0) { 605 n += row; 606 row = 0; 607 } 608 if (row + n > ri->ri_rows) 609 n = ri->ri_rows - row; 610 if (n <= 0) 611 return 0; 612 613 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 614 creator_ras_fill(sc); 615 creator_ras_setfg(sc, ri->ri_devcmap[bg]); 616 creator_ras_fifo_wait(sc, 4); 617 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 618 FBC_WRITE(sc, FFB_FBC_BY, 0); 619 FBC_WRITE(sc, FFB_FBC_BX, 0); 620 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 621 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 622 } else { 623 row *= ri->ri_font->fontheight; 624 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 625 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 626 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 627 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 628 } 629 creator_ras_wait(sc); 630 631 return 0; 632 } 633 634 int 635 creator_ras_erasecols(cookie, row, col, n, attr) 636 void *cookie; 637 int row, col, n; 638 long int attr; 639 { 640 struct rasops_info *ri = cookie; 641 struct creator_softc *sc = ri->ri_hw; 642 int fg, bg; 643 644 if ((row < 0) || (row >= ri->ri_rows)) 645 return 0; 646 if (col < 0) { 647 n += col; 648 col = 0; 649 } 650 if (col + n > ri->ri_cols) 651 n = ri->ri_cols - col; 652 if (n <= 0) 653 return 0; 654 n *= ri->ri_font->fontwidth; 655 col *= ri->ri_font->fontwidth; 656 row *= ri->ri_font->fontheight; 657 658 ri->ri_ops.unpack_attr(cookie, attr, &fg, &bg, NULL); 659 creator_ras_fill(sc); 660 creator_ras_setfg(sc, ri->ri_devcmap[bg]); 661 creator_ras_fifo_wait(sc, 4); 662 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 663 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 664 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 665 FBC_WRITE(sc, FFB_FBC_BW, n - 1); 666 creator_ras_wait(sc); 667 668 return 0; 669 } 670 671 void 672 creator_ras_fill(sc) 673 struct creator_softc *sc; 674 { 675 creator_ras_fifo_wait(sc, 2); 676 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 677 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 678 creator_ras_wait(sc); 679 } 680 681 int 682 creator_ras_copyrows(cookie, src, dst, n) 683 void *cookie; 684 int src, dst, n; 685 { 686 struct rasops_info *ri = cookie; 687 struct creator_softc *sc = ri->ri_hw; 688 689 if (dst == src) 690 return 0; 691 if (src < 0) { 692 n += src; 693 src = 0; 694 } 695 if ((src + n) > ri->ri_rows) 696 n = ri->ri_rows - src; 697 if (dst < 0) { 698 n += dst; 699 dst = 0; 700 } 701 if ((dst + n) > ri->ri_rows) 702 n = ri->ri_rows - dst; 703 if (n <= 0) 704 return 0; 705 n *= ri->ri_font->fontheight; 706 src *= ri->ri_font->fontheight; 707 dst *= ri->ri_font->fontheight; 708 709 creator_ras_fifo_wait(sc, 8); 710 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 711 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 712 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 713 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 714 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 715 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 716 FBC_WRITE(sc, FFB_FBC_BH, n); 717 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 718 creator_ras_wait(sc); 719 720 return 0; 721 } 722 723 void 724 creator_ras_setfg(sc, fg) 725 struct creator_softc *sc; 726 int32_t fg; 727 { 728 creator_ras_fifo_wait(sc, 1); 729 if (fg == sc->sc_fg_cache) 730 return; 731 sc->sc_fg_cache = fg; 732 FBC_WRITE(sc, FFB_FBC_FG, fg); 733 creator_ras_wait(sc); 734 } 735 736 #ifndef SMALL_KERNEL 737 struct creator_firmware { 738 char fw_ident[8]; 739 u_int32_t fw_size; 740 u_int32_t fw_reserved[2]; 741 u_int32_t fw_ucode[0]; 742 }; 743 744 #define CREATOR_FIRMWARE_REV 0x101 745 746 void 747 creator_load_firmware(struct device *self) 748 { 749 struct creator_softc *sc = (struct creator_softc *)self; 750 struct creator_firmware *fw; 751 u_int32_t ascr; 752 size_t buflen; 753 u_char *buf; 754 int error; 755 756 error = loadfirmware("afb", &buf, &buflen); 757 if (error) { 758 printf("%s: error %d, could not read firmware %s\n", 759 sc->sc_sunfb.sf_dev.dv_xname, error, "afb"); 760 return; 761 } 762 763 fw = (struct creator_firmware *)buf; 764 if (sizeof(*fw) > buflen || 765 fw->fw_size * sizeof(u_int32_t) > (buflen - sizeof(*fw))) { 766 printf("%s: corrupt firmware\n", sc->sc_sunfb.sf_dev.dv_xname); 767 free(buf, M_DEVBUF, 0); 768 return; 769 } 770 771 printf("%s: firmware rev %d.%d.%d\n", sc->sc_sunfb.sf_dev.dv_xname, 772 (fw->fw_ucode[CREATOR_FIRMWARE_REV] >> 16) & 0xff, 773 (fw->fw_ucode[CREATOR_FIRMWARE_REV] >> 8) & 0xff, 774 fw->fw_ucode[CREATOR_FIRMWARE_REV] & 0xff); 775 776 ascr = FBC_READ(sc, FFB_FBC_ASCR); 777 778 /* Stop all floats. */ 779 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3f); 780 FBC_WRITE(sc, FFB_FBC_ASCR, FBC_ASCR_STOP); 781 782 creator_ras_wait(sc); 783 784 /* Load firmware into all secondary floats. */ 785 if (ascr & 0x3e) { 786 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3e); 787 creator_load_sram(sc, fw->fw_ucode, fw->fw_size); 788 } 789 790 /* Load firmware into primary float. */ 791 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x01); 792 creator_load_sram(sc, fw->fw_ucode, fw->fw_size); 793 794 /* Restart all floats. */ 795 FBC_WRITE(sc, FFB_FBC_FEM, ascr & 0x3f); 796 FBC_WRITE(sc, FFB_FBC_ASCR, FBC_ASCR_RESTART); 797 798 creator_ras_wait(sc); 799 800 free(buf, M_DEVBUF, 0); 801 } 802 #endif /* SMALL_KERNEL */ 803 804 void 805 creator_load_sram(struct creator_softc *sc, u_int32_t *ucode, u_int32_t size) 806 { 807 uint64_t pstate, fprs; 808 caddr_t sram; 809 810 sram = bus_space_vaddr(sc->sc_bt, sc->sc_fbc_h) + FFB_FBC_SRAM36; 811 812 /* 813 * Apparently, loading the firmware into SRAM needs to be done 814 * using block copies. And block copies use the 815 * floating-point registers. Generally, using the FPU in the 816 * kernel is verboten. But since we load the firmware before 817 * userland processes are started, thrashing the 818 * floating-point registers is fine. We do need to enable the 819 * FPU before we access them though, otherwise we'll trap. 820 */ 821 pstate = sparc_rdpr(pstate); 822 sparc_wrpr(pstate, pstate | PSTATE_PEF, 0); 823 fprs = sparc_rd(fprs); 824 sparc_wr(fprs, FPRS_FEF, 0); 825 826 FBC_WRITE(sc, FFB_FBC_SRAMAR, 0); 827 828 while (size > 0) { 829 creator_ras_fifo_wait(sc, 16); 830 831 __asm__ volatile("ld [%0 + 0x00], %%f1\n\t" 832 "ld [%0 + 0x04], %%f0\n\t" 833 "ld [%0 + 0x08], %%f3\n\t" 834 "ld [%0 + 0x0c], %%f2\n\t" 835 "ld [%0 + 0x10], %%f5\n\t" 836 "ld [%0 + 0x14], %%f4\n\t" 837 "ld [%0 + 0x18], %%f7\n\t" 838 "ld [%0 + 0x1c], %%f6\n\t" 839 "ld [%0 + 0x20], %%f9\n\t" 840 "ld [%0 + 0x24], %%f8\n\t" 841 "ld [%0 + 0x28], %%f11\n\t" 842 "ld [%0 + 0x2c], %%f10\n\t" 843 "ld [%0 + 0x30], %%f13\n\t" 844 "ld [%0 + 0x34], %%f12\n\t" 845 "ld [%0 + 0x38], %%f15\n\t" 846 "ld [%0 + 0x3c], %%f14\n\t" 847 "membar #Sync\n\t" 848 "stda %%f0, [%1] 240\n\t" 849 "membar #Sync" 850 : : "r" (ucode), "r" (sram)); 851 852 ucode += 16; 853 size -= 16; 854 } 855 856 sparc_wr(fprs, fprs, 0); 857 sparc_wrpr(pstate, pstate, 0); 858 859 creator_ras_wait(sc); 860 } 861