1 /* $OpenBSD: cache_sh4.h,v 1.2 2008/06/26 05:42:12 ray Exp $ */ 2 /* $NetBSD: cache_sh4.h,v 1.11 2006/03/04 01:55:03 uwe Exp $ */ 3 4 /*- 5 * Copyright (c) 2002 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by UCHIYAMA Yasushi. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * SH4: SH7750 SH7750S SH7750R SH7751 SH7751R 35 */ 36 37 #ifndef _SH_CACHE_SH4_H_ 38 #define _SH_CACHE_SH4_H_ 39 #include <sh/devreg.h> 40 #ifdef _KERNEL 41 42 #define SH4_ICACHE_SIZE 8192 43 #define SH4_DCACHE_SIZE 16384 44 #define SH4_EMODE_ICACHE_SIZE 16384 45 #define SH4_EMODE_DCACHE_SIZE 32768 46 #define SH4_CACHE_LINESZ 32 47 48 #define SH4_CCR 0xff00001c 49 #define SH4_CCR_EMODE 0x80000000 50 #define SH4_CCR_IIX 0x00008000 51 #define SH4_CCR_ICI 0x00000800 52 #define SH4_CCR_ICE 0x00000100 53 #define SH4_CCR_OIX 0x00000080 54 #define SH4_CCR_ORA 0x00000020 55 #define SH4_CCR_OCI 0x00000008 56 #define SH4_CCR_CB 0x00000004 57 #define SH4_CCR_WT 0x00000002 58 #define SH4_CCR_OCE 0x00000001 59 60 #define SH4_QACR0 0xff000038 61 #define SH4_QACR1 0xff00003c 62 #define SH4_QACR_AREA_SHIFT 2 63 #define SH4_QACR_AREA_MASK 0x0000001c 64 65 /* I-cache address/data array */ 66 #define SH4_CCIA 0xf0000000 67 /* address specification */ 68 #define CCIA_A 0x00000008 /* associate bit */ 69 #define CCIA_ENTRY_SHIFT 5 /* line size 32B */ 70 #define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 71 #define CCIA_EMODE_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ 72 /* data specification */ 73 #define CCIA_V 0x00000001 74 #define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 75 76 #define SH4_CCID 0xf1000000 77 /* address specification */ 78 #define CCID_L_SHIFT 2 79 #define CCID_L_MASK 0x1c /* line-size is 32B */ 80 #define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 81 82 /* D-cache address/data array */ 83 #define SH4_CCDA 0xf4000000 84 /* address specification */ 85 #define CCDA_A 0x00000008 /* associate bit */ 86 #define CCDA_ENTRY_SHIFT 5 /* line size 32B */ 87 #define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ 88 /* data specification */ 89 #define CCDA_V 0x00000001 90 #define CCDA_U 0x00000002 91 #define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 92 93 #define SH4_CCDD 0xf5000000 94 95 /* Store Queue */ 96 #define SH4_SQ 0xe0000000 97 98 /* 99 * cache flush macro for locore level code. 100 */ 101 #define SH4_CACHE_FLUSH() \ 102 do { \ 103 uint32_t __e, __a; \ 104 \ 105 /* D-cache */ \ 106 for (__e = 0; __e < (SH4_DCACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\ 107 __a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \ 108 (*(volatile uint32_t *)__a) &= ~(CCDA_U | CCDA_V); \ 109 } \ 110 /* I-cache */ \ 111 for (__e = 0; __e < (SH4_ICACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\ 112 __a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \ 113 (*(volatile uint32_t *)__a) &= ~(CCIA_V); \ 114 } \ 115 } while(/*CONSTCOND*/0) 116 117 #define SH4_EMODE_CACHE_FLUSH() \ 118 do { \ 119 uint32_t __e, __a; \ 120 \ 121 /* D-cache */ \ 122 for (__e = 0;__e < (SH4_EMODE_DCACHE_SIZE / SH4_CACHE_LINESZ);__e++) {\ 123 __a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \ 124 (*(volatile uint32_t *)__a) &= ~(CCDA_U | CCDA_V); \ 125 } \ 126 /* I-cache */ \ 127 for (__e = 0;__e < (SH4_EMODE_ICACHE_SIZE / SH4_CACHE_LINESZ);__e++) {\ 128 __a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \ 129 (*(volatile uint32_t *)__a) &= ~(CCIA_V); \ 130 } \ 131 } while(/*CONSTCOND*/0) 132 133 #define SH7750_CACHE_FLUSH() SH4_CACHE_FLUSH() 134 #define SH7750S_CACHE_FLUSH() SH4_CACHE_FLUSH() 135 #define SH7751_CACHE_FLUSH() SH4_CACHE_FLUSH() 136 #if defined(SH4_CACHE_DISABLE_EMODE) 137 #define SH7750R_CACHE_FLUSH() SH4_CACHE_FLUSH() 138 #define SH7751R_CACHE_FLUSH() SH4_CACHE_FLUSH() 139 #else 140 #define SH7750R_CACHE_FLUSH() SH4_EMODE_CACHE_FLUSH() 141 #define SH7751R_CACHE_FLUSH() SH4_EMODE_CACHE_FLUSH() 142 #endif 143 144 #ifndef _LOCORE 145 extern void sh4_cache_config(void); 146 #endif 147 #endif /* _KERNEL */ 148 #endif /* !_SH_CACHE_SH4_H_ */ 149