1 /* $OpenBSD: intr.h,v 1.23 2003/07/14 19:23:52 drahn Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Per Fogelstrom, Opsycon AB and RTMX Inc, USA. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed under OpenBSD by 17 * Per Fogelstrom, Opsycon AB, Sweden for RTMX Inc, North Carolina USA. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 */ 34 35 #ifndef _POWERPC_INTR_H_ 36 #define _POWERPC_INTR_H_ 37 38 #define IPL_BIO 0 39 #define IPL_AUDIO IPL_BIO /* XXX - was defined this val in audio_if.h */ 40 #define IPL_NET 1 41 #define IPL_TTY 2 42 #define IPL_IMP 3 43 #define IPL_CLOCK 4 44 #define IPL_NONE 5 45 #define IPL_HIGH 6 46 47 #define IST_NONE 0 48 #define IST_PULSE 1 49 #define IST_EDGE 2 50 #define IST_LEVEL 3 51 52 #ifndef _LOCORE 53 54 #define PPC_NIRQ 66 55 #define PPC_CLK_IRQ 64 56 #define PPC_STAT_IRQ 65 57 extern int intrcnt[PPC_NIRQ]; 58 59 void setsoftclock(void); 60 void clearsoftclock(void); 61 int splsoftclock(void); 62 void setsoftnet(void); 63 void clearsoftnet(void); 64 int splsoftnet(void); 65 66 void do_pending_int(void); 67 68 69 volatile extern int cpl, ipending, astpending; 70 extern int imask[7]; 71 72 /* SPL asserts */ 73 #define splassert(wantipl) /* nothing */ 74 75 /* 76 * Reorder protection in the following inline functions is 77 * achived with an empty asm volatile statement. the compiler 78 * will not move instructions past asm volatiles. 79 */ 80 volatile static __inline int 81 splraise(int newcpl) 82 { 83 int oldcpl; 84 85 __asm__ volatile("":::"memory"); /* don't reorder.... */ 86 oldcpl = cpl; 87 cpl = oldcpl | newcpl; 88 __asm__ volatile("":::"memory"); /* don't reorder.... */ 89 return(oldcpl); 90 } 91 92 volatile static __inline void 93 splx(int newcpl) 94 { 95 __asm__ volatile("":::"memory"); /* reorder protect */ 96 cpl = newcpl; 97 if(ipending & ~newcpl) 98 do_pending_int(); 99 __asm__ volatile("":::"memory"); /* reorder protect */ 100 } 101 102 volatile static __inline int 103 spllower(int newcpl) 104 { 105 int oldcpl; 106 107 __asm__ volatile("":::"memory"); /* reorder protect */ 108 oldcpl = cpl; 109 cpl = newcpl; 110 if(ipending & ~newcpl) 111 do_pending_int(); 112 __asm__ volatile("":::"memory"); /* reorder protect */ 113 return(oldcpl); 114 } 115 116 /* Following code should be implemented with lwarx/stwcx to avoid 117 * the disable/enable. i need to read the manual once more.... */ 118 static __inline void 119 set_sint(int pending) 120 { 121 int msrsave; 122 123 __asm__ ("mfmsr %0" : "=r"(msrsave)); 124 __asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 125 ipending |= pending; 126 __asm__ volatile ("mtmsr %0" :: "r"(msrsave)); 127 } 128 129 #define SINT_CLOCK 0x10000000 130 #define SINT_NET 0x20000000 131 #define SINT_TTY 0x40000000 132 #define SPL_CLOCK 0x80000000 133 #define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_TTY) 134 135 #define splbio() splraise(imask[IPL_BIO]) 136 #define splnet() splraise(imask[IPL_NET]) 137 #define spltty() splraise(imask[IPL_TTY]) 138 #define splimp() splraise(imask[IPL_IMP]) 139 #define splaudio() splraise(imask[IPL_AUDIO]) 140 #define splclock() splraise(imask[IPL_CLOCK]) 141 #define splvm() splraise(imask[IPL_IMP]) 142 #define splstatclock() splhigh() 143 #define spllowersoftclock() spllower(SINT_CLOCK) 144 #define splsoftclock() splraise(SINT_CLOCK) 145 #define splsoftnet() splraise(SINT_NET) 146 #define splsofttty() splraise(SINT_TTY) 147 148 #define setsoftclock() set_sint(SINT_CLOCK); 149 #define setsoftnet() set_sint(SINT_NET); 150 #define setsofttty() set_sint(SINT_TTY); 151 152 #define splhigh() splraise(0xffffffff) 153 #define spl0() spllower(0) 154 155 /* 156 * Interrupt control struct used to control the ICU setup. 157 */ 158 159 struct intrhand { 160 struct intrhand *ih_next; 161 int (*ih_fun)(void *); 162 void *ih_arg; 163 u_long ih_count; 164 int ih_level; 165 int ih_irq; 166 char *ih_what; 167 }; 168 extern int ppc_configed_intr_cnt; 169 #define MAX_PRECONF_INTR 16 170 extern struct intrhand ppc_configed_intr[MAX_PRECONF_INTR]; 171 void softnet(int isr); 172 173 #endif /* _LOCORE */ 174 175 176 #endif /* _POWERPC_INTR_H_ */ 177