1 /* $OpenBSD: intr.h,v 1.11 2001/06/24 23:26:29 drahn Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Per Fogelstrom, Opsycon AB and RTMX Inc, USA. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed under OpenBSD by 17 * Per Fogelstrom, Opsycon AB, Sweden for RTMX Inc, North Carolina USA. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 */ 34 35 #ifndef _MACHINE_INTR_H_ 36 #define _MACHINE_INTR_H_ 37 38 #define IPL_BIO 0 39 #define IPL_NET 1 40 #define IPL_TTY 2 41 #define IPL_IMP 3 42 #define IPL_CLOCK 4 43 #define IPL_NONE 5 44 #define IPL_HIGH 6 45 46 #define IST_NONE 0 47 #define IST_PULSE 1 48 #define IST_EDGE 2 49 #define IST_LEVEL 3 50 51 #ifndef _LOCORE 52 53 #define PPC_NIRQ 65 54 #define PPC_CLK_IRQ 64 55 extern int intrcnt[PPC_NIRQ]; 56 57 void setsoftclock __P((void)); 58 void clearsoftclock __P((void)); 59 int splsoftclock __P((void)); 60 void setsoftnet __P((void)); 61 void clearsoftnet __P((void)); 62 int splsoftnet __P((void)); 63 64 void do_pending_int __P((void)); 65 66 67 volatile extern int cpl, ipending, astpending, tickspending; 68 extern int imask[7]; 69 70 /* 71 * Reorder protection in the following inline functions is 72 * achived with the "eieio" instruction which the assembler 73 * seems to detect and then doen't move instructions past.... 74 */ 75 static __inline int 76 splraise(int newcpl) 77 { 78 int oldcpl; 79 80 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 81 oldcpl = cpl; 82 cpl = oldcpl | newcpl; 83 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 84 return(oldcpl); 85 } 86 87 static __inline void 88 splx(int newcpl) 89 { 90 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 91 cpl = newcpl; 92 if(ipending & ~newcpl) 93 do_pending_int(); 94 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 95 } 96 97 static __inline int 98 spllower(int newcpl) 99 { 100 int oldcpl; 101 102 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 103 oldcpl = cpl; 104 cpl = newcpl; 105 if(ipending & ~newcpl) 106 do_pending_int(); 107 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 108 return(oldcpl); 109 } 110 111 /* Following code should be implemented with lwarx/stwcx to avoid 112 * the disable/enable. i need to read the manual once more.... */ 113 static __inline void 114 set_sint(int pending) 115 { 116 int msrsave; 117 118 __asm__ ("mfmsr %0" : "=r"(msrsave)); 119 __asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 120 ipending |= pending; 121 __asm__ volatile ("mtmsr %0" :: "r"(msrsave)); 122 } 123 124 #define SINT_CLOCK 0x10000000 125 #define SINT_NET 0x20000000 126 #define SINT_TTY 0x40000000 127 #define SPL_CLOCK 0x80000000 128 #define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_TTY) 129 130 #define splbio() splraise(imask[IPL_BIO]) 131 #define splnet() splraise(imask[IPL_NET]) 132 #define spltty() splraise(imask[IPL_TTY]) 133 #define splclock() splraise(SPL_CLOCK|SINT_MASK) 134 #define splimp() splraise(imask[IPL_IMP]) 135 #define splvm() splraise(imask[IPL_IMP]) 136 #define splstatclock() splhigh() 137 #define spllowersoftclock() spllower(SINT_CLOCK) 138 #define splsoftclock() splraise(SINT_CLOCK) 139 #define splsoftnet() splraise(SINT_NET) 140 #define splsofttty() splraise(SINT_TTY) 141 142 #define setsoftclock() set_sint(SINT_CLOCK); 143 #define setsoftnet() set_sint(SINT_NET); 144 #define setsofttty() set_sint(SINT_TTY); 145 146 #define splhigh() splraise(0xffffffff) 147 #define spl0() spllower(0) 148 149 /* 150 * Interrupt control struct used to control the ICU setup. 151 */ 152 153 struct intrhand { 154 struct intrhand *ih_next; 155 int (*ih_fun) __P((void *)); 156 void *ih_arg; 157 u_long ih_count; 158 int ih_level; 159 int ih_irq; 160 char *ih_what; 161 }; 162 extern int ppc_configed_intr_cnt; 163 #define MAX_PRECONF_INTR 16 164 extern struct intrhand ppc_configed_intr[MAX_PRECONF_INTR]; 165 void softnet(int isr); 166 167 #endif /* _LOCORE */ 168 169 170 #endif /* _MACHINE_INTR_H_ */ 171