1 /* $OpenBSD: intr.h,v 1.25 2003/10/31 03:04:16 drahn Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Per Fogelstrom, Opsycon AB and RTMX Inc, USA. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed under OpenBSD by 17 * Per Fogelstrom, Opsycon AB, Sweden for RTMX Inc, North Carolina USA. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 */ 34 35 #ifndef _POWERPC_INTR_H_ 36 #define _POWERPC_INTR_H_ 37 38 #define IPL_NONE 0 39 #define IPL_BIO 1 40 #define IPL_AUDIO IPL_BIO /* XXX - was defined this val in audio_if.h */ 41 #define IPL_NET 2 42 #define IPL_TTY 3 43 #define IPL_IMP 4 44 #define IPL_CLOCK 5 45 #define IPL_HIGH 6 46 #define IPL_NUM 7 47 48 #define IST_NONE 0 49 #define IST_PULSE 1 50 #define IST_EDGE 2 51 #define IST_LEVEL 3 52 53 #ifndef _LOCORE 54 55 #define PPC_NIRQ 66 56 #define PPC_CLK_IRQ 64 57 #define PPC_STAT_IRQ 65 58 extern int intrcnt[PPC_NIRQ]; 59 60 void setsoftclock(void); 61 void clearsoftclock(void); 62 int splsoftclock(void); 63 void setsoftnet(void); 64 void clearsoftnet(void); 65 int splsoftnet(void); 66 67 void do_pending_int(void); 68 69 70 volatile extern int cpl, ipending, astpending; 71 extern int imask[IPL_NUM]; 72 73 /* SPL asserts */ 74 #define splassert(wantipl) /* nothing */ 75 76 /* 77 * Reorder protection in the following inline functions is 78 * achived with an empty asm volatile statement. the compiler 79 * will not move instructions past asm volatiles. 80 */ 81 volatile static __inline int 82 splraise(int newcpl) 83 { 84 int oldcpl; 85 86 __asm__ volatile("":::"memory"); /* don't reorder.... */ 87 oldcpl = cpl; 88 cpl = oldcpl | newcpl; 89 __asm__ volatile("":::"memory"); /* don't reorder.... */ 90 return(oldcpl); 91 } 92 93 volatile static __inline void 94 splx(int newcpl) 95 { 96 __asm__ volatile("":::"memory"); /* reorder protect */ 97 cpl = newcpl; 98 if(ipending & ~newcpl) 99 do_pending_int(); 100 __asm__ volatile("":::"memory"); /* reorder protect */ 101 } 102 103 volatile static __inline int 104 spllower(int newcpl) 105 { 106 int oldcpl; 107 108 __asm__ volatile("":::"memory"); /* reorder protect */ 109 oldcpl = cpl; 110 cpl = newcpl; 111 if(ipending & ~newcpl) 112 do_pending_int(); 113 __asm__ volatile("":::"memory"); /* reorder protect */ 114 return(oldcpl); 115 } 116 117 /* Following code should be implemented with lwarx/stwcx to avoid 118 * the disable/enable. i need to read the manual once more.... */ 119 static __inline void 120 set_sint(int pending) 121 { 122 int msrsave; 123 124 __asm__ ("mfmsr %0" : "=r"(msrsave)); 125 __asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 126 ipending |= pending; 127 __asm__ volatile ("mtmsr %0" :: "r"(msrsave)); 128 } 129 130 #define SINT_CLOCK 0x10000000 131 #define SINT_NET 0x20000000 132 #define SINT_TTY 0x40000000 133 #define SPL_CLOCK 0x80000000 134 #define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_TTY) 135 136 #define splbio() splraise(imask[IPL_BIO]) 137 #define splnet() splraise(imask[IPL_NET]) 138 #define spltty() splraise(imask[IPL_TTY]) 139 #define splimp() splraise(imask[IPL_IMP]) 140 #define splaudio() splraise(imask[IPL_AUDIO]) 141 #define splclock() splraise(imask[IPL_CLOCK]) 142 #define splvm() splraise(imask[IPL_IMP]) 143 #define splstatclock() splhigh() 144 #define spllowersoftclock() spllower(SINT_CLOCK) 145 #define splsoftclock() splraise(SINT_CLOCK) 146 #define splsoftnet() splraise(SINT_NET) 147 #define splsofttty() splraise(SINT_TTY) 148 149 #define setsoftclock() set_sint(SINT_CLOCK); 150 #define setsoftnet() set_sint(SINT_NET); 151 #define setsofttty() set_sint(SINT_TTY); 152 153 #define splhigh() splraise(0xffffffff) 154 #define spl0() spllower(0) 155 156 /* 157 * Interrupt control struct used to control the ICU setup. 158 */ 159 160 struct intrhand { 161 struct intrhand *ih_next; 162 int (*ih_fun)(void *); 163 void *ih_arg; 164 u_long ih_count; 165 int ih_level; 166 int ih_irq; 167 char *ih_what; 168 }; 169 extern int ppc_configed_intr_cnt; 170 #define MAX_PRECONF_INTR 16 171 extern struct intrhand ppc_configed_intr[MAX_PRECONF_INTR]; 172 void softnet(int isr); 173 174 #endif /* _LOCORE */ 175 #endif /* _POWERPC_INTR_H_ */ 176