1 /* $OpenBSD: cpu.h,v 1.44 2009/03/26 17:24:33 oga Exp $ */ 2 /* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */ 3 4 /* 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 #ifndef _POWERPC_CPU_H_ 35 #define _POWERPC_CPU_H_ 36 37 #include <machine/frame.h> 38 39 #include <sys/device.h> 40 #include <sys/lock.h> 41 #include <sys/sched.h> 42 43 struct cpu_info { 44 struct device *ci_dev; /* our device */ 45 struct schedstate_percpu ci_schedstate; /* scheduler state */ 46 47 struct proc *ci_curproc; 48 49 struct pcb *ci_curpcb; 50 struct pmap *ci_curpm; 51 struct proc *ci_fpuproc; 52 struct proc *ci_vecproc; 53 int ci_cpuid; 54 55 volatile int ci_want_resched; 56 volatile int ci_cpl; 57 volatile int ci_iactive; 58 #define CI_IACTIVE_PROCESSING_SOFT 1 59 #define CI_IACTIVE_PROCESSING_HARD 2 60 volatile int ci_ipending; 61 62 int ci_intrdepth; 63 char *ci_intstk; 64 #define CPUSAVE_LEN 8 65 register_t ci_tempsave[CPUSAVE_LEN]; 66 register_t ci_ddbsave[CPUSAVE_LEN]; 67 #define DISISAVE_LEN 4 68 register_t ci_disisave[DISISAVE_LEN]; 69 70 volatile u_int64_t ci_nexttimerevent; 71 volatile u_int64_t ci_prevtb; 72 volatile u_int64_t ci_lasttb; 73 volatile u_int64_t ci_nextstatevent; 74 int ci_statspending; 75 76 volatile int ci_ddb_paused; 77 #define CI_DDB_RUNNING 0 78 #define CI_DDB_SHOULDSTOP 1 79 #define CI_DDB_STOPPED 2 80 #define CI_DDB_ENTERDDB 3 81 #define CI_DDB_INDDB 4 82 83 u_int32_t ci_randseed; 84 }; 85 86 static __inline struct cpu_info * 87 curcpu(void) 88 { 89 struct cpu_info *ci; 90 91 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 92 return ci; 93 } 94 95 #define curpcb (curcpu()->ci_curpcb) 96 #define curpm (curcpu()->ci_curpm) 97 98 #define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0) 99 100 #ifdef MULTIPROCESSOR 101 102 #define PPC_MAXPROCS 4 103 104 static __inline int 105 cpu_number(void) 106 { 107 int pir; 108 109 pir = curcpu()->ci_cpuid; 110 return pir; 111 } 112 113 void cpu_boot_secondary_processors(void); 114 115 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 116 #define CPU_INFO_ITERATOR int 117 #define CPU_INFO_FOREACH(cii, ci) \ 118 for (cii = 0, ci = &cpu_info[0]; cii < ncpus; cii++, ci++) 119 120 void cpu_unidle(struct cpu_info *); 121 122 #else 123 124 #define PPC_MAXPROCS 1 125 126 #define cpu_number() 0 127 128 #define CPU_IS_PRIMARY(ci) 1 129 #define CPU_INFO_ITERATOR int 130 #define CPU_INFO_FOREACH(cii, ci) \ 131 for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL) 132 133 #define cpu_unidle(ci) 134 135 #endif 136 137 #define MAXCPUS PPC_MAXPROCS 138 139 extern struct cpu_info cpu_info[PPC_MAXPROCS]; 140 141 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 142 #define CLKF_PC(frame) ((frame)->srr0) 143 #define CLKF_INTR(frame) ((frame)->depth != 0) 144 145 /* 146 * This is used during profiling to integrate system time. 147 */ 148 #define PROC_PC(p) (trapframe(p)->srr0) 149 150 void delay(unsigned); 151 #define DELAY(n) delay(n) 152 153 #define aston(p) ((p)->p_md.md_astpending = 1) 154 155 /* 156 * Preempt the current process if in interrupt from user mode, 157 * or after the current trap/syscall if in system mode. 158 */ 159 #define need_resched(ci) \ 160 do { \ 161 ci->ci_want_resched = 1; \ 162 if (ci->ci_curproc != NULL) \ 163 aston(ci->ci_curproc); \ 164 } while (0) 165 #define clear_resched(ci) (ci)->ci_want_resched = 0 166 167 #define need_proftick(p) aston(p) 168 169 void signotify(struct proc *); 170 171 extern char *bootpath; 172 173 #ifndef CACHELINESIZE 174 #define CACHELINESIZE 32 /* For now XXX */ 175 #endif 176 177 static __inline void 178 syncicache(void *from, int len) 179 { 180 int l; 181 char *p = from; 182 183 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 184 l = len; 185 186 do { 187 __asm __volatile ("dcbst 0,%0" :: "r"(p)); 188 p += CACHELINESIZE; 189 } while ((l -= CACHELINESIZE) > 0); 190 __asm __volatile ("sync"); 191 p = from; 192 l = len; 193 do { 194 __asm __volatile ("icbi 0,%0" :: "r"(p)); 195 p += CACHELINESIZE; 196 } while ((l -= CACHELINESIZE) > 0); 197 __asm __volatile ("isync"); 198 } 199 200 static __inline void 201 invdcache(void *from, int len) 202 { 203 int l; 204 char *p = from; 205 206 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 207 l = len; 208 209 do { 210 __asm __volatile ("dcbi 0,%0" :: "r"(p)); 211 p += CACHELINESIZE; 212 } while ((l -= CACHELINESIZE) > 0); 213 __asm __volatile ("sync"); 214 } 215 216 #define FUNC_SPR(n, name) \ 217 static __inline u_int32_t ppc_mf ## name (void) \ 218 { \ 219 u_int32_t ret; \ 220 __asm __volatile ("mfspr %0," # n : "=r" (ret)); \ 221 return ret; \ 222 } \ 223 static __inline void ppc_mt ## name (u_int32_t val) \ 224 { \ 225 __asm __volatile ("mtspr "# n ",%0" :: "r" (val)); \ 226 } \ 227 228 FUNC_SPR(0, mq) 229 FUNC_SPR(1, xer) 230 FUNC_SPR(4, rtcu) 231 FUNC_SPR(5, rtcl) 232 FUNC_SPR(8, lr) 233 FUNC_SPR(9, ctr) 234 FUNC_SPR(18, dsisr) 235 FUNC_SPR(19, dar) 236 FUNC_SPR(22, dec) 237 FUNC_SPR(25, sdr1) 238 FUNC_SPR(26, srr0) 239 FUNC_SPR(27, srr1) 240 FUNC_SPR(256, vrsave) 241 FUNC_SPR(272, sprg0) 242 FUNC_SPR(273, sprg1) 243 FUNC_SPR(274, sprg2) 244 FUNC_SPR(275, sprg3) 245 FUNC_SPR(280, asr) 246 FUNC_SPR(282, ear) 247 FUNC_SPR(287, pvr) 248 FUNC_SPR(528, ibat0u) 249 FUNC_SPR(529, ibat0l) 250 FUNC_SPR(530, ibat1u) 251 FUNC_SPR(531, ibat1l) 252 FUNC_SPR(532, ibat2u) 253 FUNC_SPR(533, ibat2l) 254 FUNC_SPR(534, ibat3u) 255 FUNC_SPR(535, ibat3l) 256 FUNC_SPR(536, dbat0u) 257 FUNC_SPR(537, dbat0l) 258 FUNC_SPR(538, dbat1u) 259 FUNC_SPR(539, dbat1l) 260 FUNC_SPR(540, dbat2u) 261 FUNC_SPR(541, dbat2l) 262 FUNC_SPR(542, dbat3u) 263 FUNC_SPR(543, dbat3l) 264 FUNC_SPR(1008, hid0) 265 FUNC_SPR(1009, hid1) 266 FUNC_SPR(1010, iabr) 267 FUNC_SPR(1017, l2cr) 268 FUNC_SPR(1018, l3cr) 269 FUNC_SPR(1013, dabr) 270 FUNC_SPR(1023, pir) 271 272 static __inline u_int32_t 273 ppc_mftbl (void) 274 { 275 int ret; 276 __asm __volatile ("mftb %0" : "=r" (ret)); 277 return ret; 278 } 279 280 static __inline u_int64_t 281 ppc_mftb(void) 282 { 283 u_long scratch; 284 u_int64_t tb; 285 286 __asm __volatile ("1: mftbu %0; mftb %0+1; mftbu %1;" 287 " cmpw 0,%0,%1; bne 1b" : "=r"(tb), "=r"(scratch)); 288 return tb; 289 } 290 291 static __inline u_int32_t 292 ppc_mfmsr (void) 293 { 294 int ret; 295 __asm __volatile ("mfmsr %0" : "=r" (ret)); 296 return ret; 297 } 298 299 static __inline void 300 ppc_mtmsr (u_int32_t val) 301 { 302 __asm __volatile ("mtmsr %0" :: "r" (val)); 303 } 304 305 static __inline void 306 ppc_mtsrin(u_int32_t val, u_int32_t sn_shifted) 307 { 308 __asm __volatile ("mtsrin %0,%1" :: "r"(val), "r"(sn_shifted)); 309 } 310 311 u_int64_t ppc64_mfscomc(void); 312 void ppc_mtscomc(u_int32_t); 313 void ppc64_mtscomc(u_int64_t); 314 u_int64_t ppc64_mfscomd(void); 315 void ppc_mtscomd(u_int32_t); 316 317 #include <machine/psl.h> 318 319 /* 320 * General functions to enable and disable interrupts 321 * without having inlined assembly code in many functions. 322 */ 323 static __inline void 324 ppc_intr_enable(int enable) 325 { 326 u_int32_t msr; 327 if (enable != 0) { 328 msr = ppc_mfmsr(); 329 msr |= PSL_EE; 330 ppc_mtmsr(msr); 331 } 332 } 333 334 static __inline int 335 ppc_intr_disable(void) 336 { 337 u_int32_t emsr, dmsr; 338 emsr = ppc_mfmsr(); 339 dmsr = emsr & ~PSL_EE; 340 ppc_mtmsr(dmsr); 341 return (emsr & PSL_EE); 342 } 343 344 int ppc_cpuspeed(int *); 345 void ppc_check_procid(void); 346 extern int ppc_proc_is_64b; 347 348 /* 349 * PowerPC CPU types 350 */ 351 #define PPC_CPU_MPC601 1 352 #define PPC_CPU_MPC603 3 353 #define PPC_CPU_MPC604 4 354 #define PPC_CPU_MPC603e 6 355 #define PPC_CPU_MPC603ev 7 356 #define PPC_CPU_MPC750 8 357 #define PPC_CPU_MPC604ev 9 358 #define PPC_CPU_MPC7400 12 359 #define PPC_CPU_IBM970FX 0x003c 360 #define PPC_CPU_IBM970MP 0x0044 361 #define PPC_CPU_IBM750FX 0x7000 362 #define PPC_CPU_MPC7410 0x800c 363 #define PPC_CPU_MPC7447A 0x8003 364 #define PPC_CPU_MPC7448 0x8004 365 #define PPC_CPU_MPC7450 0x8000 366 #define PPC_CPU_MPC7455 0x8001 367 #define PPC_CPU_MPC7457 0x8002 368 369 /* 370 * This needs to be included late since it relies on definitions higher 371 * up in this file. 372 */ 373 #if defined(MULTIPROCESSOR) && defined(_KERNEL) 374 #include <sys/mplock.h> 375 #endif 376 377 #endif /* _POWERPC_CPU_H_ */ 378