1 /* $OpenBSD: cpu.h,v 1.39 2008/09/16 04:20:42 drahn Exp $ */ 2 /* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */ 3 4 /* 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 #ifndef _POWERPC_CPU_H_ 35 #define _POWERPC_CPU_H_ 36 37 #include <machine/frame.h> 38 39 #include <sys/device.h> 40 #include <sys/lock.h> 41 #include <sys/sched.h> 42 43 struct cpu_info { 44 struct device *ci_dev; /* our device */ 45 struct schedstate_percpu ci_schedstate; /* scheduler state */ 46 47 struct proc *ci_curproc; 48 49 struct pcb *ci_curpcb; 50 struct pmap *ci_curpm; 51 struct proc *ci_fpuproc; 52 struct proc *ci_vecproc; 53 int ci_cpuid; 54 55 volatile int ci_want_resched; 56 volatile int ci_cpl; 57 volatile int ci_iactive; 58 #define CI_IACTIVE_PROCESSING_SOFT 1 59 #define CI_IACTIVE_PROCESSING_HARD 2 60 volatile int ci_ipending; 61 62 int ci_intrdepth; 63 char *ci_intstk; 64 #define CPUSAVE_LEN 8 65 register_t ci_tempsave[CPUSAVE_LEN]; 66 register_t ci_ddbsave[CPUSAVE_LEN]; 67 #define DISISAVE_LEN 4 68 register_t ci_disisave[DISISAVE_LEN]; 69 70 volatile u_int64_t ci_nexttimerevent; 71 volatile u_int64_t ci_prevtb; 72 volatile u_int64_t ci_lasttb; 73 volatile u_int64_t ci_nextstatevent; 74 int ci_statspending; 75 76 volatile int ci_ddb_paused; 77 #define CI_DDB_RUNNING 0 78 #define CI_DDB_SHOULDSTOP 1 79 #define CI_DDB_STOPPED 2 80 #define CI_DDB_ENTERDDB 3 81 #define CI_DDB_INDDB 4 82 83 u_long ci_randseed; 84 }; 85 86 static __inline struct cpu_info * 87 curcpu(void) 88 { 89 struct cpu_info *ci; 90 91 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 92 return ci; 93 } 94 95 #define curpcb (curcpu()->ci_curpcb) 96 #define curpm (curcpu()->ci_curpm) 97 98 #define CPU_INFO_UNIT(ci) ((ci)->ci_dev->dv_unit) 99 100 #ifdef MULTIPROCESSOR 101 102 #define PPC_MAXPROCS 4 103 104 static __inline int 105 cpu_number(void) 106 { 107 int pir; 108 109 pir = curcpu()->ci_cpuid; 110 return pir; 111 } 112 113 void cpu_boot_secondary_processors(void); 114 115 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 116 #define CPU_INFO_ITERATOR int 117 #define CPU_INFO_FOREACH(cii, ci) \ 118 for (cii = 0, ci = &cpu_info[0]; cii < PPC_MAXPROCS; cii++, ci++) 119 120 #else 121 122 #define PPC_MAXPROCS 1 123 124 #define cpu_number() 0 125 126 #define CPU_IS_PRIMARY(ci) 1 127 #define CPU_INFO_ITERATOR int 128 #define CPU_INFO_FOREACH(cii, ci) \ 129 for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL) 130 131 #endif 132 133 extern struct cpu_info cpu_info[PPC_MAXPROCS]; 134 135 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 136 #define CLKF_PC(frame) ((frame)->srr0) 137 #define CLKF_INTR(frame) ((frame)->depth != 0) 138 139 /* 140 * This is used during profiling to integrate system time. 141 */ 142 #define PROC_PC(p) (trapframe(p)->srr0) 143 144 #define cpu_wait(p) do { /* nothing */ } while (0) 145 146 void delay(unsigned); 147 #define DELAY(n) delay(n) 148 149 #define aston(p) ((p)->p_md.md_astpending = 1) 150 151 /* 152 * Preempt the current process if in interrupt from user mode, 153 * or after the current trap/syscall if in system mode. 154 */ 155 #define need_resched(ci) \ 156 do { \ 157 ci->ci_want_resched = 1; \ 158 if (ci->ci_curproc != NULL) \ 159 aston(ci->ci_curproc); \ 160 } while (0) 161 #define clear_resched(ci) (ci)->ci_want_resched = 0 162 163 #define need_proftick(p) aston(p) 164 165 void signotify(struct proc *); 166 167 extern char *bootpath; 168 169 #ifndef CACHELINESIZE 170 #define CACHELINESIZE 32 /* For now XXX */ 171 #endif 172 173 static __inline void 174 syncicache(void *from, int len) 175 { 176 int l; 177 char *p = from; 178 179 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 180 l = len; 181 182 do { 183 __asm __volatile ("dcbst 0,%0" :: "r"(p)); 184 p += CACHELINESIZE; 185 } while ((l -= CACHELINESIZE) > 0); 186 __asm __volatile ("sync"); 187 p = from; 188 l = len; 189 do { 190 __asm __volatile ("icbi 0,%0" :: "r"(p)); 191 p += CACHELINESIZE; 192 } while ((l -= CACHELINESIZE) > 0); 193 __asm __volatile ("isync"); 194 } 195 196 static __inline void 197 invdcache(void *from, int len) 198 { 199 int l; 200 char *p = from; 201 202 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 203 l = len; 204 205 do { 206 __asm __volatile ("dcbi 0,%0" :: "r"(p)); 207 p += CACHELINESIZE; 208 } while ((l -= CACHELINESIZE) > 0); 209 __asm __volatile ("sync"); 210 } 211 212 #define FUNC_SPR(n, name) \ 213 static __inline u_int32_t ppc_mf ## name (void) \ 214 { \ 215 u_int32_t ret; \ 216 __asm __volatile ("mfspr %0," # n : "=r" (ret)); \ 217 return ret; \ 218 } \ 219 static __inline void ppc_mt ## name (u_int32_t val) \ 220 { \ 221 __asm __volatile ("mtspr "# n ",%0" :: "r" (val)); \ 222 } \ 223 224 FUNC_SPR(0, mq) 225 FUNC_SPR(1, xer) 226 FUNC_SPR(4, rtcu) 227 FUNC_SPR(5, rtcl) 228 FUNC_SPR(8, lr) 229 FUNC_SPR(9, ctr) 230 FUNC_SPR(18, dsisr) 231 FUNC_SPR(19, dar) 232 FUNC_SPR(22, dec) 233 FUNC_SPR(25, sdr1) 234 FUNC_SPR(26, srr0) 235 FUNC_SPR(27, srr1) 236 FUNC_SPR(256, vrsave) 237 FUNC_SPR(272, sprg0) 238 FUNC_SPR(273, sprg1) 239 FUNC_SPR(274, sprg2) 240 FUNC_SPR(275, sprg3) 241 FUNC_SPR(280, asr) 242 FUNC_SPR(282, ear) 243 FUNC_SPR(287, pvr) 244 FUNC_SPR(528, ibat0u) 245 FUNC_SPR(529, ibat0l) 246 FUNC_SPR(530, ibat1u) 247 FUNC_SPR(531, ibat1l) 248 FUNC_SPR(532, ibat2u) 249 FUNC_SPR(533, ibat2l) 250 FUNC_SPR(534, ibat3u) 251 FUNC_SPR(535, ibat3l) 252 FUNC_SPR(536, dbat0u) 253 FUNC_SPR(537, dbat0l) 254 FUNC_SPR(538, dbat1u) 255 FUNC_SPR(539, dbat1l) 256 FUNC_SPR(540, dbat2u) 257 FUNC_SPR(541, dbat2l) 258 FUNC_SPR(542, dbat3u) 259 FUNC_SPR(543, dbat3l) 260 FUNC_SPR(1008, hid0) 261 FUNC_SPR(1009, hid1) 262 FUNC_SPR(1010, iabr) 263 FUNC_SPR(1017, l2cr) 264 FUNC_SPR(1018, l3cr) 265 FUNC_SPR(1013, dabr) 266 FUNC_SPR(1023, pir) 267 268 static __inline u_int32_t 269 ppc_mftbl (void) 270 { 271 int ret; 272 __asm __volatile ("mftb %0" : "=r" (ret)); 273 return ret; 274 } 275 276 static __inline u_int64_t 277 ppc_mftb(void) 278 { 279 u_long scratch; 280 u_int64_t tb; 281 282 __asm __volatile ("1: mftbu %0; mftb %0+1; mftbu %1;" 283 " cmpw 0,%0,%1; bne 1b" : "=r"(tb), "=r"(scratch)); 284 return tb; 285 } 286 287 static __inline u_int32_t 288 ppc_mfmsr (void) 289 { 290 int ret; 291 __asm __volatile ("mfmsr %0" : "=r" (ret)); 292 return ret; 293 } 294 295 static __inline void 296 ppc_mtmsr (u_int32_t val) 297 { 298 __asm __volatile ("mtmsr %0" :: "r" (val)); 299 } 300 301 static __inline void 302 ppc_mtsrin(u_int32_t val, u_int32_t sn_shifted) 303 { 304 __asm __volatile ("mtsrin %0,%1" :: "r"(val), "r"(sn_shifted)); 305 } 306 307 u_int64_t ppc64_mfscomc(void); 308 void ppc_mtscomc(u_int32_t); 309 void ppc64_mtscomc(u_int64_t); 310 u_int64_t ppc64_mfscomd(void); 311 void ppc_mtscomd(u_int32_t); 312 313 #include <machine/psl.h> 314 315 /* 316 * General functions to enable and disable interrupts 317 * without having inlined assembly code in many functions. 318 */ 319 static __inline void 320 ppc_intr_enable(int enable) 321 { 322 u_int32_t msr; 323 if (enable != 0) { 324 msr = ppc_mfmsr(); 325 msr |= PSL_EE; 326 ppc_mtmsr(msr); 327 } 328 } 329 330 static __inline int 331 ppc_intr_disable(void) 332 { 333 u_int32_t emsr, dmsr; 334 emsr = ppc_mfmsr(); 335 dmsr = emsr & ~PSL_EE; 336 ppc_mtmsr(dmsr); 337 return (emsr & PSL_EE); 338 } 339 340 int ppc_cpuspeed(int *); 341 void ppc_check_procid(void); 342 extern int ppc_proc_is_64b; 343 344 /* 345 * PowerPC CPU types 346 */ 347 #define PPC_CPU_MPC601 1 348 #define PPC_CPU_MPC603 3 349 #define PPC_CPU_MPC604 4 350 #define PPC_CPU_MPC603e 6 351 #define PPC_CPU_MPC603ev 7 352 #define PPC_CPU_MPC750 8 353 #define PPC_CPU_MPC604ev 9 354 #define PPC_CPU_MPC7400 12 355 #define PPC_CPU_IBM970FX 0x003c 356 #define PPC_CPU_IBM970MP 0x0044 357 #define PPC_CPU_IBM750FX 0x7000 358 #define PPC_CPU_MPC7410 0x800c 359 #define PPC_CPU_MPC7447A 0x8003 360 #define PPC_CPU_MPC7448 0x8004 361 #define PPC_CPU_MPC7450 0x8000 362 #define PPC_CPU_MPC7455 0x8001 363 #define PPC_CPU_MPC7457 0x8002 364 365 /* 366 * This needs to be included late since it relies on definitions higher 367 * up in this file. 368 */ 369 #if defined(MULTIPROCESSOR) && defined(_KERNEL) 370 #include <sys/mplock.h> 371 #endif 372 373 #endif /* _POWERPC_CPU_H_ */ 374