1 /* $OpenBSD: cpu.h,v 1.53 2014/07/11 10:53:07 uebayasi Exp $ */ 2 /* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */ 3 4 /* 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 #ifndef _POWERPC_CPU_H_ 35 #define _POWERPC_CPU_H_ 36 37 #include <machine/frame.h> 38 39 #include <sys/device.h> 40 #include <sys/lock.h> 41 #include <sys/sched.h> 42 43 struct cpu_info { 44 struct device *ci_dev; /* our device */ 45 struct schedstate_percpu ci_schedstate; /* scheduler state */ 46 47 struct proc *ci_curproc; 48 49 struct pcb *ci_curpcb; 50 struct pmap *ci_curpm; 51 struct proc *ci_fpuproc; 52 struct proc *ci_vecproc; 53 int ci_cpuid; 54 55 volatile int ci_want_resched; 56 volatile int ci_cpl; 57 volatile int ci_iactive; 58 #define CI_IACTIVE_PROCESSING_SOFT 1 59 #define CI_IACTIVE_PROCESSING_HARD 2 60 volatile int ci_ipending; 61 62 int ci_intrdepth; 63 char *ci_intstk; 64 #define CPUSAVE_LEN 8 65 register_t ci_tempsave[CPUSAVE_LEN]; 66 register_t ci_ddbsave[CPUSAVE_LEN]; 67 #define DISISAVE_LEN 4 68 register_t ci_disisave[DISISAVE_LEN]; 69 70 volatile u_int64_t ci_nexttimerevent; 71 volatile u_int64_t ci_prevtb; 72 volatile u_int64_t ci_lasttb; 73 volatile u_int64_t ci_nextstatevent; 74 int ci_statspending; 75 76 volatile int ci_ddb_paused; 77 #define CI_DDB_RUNNING 0 78 #define CI_DDB_SHOULDSTOP 1 79 #define CI_DDB_STOPPED 2 80 #define CI_DDB_ENTERDDB 3 81 #define CI_DDB_INDDB 4 82 83 u_int32_t ci_randseed; 84 85 #ifdef DIAGNOSTIC 86 int ci_mutex_level; 87 #endif 88 #ifdef GPROF 89 struct gmonparam *ci_gmon; 90 #endif 91 }; 92 93 static __inline struct cpu_info * 94 curcpu(void) 95 { 96 struct cpu_info *ci; 97 98 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 99 return ci; 100 } 101 102 #define curpcb (curcpu()->ci_curpcb) 103 #define curpm (curcpu()->ci_curpm) 104 105 #define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0) 106 107 #ifdef MULTIPROCESSOR 108 109 #define PPC_MAXPROCS 4 110 111 static __inline int 112 cpu_number(void) 113 { 114 int pir; 115 116 pir = curcpu()->ci_cpuid; 117 return pir; 118 } 119 120 void cpu_boot_secondary_processors(void); 121 122 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 123 #define CPU_INFO_ITERATOR int 124 #define CPU_INFO_FOREACH(cii, ci) \ 125 for (cii = 0, ci = &cpu_info[0]; cii < ncpus; cii++, ci++) 126 127 void cpu_unidle(struct cpu_info *); 128 129 #else 130 131 #define PPC_MAXPROCS 1 132 133 #define cpu_number() 0 134 135 #define CPU_IS_PRIMARY(ci) 1 136 #define CPU_INFO_ITERATOR int 137 #define CPU_INFO_FOREACH(cii, ci) \ 138 for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL) 139 140 #define cpu_unidle(ci) 141 142 #endif 143 144 #define CPU_BUSY_CYCLE() do {} while (0) 145 146 #define MAXCPUS PPC_MAXPROCS 147 148 extern struct cpu_info cpu_info[PPC_MAXPROCS]; 149 150 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 151 #define CLKF_PC(frame) ((frame)->srr0) 152 #define CLKF_INTR(frame) ((frame)->depth != 0) 153 154 /* 155 * This is used during profiling to integrate system time. 156 */ 157 #define PROC_PC(p) (trapframe(p)->srr0) 158 #define PROC_STACK(p) (trapframe(p)->fixreg[1]) 159 160 void delay(unsigned); 161 #define DELAY(n) delay(n) 162 163 #define aston(p) ((p)->p_md.md_astpending = 1) 164 165 /* 166 * Preempt the current process if in interrupt from user mode, 167 * or after the current trap/syscall if in system mode. 168 */ 169 #define need_resched(ci) \ 170 do { \ 171 ci->ci_want_resched = 1; \ 172 if (ci->ci_curproc != NULL) \ 173 aston(ci->ci_curproc); \ 174 } while (0) 175 #define clear_resched(ci) (ci)->ci_want_resched = 0 176 177 #define need_proftick(p) aston(p) 178 179 void signotify(struct proc *); 180 181 extern char *bootpath; 182 183 #ifndef CACHELINESIZE 184 #define CACHELINESIZE 32 /* For now XXX */ 185 #endif 186 187 static __inline void 188 syncicache(void *from, int len) 189 { 190 int l; 191 char *p = from; 192 193 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 194 l = len; 195 196 do { 197 __asm volatile ("dcbst 0,%0" :: "r"(p)); 198 p += CACHELINESIZE; 199 } while ((l -= CACHELINESIZE) > 0); 200 __asm volatile ("sync"); 201 p = from; 202 l = len; 203 do { 204 __asm volatile ("icbi 0,%0" :: "r"(p)); 205 p += CACHELINESIZE; 206 } while ((l -= CACHELINESIZE) > 0); 207 __asm volatile ("isync"); 208 } 209 210 static __inline void 211 invdcache(void *from, int len) 212 { 213 int l; 214 char *p = from; 215 216 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 217 l = len; 218 219 do { 220 __asm volatile ("dcbi 0,%0" :: "r"(p)); 221 p += CACHELINESIZE; 222 } while ((l -= CACHELINESIZE) > 0); 223 __asm volatile ("sync"); 224 } 225 226 #define FUNC_SPR(n, name) \ 227 static __inline u_int32_t ppc_mf ## name (void) \ 228 { \ 229 u_int32_t ret; \ 230 __asm volatile ("mfspr %0," # n : "=r" (ret)); \ 231 return ret; \ 232 } \ 233 static __inline void ppc_mt ## name (u_int32_t val) \ 234 { \ 235 __asm volatile ("mtspr "# n ",%0" :: "r" (val)); \ 236 } \ 237 238 FUNC_SPR(0, mq) 239 FUNC_SPR(1, xer) 240 FUNC_SPR(4, rtcu) 241 FUNC_SPR(5, rtcl) 242 FUNC_SPR(8, lr) 243 FUNC_SPR(9, ctr) 244 FUNC_SPR(18, dsisr) 245 FUNC_SPR(19, dar) 246 FUNC_SPR(22, dec) 247 FUNC_SPR(25, sdr1) 248 FUNC_SPR(26, srr0) 249 FUNC_SPR(27, srr1) 250 FUNC_SPR(256, vrsave) 251 FUNC_SPR(272, sprg0) 252 FUNC_SPR(273, sprg1) 253 FUNC_SPR(274, sprg2) 254 FUNC_SPR(275, sprg3) 255 FUNC_SPR(280, asr) 256 FUNC_SPR(282, ear) 257 FUNC_SPR(287, pvr) 258 FUNC_SPR(528, ibat0u) 259 FUNC_SPR(529, ibat0l) 260 FUNC_SPR(530, ibat1u) 261 FUNC_SPR(531, ibat1l) 262 FUNC_SPR(532, ibat2u) 263 FUNC_SPR(533, ibat2l) 264 FUNC_SPR(534, ibat3u) 265 FUNC_SPR(535, ibat3l) 266 FUNC_SPR(560, ibat4u) 267 FUNC_SPR(561, ibat4l) 268 FUNC_SPR(562, ibat5u) 269 FUNC_SPR(563, ibat5l) 270 FUNC_SPR(564, ibat6u) 271 FUNC_SPR(565, ibat6l) 272 FUNC_SPR(566, ibat7u) 273 FUNC_SPR(567, ibat7l) 274 FUNC_SPR(536, dbat0u) 275 FUNC_SPR(537, dbat0l) 276 FUNC_SPR(538, dbat1u) 277 FUNC_SPR(539, dbat1l) 278 FUNC_SPR(540, dbat2u) 279 FUNC_SPR(541, dbat2l) 280 FUNC_SPR(542, dbat3u) 281 FUNC_SPR(543, dbat3l) 282 FUNC_SPR(568, dbat4u) 283 FUNC_SPR(569, dbat4l) 284 FUNC_SPR(570, dbat5u) 285 FUNC_SPR(571, dbat5l) 286 FUNC_SPR(572, dbat6u) 287 FUNC_SPR(573, dbat6l) 288 FUNC_SPR(574, dbat7u) 289 FUNC_SPR(575, dbat7l) 290 FUNC_SPR(1008, hid0) 291 FUNC_SPR(1009, hid1) 292 FUNC_SPR(1010, iabr) 293 FUNC_SPR(1017, l2cr) 294 FUNC_SPR(1018, l3cr) 295 FUNC_SPR(1013, dabr) 296 FUNC_SPR(1023, pir) 297 298 static __inline u_int32_t 299 ppc_mftbl (void) 300 { 301 int ret; 302 __asm volatile ("mftb %0" : "=r" (ret)); 303 return ret; 304 } 305 306 static __inline u_int64_t 307 ppc_mftb(void) 308 { 309 u_long scratch; 310 u_int64_t tb; 311 312 __asm volatile ("1: mftbu %0; mftb %0+1; mftbu %1;" 313 " cmpw 0,%0,%1; bne 1b" : "=r"(tb), "=r"(scratch)); 314 return tb; 315 } 316 317 static __inline u_int32_t 318 ppc_mfmsr (void) 319 { 320 int ret; 321 __asm volatile ("mfmsr %0" : "=r" (ret)); 322 return ret; 323 } 324 325 static __inline void 326 ppc_mtmsr (u_int32_t val) 327 { 328 __asm volatile ("mtmsr %0" :: "r" (val)); 329 } 330 331 static __inline void 332 ppc_mtsrin(u_int32_t val, u_int32_t sn_shifted) 333 { 334 __asm volatile ("mtsrin %0,%1" :: "r"(val), "r"(sn_shifted)); 335 } 336 337 u_int64_t ppc64_mfscomc(void); 338 void ppc_mtscomc(u_int32_t); 339 void ppc64_mtscomc(u_int64_t); 340 u_int64_t ppc64_mfscomd(void); 341 void ppc_mtscomd(u_int32_t); 342 343 #include <machine/psl.h> 344 345 /* 346 * General functions to enable and disable interrupts 347 * without having inlined assembly code in many functions. 348 */ 349 static __inline void 350 ppc_intr_enable(int enable) 351 { 352 u_int32_t msr; 353 if (enable != 0) { 354 msr = ppc_mfmsr(); 355 msr |= PSL_EE; 356 ppc_mtmsr(msr); 357 } 358 } 359 360 static __inline int 361 ppc_intr_disable(void) 362 { 363 u_int32_t emsr, dmsr; 364 emsr = ppc_mfmsr(); 365 dmsr = emsr & ~PSL_EE; 366 ppc_mtmsr(dmsr); 367 return (emsr & PSL_EE); 368 } 369 370 int ppc_cpuspeed(int *); 371 void ppc_check_procid(void); 372 extern int ppc_proc_is_64b; 373 374 /* 375 * PowerPC CPU types 376 */ 377 #define PPC_CPU_MPC601 1 378 #define PPC_CPU_MPC603 3 379 #define PPC_CPU_MPC604 4 380 #define PPC_CPU_MPC603e 6 381 #define PPC_CPU_MPC603ev 7 382 #define PPC_CPU_MPC750 8 383 #define PPC_CPU_MPC604ev 9 384 #define PPC_CPU_MPC7400 12 385 #define PPC_CPU_IBM970 0x0039 386 #define PPC_CPU_IBM970FX 0x003c 387 #define PPC_CPU_IBM970MP 0x0044 388 #define PPC_CPU_IBM750FX 0x7000 389 #define PPC_CPU_MPC7410 0x800c 390 #define PPC_CPU_MPC7447A 0x8003 391 #define PPC_CPU_MPC7448 0x8004 392 #define PPC_CPU_MPC7450 0x8000 393 #define PPC_CPU_MPC7455 0x8001 394 #define PPC_CPU_MPC7457 0x8002 395 396 /* 397 * This needs to be included late since it relies on definitions higher 398 * up in this file. 399 */ 400 #if defined(MULTIPROCESSOR) && defined(_KERNEL) 401 #include <sys/mplock.h> 402 #endif 403 404 #endif /* _POWERPC_CPU_H_ */ 405