1 /* $OpenBSD: cpu.h,v 1.65 2019/03/23 05:27:53 visa Exp $ */ 2 /* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */ 3 4 /* 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 #ifndef _POWERPC_CPU_H_ 35 #define _POWERPC_CPU_H_ 36 37 #include <machine/frame.h> 38 39 #include <sys/device.h> 40 #include <sys/sched.h> 41 #include <sys/srp.h> 42 43 struct cpu_info { 44 struct device *ci_dev; /* our device */ 45 struct schedstate_percpu ci_schedstate; /* scheduler state */ 46 47 struct proc *ci_curproc; 48 49 struct pcb *ci_curpcb; 50 struct pmap *ci_curpm; 51 struct proc *ci_fpuproc; 52 struct proc *ci_vecproc; 53 int ci_cpuid; 54 55 volatile int ci_want_resched; 56 volatile int ci_cpl; 57 volatile int ci_ipending; 58 59 volatile int ci_flags; 60 #define CI_FLAGS_SLEEPING 2 61 62 #if defined(MULTIPROCESSOR) 63 struct srp_hazard ci_srp_hazards[SRP_HAZARD_NUM]; 64 #endif 65 66 int ci_intrdepth; 67 char *ci_intstk; 68 #define CPUSAVE_LEN 8 69 register_t ci_tempsave[CPUSAVE_LEN]; 70 register_t ci_ddbsave[CPUSAVE_LEN]; 71 #define DISISAVE_LEN 4 72 register_t ci_disisave[DISISAVE_LEN]; 73 74 volatile u_int64_t ci_nexttimerevent; 75 volatile u_int64_t ci_prevtb; 76 volatile u_int64_t ci_lasttb; 77 volatile u_int64_t ci_nextstatevent; 78 int ci_statspending; 79 80 volatile int ci_ddb_paused; 81 #define CI_DDB_RUNNING 0 82 #define CI_DDB_SHOULDSTOP 1 83 #define CI_DDB_STOPPED 2 84 #define CI_DDB_ENTERDDB 3 85 #define CI_DDB_INDDB 4 86 87 u_int32_t ci_randseed; 88 89 #ifdef DIAGNOSTIC 90 int ci_mutex_level; 91 #endif 92 #ifdef GPROF 93 struct gmonparam *ci_gmon; 94 #endif 95 }; 96 97 static __inline struct cpu_info * 98 curcpu(void) 99 { 100 struct cpu_info *ci; 101 102 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 103 return ci; 104 } 105 106 #define curpcb (curcpu()->ci_curpcb) 107 #define curpm (curcpu()->ci_curpm) 108 109 #define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0) 110 111 #ifdef MULTIPROCESSOR 112 113 #define PPC_MAXPROCS 4 114 115 static __inline int 116 cpu_number(void) 117 { 118 int pir; 119 120 pir = curcpu()->ci_cpuid; 121 return pir; 122 } 123 124 void cpu_boot_secondary_processors(void); 125 126 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 127 #define CPU_INFO_ITERATOR int 128 #define CPU_INFO_FOREACH(cii, ci) \ 129 for (cii = 0, ci = &cpu_info[0]; cii < ncpusfound; cii++, ci++) 130 131 void cpu_unidle(struct cpu_info *); 132 133 #else 134 135 #define PPC_MAXPROCS 1 136 137 #define cpu_number() 0 138 139 #define CPU_IS_PRIMARY(ci) 1 140 #define CPU_INFO_ITERATOR int 141 #define CPU_INFO_FOREACH(cii, ci) \ 142 for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL) 143 144 #define cpu_unidle(ci) 145 146 #endif 147 148 #define CPU_BUSY_CYCLE() do {} while (0) 149 150 #define MAXCPUS PPC_MAXPROCS 151 152 extern struct cpu_info cpu_info[PPC_MAXPROCS]; 153 154 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 155 #define CLKF_PC(frame) ((frame)->srr0) 156 #define CLKF_INTR(frame) ((frame)->depth != 0) 157 158 extern int ppc_cpuidle; 159 extern int ppc_proc_is_64b; 160 extern int ppc_nobat; 161 162 void cpu_bootstrap(void); 163 164 /* 165 * This is used during profiling to integrate system time. 166 */ 167 #define PROC_PC(p) (trapframe(p)->srr0) 168 #define PROC_STACK(p) (trapframe(p)->fixreg[1]) 169 170 void delay(unsigned); 171 #define DELAY(n) delay(n) 172 173 #define aston(p) ((p)->p_md.md_astpending = 1) 174 175 /* 176 * Preempt the current process if in interrupt from user mode, 177 * or after the current trap/syscall if in system mode. 178 */ 179 #define need_resched(ci) \ 180 do { \ 181 ci->ci_want_resched = 1; \ 182 if (ci->ci_curproc != NULL) \ 183 aston(ci->ci_curproc); \ 184 } while (0) 185 #define clear_resched(ci) (ci)->ci_want_resched = 0 186 187 #define need_proftick(p) aston(p) 188 189 void signotify(struct proc *); 190 191 extern char *bootpath; 192 193 #ifndef CACHELINESIZE 194 #define CACHELINESIZE 32 /* For now XXX */ 195 #endif 196 197 static __inline void 198 syncicache(void *from, int len) 199 { 200 int l; 201 char *p = from; 202 203 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 204 l = len; 205 206 do { 207 __asm volatile ("dcbst 0,%0" :: "r"(p)); 208 p += CACHELINESIZE; 209 } while ((l -= CACHELINESIZE) > 0); 210 __asm volatile ("sync"); 211 p = from; 212 l = len; 213 do { 214 __asm volatile ("icbi 0,%0" :: "r"(p)); 215 p += CACHELINESIZE; 216 } while ((l -= CACHELINESIZE) > 0); 217 __asm volatile ("isync"); 218 } 219 220 static __inline void 221 invdcache(void *from, int len) 222 { 223 int l; 224 char *p = from; 225 226 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 227 l = len; 228 229 do { 230 __asm volatile ("dcbi 0,%0" :: "r"(p)); 231 p += CACHELINESIZE; 232 } while ((l -= CACHELINESIZE) > 0); 233 __asm volatile ("sync"); 234 } 235 236 static __inline void 237 flushdcache(void *from, int len) 238 { 239 int l; 240 char *p = from; 241 242 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 243 l = len; 244 245 do { 246 __asm volatile ("dcbf 0,%0" :: "r"(p)); 247 p += CACHELINESIZE; 248 } while ((l -= CACHELINESIZE) > 0); 249 __asm volatile ("sync"); 250 } 251 252 #define FUNC_SPR(n, name) \ 253 static __inline u_int32_t ppc_mf ## name (void) \ 254 { \ 255 u_int32_t ret; \ 256 __asm volatile ("mfspr %0," # n : "=r" (ret)); \ 257 return ret; \ 258 } \ 259 static __inline void ppc_mt ## name (u_int32_t val) \ 260 { \ 261 __asm volatile ("mtspr "# n ",%0" :: "r" (val)); \ 262 } \ 263 264 FUNC_SPR(0, mq) 265 FUNC_SPR(1, xer) 266 FUNC_SPR(4, rtcu) 267 FUNC_SPR(5, rtcl) 268 FUNC_SPR(8, lr) 269 FUNC_SPR(9, ctr) 270 FUNC_SPR(18, dsisr) 271 FUNC_SPR(19, dar) 272 FUNC_SPR(22, dec) 273 FUNC_SPR(25, sdr1) 274 FUNC_SPR(26, srr0) 275 FUNC_SPR(27, srr1) 276 FUNC_SPR(256, vrsave) 277 FUNC_SPR(272, sprg0) 278 FUNC_SPR(273, sprg1) 279 FUNC_SPR(274, sprg2) 280 FUNC_SPR(275, sprg3) 281 FUNC_SPR(280, asr) 282 FUNC_SPR(282, ear) 283 FUNC_SPR(287, pvr) 284 FUNC_SPR(311, hior) 285 FUNC_SPR(528, ibat0u) 286 FUNC_SPR(529, ibat0l) 287 FUNC_SPR(530, ibat1u) 288 FUNC_SPR(531, ibat1l) 289 FUNC_SPR(532, ibat2u) 290 FUNC_SPR(533, ibat2l) 291 FUNC_SPR(534, ibat3u) 292 FUNC_SPR(535, ibat3l) 293 FUNC_SPR(560, ibat4u) 294 FUNC_SPR(561, ibat4l) 295 FUNC_SPR(562, ibat5u) 296 FUNC_SPR(563, ibat5l) 297 FUNC_SPR(564, ibat6u) 298 FUNC_SPR(565, ibat6l) 299 FUNC_SPR(566, ibat7u) 300 FUNC_SPR(567, ibat7l) 301 FUNC_SPR(536, dbat0u) 302 FUNC_SPR(537, dbat0l) 303 FUNC_SPR(538, dbat1u) 304 FUNC_SPR(539, dbat1l) 305 FUNC_SPR(540, dbat2u) 306 FUNC_SPR(541, dbat2l) 307 FUNC_SPR(542, dbat3u) 308 FUNC_SPR(543, dbat3l) 309 FUNC_SPR(568, dbat4u) 310 FUNC_SPR(569, dbat4l) 311 FUNC_SPR(570, dbat5u) 312 FUNC_SPR(571, dbat5l) 313 FUNC_SPR(572, dbat6u) 314 FUNC_SPR(573, dbat6l) 315 FUNC_SPR(574, dbat7u) 316 FUNC_SPR(575, dbat7l) 317 FUNC_SPR(1009, hid1) 318 FUNC_SPR(1010, iabr) 319 FUNC_SPR(1017, l2cr) 320 FUNC_SPR(1018, l3cr) 321 FUNC_SPR(1013, dabr) 322 FUNC_SPR(1023, pir) 323 324 static __inline u_int32_t 325 ppc_mftbl (void) 326 { 327 int ret; 328 __asm volatile ("mftb %0" : "=r" (ret)); 329 return ret; 330 } 331 332 333 static __inline u_int64_t 334 ppc_mftb(void) 335 { 336 u_long scratch; 337 u_int64_t tb; 338 339 __asm volatile ("1: mftbu %0; mftb %0+1; mftbu %1;" 340 " cmpw 0,%0,%1; bne 1b" : "=r"(tb), "=r"(scratch)); 341 return tb; 342 } 343 344 static __inline void 345 ppc_mttb(u_int64_t tb) 346 { 347 __asm volatile ("mttbl %0" :: "r"(0)); 348 __asm volatile ("mttbu %0" :: "r"((u_int32_t)(tb >> 32))); 349 __asm volatile ("mttbl %0" :: "r"((u_int32_t)(tb & 0xffffffff))); 350 } 351 352 static __inline u_int32_t 353 ppc_mfmsr (void) 354 { 355 int ret; 356 __asm volatile ("mfmsr %0" : "=r" (ret)); 357 return ret; 358 } 359 360 static __inline void 361 ppc_mtmsr (u_int32_t val) 362 { 363 __asm volatile ("mtmsr %0" :: "r" (val)); 364 } 365 366 static __inline void 367 ppc_mtsrin(u_int32_t val, u_int32_t sn_shifted) 368 { 369 __asm volatile ("mtsrin %0,%1" :: "r"(val), "r"(sn_shifted)); 370 } 371 372 u_int64_t ppc64_mfscomc(void); 373 void ppc_mtscomc(u_int32_t); 374 void ppc64_mtscomc(u_int64_t); 375 u_int64_t ppc64_mfscomd(void); 376 void ppc_mtscomd(u_int32_t); 377 u_int32_t ppc_mfhid0(void); 378 void ppc_mthid0(u_int32_t); 379 u_int64_t ppc64_mfhid1(void); 380 void ppc64_mthid1(u_int64_t); 381 u_int64_t ppc64_mfhid4(void); 382 void ppc64_mthid4(u_int64_t); 383 u_int64_t ppc64_mfhid5(void); 384 void ppc64_mthid5(u_int64_t); 385 386 #include <machine/psl.h> 387 388 /* 389 * General functions to enable and disable interrupts 390 * without having inlined assembly code in many functions. 391 */ 392 static __inline void 393 ppc_intr_enable(int enable) 394 { 395 u_int32_t msr; 396 if (enable != 0) { 397 msr = ppc_mfmsr(); 398 msr |= PSL_EE; 399 ppc_mtmsr(msr); 400 } 401 } 402 403 static __inline int 404 ppc_intr_disable(void) 405 { 406 u_int32_t emsr, dmsr; 407 emsr = ppc_mfmsr(); 408 dmsr = emsr & ~PSL_EE; 409 ppc_mtmsr(dmsr); 410 return (emsr & PSL_EE); 411 } 412 413 static __inline u_long 414 intr_disable(void) 415 { 416 return ppc_intr_disable(); 417 } 418 419 static __inline void 420 intr_restore(u_long s) 421 { 422 ppc_intr_enable(s); 423 } 424 425 int ppc_cpuspeed(int *); 426 427 /* 428 * PowerPC CPU types 429 */ 430 #define PPC_CPU_MPC601 1 431 #define PPC_CPU_MPC603 3 432 #define PPC_CPU_MPC604 4 433 #define PPC_CPU_MPC603e 6 434 #define PPC_CPU_MPC603ev 7 435 #define PPC_CPU_MPC750 8 436 #define PPC_CPU_MPC604ev 9 437 #define PPC_CPU_MPC7400 12 438 #define PPC_CPU_IBM970 0x0039 439 #define PPC_CPU_IBM970FX 0x003c 440 #define PPC_CPU_IBM970MP 0x0044 441 #define PPC_CPU_IBM750FX 0x7000 442 #define PPC_CPU_MPC7410 0x800c 443 #define PPC_CPU_MPC7447A 0x8003 444 #define PPC_CPU_MPC7448 0x8004 445 #define PPC_CPU_MPC7450 0x8000 446 #define PPC_CPU_MPC7455 0x8001 447 #define PPC_CPU_MPC7457 0x8002 448 #define PPC_CPU_MPC83xx 0x8083 449 450 /* 451 * This needs to be included late since it relies on definitions higher 452 * up in this file. 453 */ 454 #if defined(MULTIPROCESSOR) && defined(_KERNEL) 455 #include <sys/mplock.h> 456 #endif 457 458 #endif /* _POWERPC_CPU_H_ */ 459