1 /* $OpenBSD: cpu.h,v 1.74 2022/11/29 00:58:05 cheloha Exp $ */ 2 /* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */ 3 4 /* 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 #ifndef _POWERPC_CPU_H_ 35 #define _POWERPC_CPU_H_ 36 37 #include <machine/frame.h> 38 39 #include <sys/clockintr.h> 40 #include <sys/device.h> 41 #include <sys/sched.h> 42 #include <sys/srp.h> 43 44 struct cpu_info { 45 struct device *ci_dev; /* our device */ 46 struct schedstate_percpu ci_schedstate; /* scheduler state */ 47 48 struct proc *ci_curproc; 49 50 struct pcb *ci_curpcb; 51 struct pmap *ci_curpm; 52 struct proc *ci_fpuproc; 53 struct proc *ci_vecproc; 54 int ci_cpuid; 55 56 volatile int ci_want_resched; 57 volatile int ci_cpl; 58 volatile int ci_ipending; 59 volatile int ci_dec_deferred; 60 61 volatile int ci_flags; 62 #define CI_FLAGS_SLEEPING 2 63 64 #if defined(MULTIPROCESSOR) 65 struct srp_hazard ci_srp_hazards[SRP_HAZARD_NUM]; 66 #endif 67 68 int ci_intrdepth; 69 char *ci_intstk; 70 #define CPUSAVE_LEN 8 71 register_t ci_tempsave[CPUSAVE_LEN]; 72 register_t ci_ddbsave[CPUSAVE_LEN]; 73 #define DISISAVE_LEN 4 74 register_t ci_disisave[DISISAVE_LEN]; 75 76 struct clockintr_queue ci_queue; 77 78 volatile int ci_ddb_paused; 79 #define CI_DDB_RUNNING 0 80 #define CI_DDB_SHOULDSTOP 1 81 #define CI_DDB_STOPPED 2 82 #define CI_DDB_ENTERDDB 3 83 #define CI_DDB_INDDB 4 84 85 u_int32_t ci_randseed; 86 87 #ifdef DIAGNOSTIC 88 int ci_mutex_level; 89 #endif 90 #ifdef GPROF 91 struct gmonparam *ci_gmon; 92 #endif 93 char ci_panicbuf[512]; 94 }; 95 96 static __inline struct cpu_info * 97 curcpu(void) 98 { 99 struct cpu_info *ci; 100 101 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 102 return ci; 103 } 104 105 #define curpcb (curcpu()->ci_curpcb) 106 #define curpm (curcpu()->ci_curpm) 107 108 #define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0) 109 110 #ifdef MULTIPROCESSOR 111 112 #define PPC_MAXPROCS 4 113 114 static __inline int 115 cpu_number(void) 116 { 117 int pir; 118 119 pir = curcpu()->ci_cpuid; 120 return pir; 121 } 122 123 void cpu_boot_secondary_processors(void); 124 125 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 126 #define CPU_IS_RUNNING(ci) 1 127 #define CPU_INFO_ITERATOR int 128 #define CPU_INFO_FOREACH(cii, ci) \ 129 for (cii = 0, ci = &cpu_info[0]; cii < ncpusfound; cii++, ci++) 130 131 void cpu_unidle(struct cpu_info *); 132 133 #else 134 135 #define PPC_MAXPROCS 1 136 137 #define cpu_number() 0 138 139 #define CPU_IS_PRIMARY(ci) 1 140 #define CPU_IS_RUNNING(ci) 1 141 #define CPU_INFO_ITERATOR int 142 #define CPU_INFO_FOREACH(cii, ci) \ 143 for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL) 144 145 #define cpu_unidle(ci) 146 147 #endif 148 149 #define CPU_BUSY_CYCLE() do {} while (0) 150 151 #define MAXCPUS PPC_MAXPROCS 152 153 extern struct cpu_info cpu_info[PPC_MAXPROCS]; 154 155 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 156 #define CLKF_PC(frame) ((frame)->srr0) 157 #define CLKF_INTR(frame) ((frame)->depth != 0) 158 159 extern int ppc_cpuidle; 160 extern int ppc_proc_is_64b; 161 extern int ppc_nobat; 162 163 void cpu_bootstrap(void); 164 165 static inline unsigned int 166 cpu_rnd_messybits(void) 167 { 168 unsigned int hi, lo; 169 170 __asm volatile("mftbu %0; mftb %1" : "=r" (hi), "=r" (lo)); 171 172 return (hi ^ lo); 173 } 174 175 /* 176 * This is used during profiling to integrate system time. 177 */ 178 #define PROC_PC(p) (trapframe(p)->srr0) 179 #define PROC_STACK(p) (trapframe(p)->fixreg[1]) 180 181 void delay(unsigned); 182 #define DELAY(n) delay(n) 183 184 #define aston(p) ((p)->p_md.md_astpending = 1) 185 186 /* 187 * Preempt the current process if in interrupt from user mode, 188 * or after the current trap/syscall if in system mode. 189 */ 190 #define need_resched(ci) \ 191 do { \ 192 ci->ci_want_resched = 1; \ 193 if (ci->ci_curproc != NULL) \ 194 aston(ci->ci_curproc); \ 195 } while (0) 196 #define clear_resched(ci) (ci)->ci_want_resched = 0 197 198 #define need_proftick(p) aston(p) 199 200 void signotify(struct proc *); 201 202 extern char *bootpath; 203 204 #ifndef CACHELINESIZE 205 #define CACHELINESIZE 32 /* For now XXX */ 206 #endif 207 208 static __inline void 209 syncicache(void *from, size_t len) 210 { 211 size_t by, i; 212 213 by = CACHELINESIZE; 214 i = 0; 215 do { 216 __asm volatile ("dcbst %0,%1" :: "r"(from), "r"(i)); 217 i += by; 218 } while (i < len); 219 __asm volatile ("sync"); 220 i = 0; 221 do { 222 __asm volatile ("icbi %0,%1" :: "r"(from), "r"(i)); 223 i += by; 224 } while (i < len); 225 __asm volatile ("sync; isync"); 226 } 227 228 static __inline void 229 invdcache(void *from, int len) 230 { 231 int l; 232 char *p = from; 233 234 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 235 l = len; 236 237 do { 238 __asm volatile ("dcbi 0,%0" :: "r"(p)); 239 p += CACHELINESIZE; 240 } while ((l -= CACHELINESIZE) > 0); 241 __asm volatile ("sync"); 242 } 243 244 static __inline void 245 flushdcache(void *from, int len) 246 { 247 int l; 248 char *p = from; 249 250 len = len + (((u_int32_t) from) & (CACHELINESIZE - 1)); 251 l = len; 252 253 do { 254 __asm volatile ("dcbf 0,%0" :: "r"(p)); 255 p += CACHELINESIZE; 256 } while ((l -= CACHELINESIZE) > 0); 257 __asm volatile ("sync"); 258 } 259 260 #define FUNC_SPR(n, name) \ 261 static __inline u_int32_t ppc_mf ## name (void) \ 262 { \ 263 u_int32_t ret; \ 264 __asm volatile ("mfspr %0," # n : "=r" (ret)); \ 265 return ret; \ 266 } \ 267 static __inline void ppc_mt ## name (u_int32_t val) \ 268 { \ 269 __asm volatile ("mtspr "# n ",%0" :: "r" (val)); \ 270 } \ 271 272 FUNC_SPR(0, mq) 273 FUNC_SPR(1, xer) 274 FUNC_SPR(4, rtcu) 275 FUNC_SPR(5, rtcl) 276 FUNC_SPR(8, lr) 277 FUNC_SPR(9, ctr) 278 FUNC_SPR(18, dsisr) 279 FUNC_SPR(19, dar) 280 FUNC_SPR(22, dec) 281 FUNC_SPR(25, sdr1) 282 FUNC_SPR(26, srr0) 283 FUNC_SPR(27, srr1) 284 FUNC_SPR(256, vrsave) 285 FUNC_SPR(272, sprg0) 286 FUNC_SPR(273, sprg1) 287 FUNC_SPR(274, sprg2) 288 FUNC_SPR(275, sprg3) 289 FUNC_SPR(280, asr) 290 FUNC_SPR(282, ear) 291 FUNC_SPR(287, pvr) 292 FUNC_SPR(311, hior) 293 FUNC_SPR(528, ibat0u) 294 FUNC_SPR(529, ibat0l) 295 FUNC_SPR(530, ibat1u) 296 FUNC_SPR(531, ibat1l) 297 FUNC_SPR(532, ibat2u) 298 FUNC_SPR(533, ibat2l) 299 FUNC_SPR(534, ibat3u) 300 FUNC_SPR(535, ibat3l) 301 FUNC_SPR(560, ibat4u) 302 FUNC_SPR(561, ibat4l) 303 FUNC_SPR(562, ibat5u) 304 FUNC_SPR(563, ibat5l) 305 FUNC_SPR(564, ibat6u) 306 FUNC_SPR(565, ibat6l) 307 FUNC_SPR(566, ibat7u) 308 FUNC_SPR(567, ibat7l) 309 FUNC_SPR(536, dbat0u) 310 FUNC_SPR(537, dbat0l) 311 FUNC_SPR(538, dbat1u) 312 FUNC_SPR(539, dbat1l) 313 FUNC_SPR(540, dbat2u) 314 FUNC_SPR(541, dbat2l) 315 FUNC_SPR(542, dbat3u) 316 FUNC_SPR(543, dbat3l) 317 FUNC_SPR(568, dbat4u) 318 FUNC_SPR(569, dbat4l) 319 FUNC_SPR(570, dbat5u) 320 FUNC_SPR(571, dbat5l) 321 FUNC_SPR(572, dbat6u) 322 FUNC_SPR(573, dbat6l) 323 FUNC_SPR(574, dbat7u) 324 FUNC_SPR(575, dbat7l) 325 FUNC_SPR(1009, hid1) 326 FUNC_SPR(1010, iabr) 327 FUNC_SPR(1017, l2cr) 328 FUNC_SPR(1018, l3cr) 329 FUNC_SPR(1013, dabr) 330 FUNC_SPR(1023, pir) 331 332 static __inline u_int32_t 333 ppc_mftbl (void) 334 { 335 int ret; 336 __asm volatile ("mftb %0" : "=r" (ret)); 337 return ret; 338 } 339 340 341 static __inline u_int64_t 342 ppc_mftb(void) 343 { 344 u_long scratch; 345 u_int64_t tb; 346 347 __asm volatile ("1: mftbu %0; mftb %L0; mftbu %1;" 348 " cmpw 0,%0,%1; bne 1b" : "=r"(tb), "=r"(scratch)); 349 return tb; 350 } 351 352 static __inline void 353 ppc_mttb(u_int64_t tb) 354 { 355 __asm volatile ("mttbl %0" :: "r"(0)); 356 __asm volatile ("mttbu %0" :: "r"((u_int32_t)(tb >> 32))); 357 __asm volatile ("mttbl %0" :: "r"((u_int32_t)(tb & 0xffffffff))); 358 } 359 360 static __inline u_int32_t 361 ppc_mfmsr (void) 362 { 363 int ret; 364 __asm volatile ("mfmsr %0" : "=r" (ret)); 365 return ret; 366 } 367 368 static __inline void 369 ppc_mtmsr (u_int32_t val) 370 { 371 __asm volatile ("mtmsr %0" :: "r" (val)); 372 } 373 374 static __inline void 375 ppc_mtsrin(u_int32_t val, u_int32_t sn_shifted) 376 { 377 __asm volatile ("mtsrin %0,%1" :: "r"(val), "r"(sn_shifted)); 378 } 379 380 u_int64_t ppc64_mfscomc(void); 381 void ppc_mtscomc(u_int32_t); 382 void ppc64_mtscomc(u_int64_t); 383 u_int64_t ppc64_mfscomd(void); 384 void ppc_mtscomd(u_int32_t); 385 u_int32_t ppc_mfhid0(void); 386 void ppc_mthid0(u_int32_t); 387 u_int64_t ppc64_mfhid1(void); 388 void ppc64_mthid1(u_int64_t); 389 u_int64_t ppc64_mfhid4(void); 390 void ppc64_mthid4(u_int64_t); 391 u_int64_t ppc64_mfhid5(void); 392 void ppc64_mthid5(u_int64_t); 393 394 #include <machine/psl.h> 395 396 /* 397 * General functions to enable and disable interrupts 398 * without having inlined assembly code in many functions. 399 */ 400 static __inline void 401 ppc_intr_enable(int enable) 402 { 403 u_int32_t msr; 404 if (enable != 0) { 405 msr = ppc_mfmsr(); 406 msr |= PSL_EE; 407 ppc_mtmsr(msr); 408 } 409 } 410 411 static __inline int 412 ppc_intr_disable(void) 413 { 414 u_int32_t emsr, dmsr; 415 emsr = ppc_mfmsr(); 416 dmsr = emsr & ~PSL_EE; 417 ppc_mtmsr(dmsr); 418 return (emsr & PSL_EE); 419 } 420 421 static inline void 422 intr_enable(void) 423 { 424 ppc_mtmsr(ppc_mfmsr() | PSL_EE); 425 } 426 427 static __inline u_long 428 intr_disable(void) 429 { 430 return ppc_intr_disable(); 431 } 432 433 static __inline void 434 intr_restore(u_long s) 435 { 436 ppc_intr_enable(s); 437 } 438 439 int ppc_cpuspeed(int *); 440 441 /* 442 * PowerPC CPU types 443 */ 444 #define PPC_CPU_MPC601 1 445 #define PPC_CPU_MPC603 3 446 #define PPC_CPU_MPC604 4 447 #define PPC_CPU_MPC603e 6 448 #define PPC_CPU_MPC603ev 7 449 #define PPC_CPU_MPC750 8 450 #define PPC_CPU_MPC604ev 9 451 #define PPC_CPU_MPC7400 12 452 #define PPC_CPU_IBM970 0x0039 453 #define PPC_CPU_IBM970FX 0x003c 454 #define PPC_CPU_IBM970MP 0x0044 455 #define PPC_CPU_IBM750FX 0x7000 456 #define PPC_CPU_MPC7410 0x800c 457 #define PPC_CPU_MPC7447A 0x8003 458 #define PPC_CPU_MPC7448 0x8004 459 #define PPC_CPU_MPC7450 0x8000 460 #define PPC_CPU_MPC7455 0x8001 461 #define PPC_CPU_MPC7457 0x8002 462 #define PPC_CPU_MPC83xx 0x8083 463 464 /* 465 * This needs to be included late since it relies on definitions higher 466 * up in this file. 467 */ 468 #if defined(MULTIPROCESSOR) && defined(_KERNEL) 469 #include <sys/mplock.h> 470 #endif 471 472 #endif /* _POWERPC_CPU_H_ */ 473