1 /* $OpenBSD: intr.h,v 1.3 2013/05/17 19:38:52 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _MACHINE_INTR_H_ 30 #define _MACHINE_INTR_H_ 31 32 /* 33 * The interrupt level ipl is a logical level; per-platform interrupt 34 * code will turn it into the appropriate hardware interrupt masks 35 * values. 36 * 37 * Interrupt sources on the CPU are kept enabled regardless of the 38 * current ipl value; individual hardware sources interrupting while 39 * logically masked are masked on the fly, remembered as pending, and 40 * unmasked at the first splx() opportunity. 41 * 42 * An exception to this rule is the clock interrupt. Clock interrupts 43 * are always allowed to happen, but will (of course!) not be serviced 44 * if logically masked. The reason for this is that clocks usually sit on 45 * INT5 and cannot be easily masked if external hardware masking is used. 46 */ 47 48 /* Interrupt priority `levels'; not mutually exclusive. */ 49 #define IPL_NONE 0 /* nothing */ 50 #define IPL_SOFTINT 1 /* soft interrupts */ 51 #define IPL_BIO 2 /* block I/O */ 52 #define IPL_AUDIO IPL_BIO 53 #define IPL_NET 3 /* network */ 54 #define IPL_TTY 4 /* terminal */ 55 #define IPL_VM 5 /* memory allocation */ 56 #define IPL_CLOCK 6 /* clock */ 57 #define IPL_SCHED IPL_CLOCK 58 #define IPL_HIGH 7 /* everything */ 59 #define IPL_IPI 8 /* interprocessor interrupt */ 60 #define NIPLS 9 /* Number of levels */ 61 62 /* Interrupt priority 'flags'. */ 63 #define IPL_MPSAFE 0 /* no "mpsafe" interrupts */ 64 65 /* Interrupt sharing types. */ 66 #define IST_NONE 0 /* none */ 67 #define IST_PULSE 1 /* pulsed */ 68 #define IST_EDGE 2 /* edge-triggered */ 69 #define IST_LEVEL 3 /* level-triggered */ 70 71 #define SINTBIT(q) (q) 72 #define SINTMASK(q) (1 << SINTBIT(q)) 73 74 /* Soft interrupt masks. */ 75 76 #define IPL_SOFT 0 77 #define IPL_SOFTCLOCK 1 78 #define IPL_SOFTNET 2 79 #define IPL_SOFTTTY 3 80 81 #define SI_SOFT 0 /* for IPL_SOFT */ 82 #define SI_SOFTCLOCK 1 /* for IPL_SOFTCLOCK */ 83 #define SI_SOFTNET 2 /* for IPL_SOFTNET */ 84 #define SI_SOFTTTY 3 /* for IPL_SOFTTTY */ 85 86 #define SI_NQUEUES 4 87 88 #ifndef _LOCORE 89 90 #include <machine/mutex.h> 91 #include <sys/queue.h> 92 93 struct soft_intrhand { 94 TAILQ_ENTRY(soft_intrhand) sih_list; 95 void (*sih_func)(void *); 96 void *sih_arg; 97 struct soft_intrq *sih_siq; 98 int sih_pending; 99 }; 100 101 struct soft_intrq { 102 TAILQ_HEAD(, soft_intrhand) siq_list; 103 int siq_si; 104 struct mutex siq_mtx; 105 }; 106 107 void softintr_disestablish(void *); 108 void softintr_dispatch(int); 109 void *softintr_establish(int, void (*)(void *), void *); 110 void softintr_init(void); 111 void softintr_schedule(void *); 112 113 /* XXX For legacy software interrupts. */ 114 extern struct soft_intrhand *softnet_intrhand; 115 116 #define setsoftnet() softintr_schedule(softnet_intrhand) 117 118 #define splsoft() splraise(IPL_SOFTINT) 119 #define splbio() splraise(IPL_BIO) 120 #define splnet() splraise(IPL_NET) 121 #define spltty() splraise(IPL_TTY) 122 #define splaudio() splraise(IPL_AUDIO) 123 #define splvm() splraise(IPL_VM) 124 #define splclock() splraise(IPL_CLOCK) 125 #define splsched() splraise(IPL_SCHED) 126 #define splhigh() splraise(IPL_HIGH) 127 128 #define splsoftclock() splsoft() 129 #define splsoftnet() splsoft() 130 #define splstatclock() splhigh() 131 132 #define spllock() splhigh() 133 #define spl0() spllower(0) 134 135 void splinit(void); 136 137 #define splassert(X) 138 #define splsoftassert(X) 139 140 /* Inlines */ 141 static __inline void register_splx_handler(void (*)(int)); 142 143 typedef void (int_f)(int); 144 extern int_f *splx_hand; 145 146 static __inline void 147 register_splx_handler(void(*handler)(int)) 148 { 149 splx_hand = handler; 150 } 151 152 int splraise(int); 153 void splx(int); 154 int spllower(int); 155 156 /* 157 * Interrupt control struct used by interrupt dispatchers 158 * to hold interrupt handler info. 159 */ 160 161 #include <sys/evcount.h> 162 163 struct intrhand { 164 struct intrhand *ih_next; 165 int (*ih_fun)(void *); 166 void *ih_arg; 167 int ih_level; 168 int ih_irq; 169 struct evcount ih_count; 170 int ih_flags; 171 #define IH_ALLOCATED 0x01 172 }; 173 174 /* 175 * Low level interrupt dispatcher registration data. 176 */ 177 178 /* Schedule priorities for base interrupts (CPU) */ 179 #define INTPRI_IPI 0 180 #define INTPRI_CLOCK 1 181 /* other values are system-specific */ 182 183 #define NLOWINT 16 /* Number of low level registrations possible */ 184 185 extern uint32_t idle_mask; 186 187 struct trap_frame; 188 void set_intr(int, uint32_t, uint32_t(*)(uint32_t, struct trap_frame *)); 189 190 uint32_t updateimask(uint32_t); 191 void dosoftint(void); 192 193 #ifdef MULTIPROCESSOR 194 #define ENABLEIPI() updateimask(~CR_INT_1) /* enable IPI interrupt level */ 195 #endif 196 void octeon_intr_init(void); 197 void octeon_setintrmask(int); 198 void *octeon_intr_establish(int, int, int (*)(void *), 199 void *, const char *); 200 void octeon_intr_disestablish(void *); 201 void octeon_intr_init(void); 202 203 #endif /* _LOCORE */ 204 205 #endif /* _MACHINE_INTR_H_ */ 206