1 /* $OpenBSD: cn30xxsmi.c,v 1.3 2014/08/11 18:08:17 miod Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/mbuf.h> 33 34 #include <machine/octeonvar.h> 35 36 #include <octeon/dev/cn30xxfpavar.h> 37 #include <octeon/dev/cn30xxpipreg.h> 38 #include <octeon/dev/cn30xxsmireg.h> 39 #include <octeon/dev/cn30xxsmivar.h> 40 41 void cn30xxsmi_enable(struct cn30xxsmi_softc *); 42 43 /* XXX */ 44 void 45 cn30xxsmi_init(struct cn30xxsmi_attach_args *aa, 46 struct cn30xxsmi_softc **rsc) 47 { 48 struct cn30xxsmi_softc *sc; 49 int status; 50 51 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 52 if (sc == NULL) 53 panic("can't allocate memory: %s", __func__); 54 55 sc->sc_port = aa->aa_port; 56 sc->sc_regt = aa->aa_regt; 57 58 status = bus_space_map(sc->sc_regt, SMI_BASE, SMI_SIZE, 0, 59 &sc->sc_regh); 60 if (status != 0) 61 panic("can't map %s space", "smi register"); 62 63 cn30xxsmi_enable(sc); 64 65 *rsc = sc; 66 } 67 68 #define _SMI_RD8(sc, off) \ 69 bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off)) 70 #define _SMI_WR8(sc, off, v) \ 71 bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v)) 72 73 int 74 cn30xxsmi_read(struct cn30xxsmi_softc *sc, int phy_addr, int reg) 75 { 76 uint64_t smi_rd; 77 int timo; 78 79 _SMI_WR8(sc, SMI_CMD_OFFSET, SMI_CMD_PHY_OP | 80 (phy_addr << SMI_CMD_PHY_ADR_SHIFT) | 81 (reg << SMI_CMD_REG_ADR_SHIFT)); 82 83 timo = 10000; 84 smi_rd = _SMI_RD8(sc, SMI_RD_DAT_OFFSET); 85 while (ISSET(smi_rd, SMI_RD_DAT_PENDING)) { 86 if (timo-- == 0) 87 break; 88 delay(10); 89 smi_rd = _SMI_RD8(sc, SMI_RD_DAT_OFFSET); 90 } 91 if (ISSET(smi_rd, SMI_RD_DAT_PENDING)) { 92 return -1; 93 } 94 95 return ISSET(smi_rd, SMI_RD_DAT_VAL) ? (smi_rd & SMI_RD_DAT_DAT) : 0; 96 } 97 98 void 99 cn30xxsmi_write(struct cn30xxsmi_softc *sc, int phy_addr, int reg, int value) 100 { 101 uint64_t smi_wr; 102 int timo; 103 104 smi_wr = 0; 105 SET(smi_wr, value); 106 _SMI_WR8(sc, SMI_WR_DAT_OFFSET, smi_wr); 107 108 _SMI_WR8(sc, SMI_CMD_OFFSET, (phy_addr << SMI_CMD_PHY_ADR_SHIFT) | 109 (reg << SMI_CMD_REG_ADR_SHIFT)); 110 111 timo = 10000; 112 smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET); 113 while (ISSET(smi_wr, SMI_WR_DAT_PENDING)) { 114 if (timo-- == 0) 115 break; 116 delay(10); 117 smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET); 118 } 119 if (ISSET(smi_wr, SMI_WR_DAT_PENDING)) { 120 /* XXX log */ 121 printf("ERROR: cnmac_mii_writereg(0x%x, 0x%x, 0x%x) timed out.\n", 122 phy_addr, reg, value); 123 } 124 } 125 126 void 127 cn30xxsmi_enable(struct cn30xxsmi_softc *sc) 128 { 129 _SMI_WR8(sc, SMI_EN_OFFSET, SMI_EN_EN); 130 } 131 132 void 133 cn30xxsmi_set_clock(struct cn30xxsmi_softc *sc, uint64_t clock) 134 { 135 _SMI_WR8(sc, SMI_CLK_OFFSET, clock); 136 } 137 138