1 /* $OpenBSD: cn30xxpko.c,v 1.5 2016/05/24 14:06:39 visa Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 33 #include <machine/octeonvar.h> 34 35 #include <octeon/dev/cn30xxfaureg.h> 36 #include <octeon/dev/cn30xxfpavar.h> 37 #include <octeon/dev/cn30xxpkoreg.h> 38 #include <octeon/dev/cn30xxpkovar.h> 39 40 static inline void cn30xxpko_op_store(uint64_t, uint64_t); 41 42 #ifdef OCTEON_ETH_DEBUG 43 void cn30xxpko_intr_rml(void *); 44 #endif 45 46 #define _PKO_RD8(sc, off) \ 47 bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off)) 48 #define _PKO_WR8(sc, off, v) \ 49 bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v)) 50 51 #ifdef OCTEON_ETH_DEBUG 52 struct cn30xxpko_softc *__cn30xxpko_softc; 53 #endif 54 55 /* ----- gloal functions */ 56 57 /* XXX */ 58 void 59 cn30xxpko_init(struct cn30xxpko_attach_args *aa, 60 struct cn30xxpko_softc **rsc) 61 { 62 struct cn30xxpko_softc *sc; 63 int status; 64 65 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 66 if (sc == NULL) 67 panic("can't allocate memory: %s", __func__); 68 69 sc->sc_port = aa->aa_port; 70 sc->sc_regt = aa->aa_regt; 71 sc->sc_cmdptr = aa->aa_cmdptr; 72 sc->sc_cmd_buf_pool = aa->aa_cmd_buf_pool; 73 sc->sc_cmd_buf_size = aa->aa_cmd_buf_size; 74 75 status = bus_space_map(sc->sc_regt, PKO_BASE, PKO_SIZE, 0, 76 &sc->sc_regh); 77 if (status != 0) 78 panic("can't map %s space", "pko register"); 79 80 *rsc = sc; 81 82 #ifdef OCTEON_ETH_DEBUG 83 __cn30xxpko_softc = sc; 84 #endif 85 } 86 87 int 88 cn30xxpko_enable(struct cn30xxpko_softc *sc) 89 { 90 uint64_t reg_flags; 91 92 reg_flags = _PKO_RD8(sc, PKO_REG_FLAGS_OFFSET); 93 /* PKO_REG_FLAGS_RESET=0 */ 94 /* PKO_REG_FLAGS_STORE_BE=0 */ 95 SET(reg_flags, PKO_REG_FLAGS_ENA_DWB); 96 SET(reg_flags, PKO_REG_FLAGS_ENA_PKO); 97 /* XXX */ 98 mips_sync(); 99 _PKO_WR8(sc, PKO_REG_FLAGS_OFFSET, reg_flags); 100 101 return 0; 102 } 103 104 #if 0 105 void 106 cn30xxpko_reset(cn30xxpko_softc *sc) 107 { 108 uint64_t reg_flags; 109 110 reg_flags = _PKO_RD8(sc, PKO_REG_FLAGS_OFFSET); 111 SET(reg_flags, PKO_REG_FLAGS_RESET); 112 _PKO_WR8(sc, PKO_REG_FLAGS_OFFSET, reg_flags); 113 } 114 #endif 115 116 void 117 cn30xxpko_config(struct cn30xxpko_softc *sc) 118 { 119 uint64_t reg_cmd_buf = 0; 120 121 SET(reg_cmd_buf, (sc->sc_cmd_buf_pool << 20) & PKO_REG_CMD_BUF_POOL); 122 SET(reg_cmd_buf, sc->sc_cmd_buf_size & PKO_REG_CMD_BUF_SIZE); 123 _PKO_WR8(sc, PKO_REG_CMD_BUF_OFFSET, reg_cmd_buf); 124 125 #ifdef OCTEON_ETH_DEBUG 126 cn30xxpko_int_enable(sc, 1); 127 #endif 128 } 129 130 int 131 cn30xxpko_port_enable(struct cn30xxpko_softc *sc, int enable) 132 { 133 uint64_t reg_read_idx; 134 uint64_t mem_queue_qos; 135 136 reg_read_idx = 0; 137 SET(reg_read_idx, sc->sc_port & PKO_REG_READ_IDX_IDX); 138 139 /* XXX assume one queue maped one port */ 140 /* Enable packet output by enabling all queues for this port */ 141 mem_queue_qos = 0; 142 SET(mem_queue_qos, ((uint64_t)sc->sc_port << 7) & PKO_MEM_QUEUE_QOS_PID); 143 SET(mem_queue_qos, sc->sc_port & PKO_MEM_QUEUE_QOS_QID); 144 SET(mem_queue_qos, ((enable ? 0xffULL : 0x00ULL) << 53) & 145 PKO_MEM_QUEUE_QOS_QOS_MASK); 146 147 _PKO_WR8(sc, PKO_REG_READ_IDX_OFFSET, reg_read_idx); 148 _PKO_WR8(sc, PKO_MEM_QUEUE_QOS_OFFSET, mem_queue_qos); 149 150 return 0; 151 } 152 153 int pko_queue_map_init[32]; 154 155 int 156 cn30xxpko_port_config(struct cn30xxpko_softc *sc) 157 { 158 paddr_t buf_ptr = 0; 159 uint64_t mem_queue_ptrs; 160 161 KASSERT(sc->sc_port < 32); 162 163 buf_ptr = cn30xxfpa_load(OCTEON_POOL_NO_CMD); 164 if (buf_ptr == 0) 165 return 1; 166 167 KASSERT(buf_ptr != 0); 168 169 /* assume one queue maped one port */ 170 mem_queue_ptrs = 0; 171 SET(mem_queue_ptrs, PKO_MEM_QUEUE_PTRS_TAIL); 172 SET(mem_queue_ptrs, ((uint64_t)0 << 13) & PKO_MEM_QUEUE_PTRS_IDX); 173 SET(mem_queue_ptrs, ((uint64_t)sc->sc_port << 7) & PKO_MEM_QUEUE_PTRS_PID); 174 SET(mem_queue_ptrs, sc->sc_port & PKO_MEM_QUEUE_PTRS_QID); 175 SET(mem_queue_ptrs, ((uint64_t)0xff << 53) & PKO_MEM_QUEUE_PTRS_QOS_MASK); 176 SET(mem_queue_ptrs, ((uint64_t)buf_ptr << 17) & PKO_MEM_QUEUE_PTRS_BUF_PTR); 177 mips_sync(); 178 _PKO_WR8(sc, PKO_MEM_QUEUE_PTRS_OFFSET, mem_queue_ptrs); 179 180 /* 181 * Set initial command buffer address and index 182 * for queue. 183 */ 184 sc->sc_cmdptr->cmdptr = (uint64_t)buf_ptr; 185 sc->sc_cmdptr->cmdptr_idx = 0; 186 187 pko_queue_map_init[sc->sc_port] = 1; 188 189 return 0; 190 } 191 192 #ifdef OCTEON_ETH_DEBUG 193 int cn30xxpko_intr_rml_verbose; 194 195 void 196 cn30xxpko_intr_rml(void *arg) 197 { 198 struct cn30xxpko_softc *sc; 199 uint64_t reg; 200 201 sc = __cn30xxpko_softc; 202 KASSERT(sc != NULL); 203 reg = cn30xxpko_int_summary(sc); 204 if (cn30xxpko_intr_rml_verbose) 205 printf("%s: PKO_REG_ERROR=0x%016llx\n", __func__, reg); 206 } 207 208 void 209 cn30xxpko_int_enable(struct cn30xxpko_softc *sc, int enable) 210 { 211 uint64_t pko_int_xxx = 0; 212 213 pko_int_xxx = PKO_REG_ERROR_DOORBELL | PKO_REG_ERROR_PARITY; 214 _PKO_WR8(sc, PKO_REG_ERROR_OFFSET, pko_int_xxx); 215 _PKO_WR8(sc, PKO_REG_INT_MASK_OFFSET, enable ? pko_int_xxx : 0); 216 } 217 218 uint64_t 219 cn30xxpko_int_summary(struct cn30xxpko_softc *sc) 220 { 221 uint64_t summary; 222 223 summary = _PKO_RD8(sc, PKO_REG_ERROR_OFFSET); 224 _PKO_WR8(sc, PKO_REG_ERROR_OFFSET, summary); 225 return summary; 226 } 227 #endif 228