1 /* $OpenBSD: cpu.h,v 1.82 2012/06/24 16:26:02 miod Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 */ 44 45 #ifndef _MIPS64_CPU_H_ 46 #define _MIPS64_CPU_H_ 47 48 #ifndef _LOCORE 49 50 /* 51 * MIPS32-style segment definitions. 52 * They only cover the first 512MB of physical addresses. 53 */ 54 #define CKSEG0_BASE 0xffffffff80000000UL 55 #define CKSEG1_BASE 0xffffffffa0000000UL 56 #define CKSSEG_BASE 0xffffffffc0000000UL 57 #define CKSEG3_BASE 0xffffffffe0000000UL 58 #define CKSEG_SIZE 0x0000000020000000UL 59 60 #define CKSEG0_TO_PHYS(x) ((u_long)(x) & (CKSEG_SIZE - 1)) 61 #define CKSEG1_TO_PHYS(x) ((u_long)(x) & (CKSEG_SIZE - 1)) 62 #define PHYS_TO_CKSEG0(x) ((u_long)(x) | CKSEG0_BASE) 63 #define PHYS_TO_CKSEG1(x) ((u_long)(x) | CKSEG1_BASE) 64 65 /* 66 * MIPS64-style segment definitions. 67 * These allow for 36 bits of addressable physical memory, thus 64GB. 68 */ 69 70 /* 71 * Cache Coherency Attributes. 72 */ 73 /* r8k only */ 74 #define CCA_NC_COPROCESSOR 0UL /* uncached, coprocessor ordered */ 75 /* common to r4, r5k, r8k and r1xk */ 76 #define CCA_NC 2UL /* uncached, write-around */ 77 #define CCA_NONCOHERENT 3UL /* cached, non-coherent, write-back */ 78 /* r8k, r1xk only */ 79 #define CCA_COHERENT_EXCL 4UL /* cached, coherent, exclusive */ 80 #define CCA_COHERENT_EXCLWRITE 5UL /* cached, coherent, exclusive write */ 81 /* r1xk only */ 82 #define CCA_NC_ACCELERATED 7UL /* uncached accelerated */ 83 /* r4k only */ 84 #define CCA_COHERENT_UPDWRITE 6UL /* cached, coherent, update on write */ 85 86 #ifdef TGT_COHERENT 87 #define CCA_CACHED CCA_COHERENT_EXCLWRITE 88 #else 89 #define CCA_CACHED CCA_NONCOHERENT 90 #endif 91 92 /* 93 * Uncached spaces. 94 * R1x000 processors use bits 58:57 of uncached virtual addresses (CCA_NC) 95 * to select different spaces. Unfortunately, other processors need these 96 * bits to be zero, so uncached address have to be decided at runtime. 97 */ 98 #define SP_HUB 0UL /* Hub space */ 99 #define SP_IO 1UL /* I/O space */ 100 #define SP_SPECIAL 2UL /* Memory Special space */ 101 #define SP_NC 3UL /* Memory Uncached space */ 102 103 #define XKSSSEG_BASE 0x4000000000000000UL 104 #define XKPHYS_BASE 0x8000000000000000UL 105 #define XKSSEG_BASE 0xc000000000000000UL 106 107 #define XKPHYS_TO_PHYS(x) ((paddr_t)(x) & 0x0000000fffffffffUL) 108 #define PHYS_TO_XKPHYS(x,c) ((paddr_t)(x) | XKPHYS_BASE | ((c) << 59)) 109 #define PHYS_TO_XKPHYS_UNCACHED(x,s) \ 110 (PHYS_TO_XKPHYS(x, CCA_NC) | ((s) << 57)) 111 #define IS_XKPHYS(va) (((va) >> 62) == 2) 112 #define XKPHYS_TO_CCA(x) (((x) >> 59) & 0x07) 113 #define XKPHYS_TO_SP(x) (((x) >> 57) & 0x03) 114 115 #endif /* _LOCORE */ 116 117 #if defined(_KERNEL) || defined(_STANDALONE) 118 119 /* 120 * Status register. 121 */ 122 #define SR_XX 0x80000000 123 #define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */ 124 #define SR_COP_0_BIT 0x10000000 125 #define SR_COP_1_BIT 0x20000000 126 #define SR_RP 0x08000000 127 #define SR_FR_32 0x04000000 128 #define SR_RE 0x02000000 129 #define SR_DSD 0x01000000 /* Only on R12000 */ 130 #define SR_BOOT_EXC_VEC 0x00400000 131 #define SR_TLB_SHUTDOWN 0x00200000 132 #define SR_SOFT_RESET 0x00100000 133 #define SR_DIAG_CH 0x00040000 134 #define SR_DIAG_CE 0x00020000 135 #define SR_DIAG_DE 0x00010000 136 #define SR_KX 0x00000080 137 #define SR_SX 0x00000040 138 #define SR_UX 0x00000020 139 #define SR_KSU_MASK 0x00000018 140 #define SR_KSU_USER 0x00000010 141 #define SR_KSU_SUPER 0x00000008 142 #define SR_KSU_KERNEL 0x00000000 143 #define SR_ERL 0x00000004 144 #define SR_EXL 0x00000002 145 #define SR_INT_ENAB 0x00000001 146 147 #define SR_INT_MASK 0x0000ff00 148 #define SOFT_INT_MASK_0 0x00000100 149 #define SOFT_INT_MASK_1 0x00000200 150 #define SR_INT_MASK_0 0x00000400 151 #define SR_INT_MASK_1 0x00000800 152 #define SR_INT_MASK_2 0x00001000 153 #define SR_INT_MASK_3 0x00002000 154 #define SR_INT_MASK_4 0x00004000 155 #define SR_INT_MASK_5 0x00008000 156 /* 157 * Interrupt control register in RM7000. Expansion of interrupts. 158 */ 159 #define IC_INT_MASK 0x00003f00 /* Two msb reserved */ 160 #define IC_INT_MASK_6 0x00000100 161 #define IC_INT_MASK_7 0x00000200 162 #define IC_INT_MASK_8 0x00000400 163 #define IC_INT_MASK_9 0x00000800 164 #define IC_INT_TIMR 0x00001000 /* 12 Timer */ 165 #define IC_INT_PERF 0x00002000 /* 13 Performance counter */ 166 #define IC_INT_TE 0x00000080 /* Timer on INT11 */ 167 168 #define ALL_INT_MASK ((IC_INT_MASK << 8) | SR_INT_MASK) 169 #define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 170 #define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK) 171 172 173 /* 174 * The bits in the cause register. 175 * 176 * CR_BR_DELAY Exception happened in branch delay slot. 177 * CR_COP_ERR Coprocessor error. 178 * CR_IP Interrupt pending bits defined below. 179 * CR_EXC_CODE The exception type (see exception codes below). 180 */ 181 #define CR_BR_DELAY 0x80000000 182 #define CR_COP_ERR 0x30000000 183 #define CR_EXC_CODE 0x0000007c 184 #define CR_EXC_CODE_SHIFT 2 185 #define CR_IPEND 0x003fff00 186 #define CR_INT_SOFT0 0x00000100 187 #define CR_INT_SOFT1 0x00000200 188 #define CR_INT_0 0x00000400 189 #define CR_INT_1 0x00000800 190 #define CR_INT_2 0x00001000 191 #define CR_INT_3 0x00002000 192 #define CR_INT_4 0x00004000 193 #define CR_INT_5 0x00008000 194 /* Following on RM7000 */ 195 #define CR_INT_6 0x00010000 196 #define CR_INT_7 0x00020000 197 #define CR_INT_8 0x00040000 198 #define CR_INT_9 0x00080000 199 #define CR_INT_HARD 0x000ffc00 200 #define CR_INT_TIMR 0x00100000 /* 12 Timer */ 201 #define CR_INT_PERF 0x00200000 /* 13 Performance counter */ 202 203 /* 204 * The bits in the context register. 205 */ 206 #define CNTXT_PTE_BASE 0xff800000 207 #define CNTXT_BAD_VPN2 0x007ffff0 208 209 /* 210 * Location of exception vectors. 211 */ 212 #define RESET_EXC_VEC (CKSEG1_BASE + 0x1fc00000) 213 #define TLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000000) 214 #define XTLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000080) 215 #define CACHE_ERR_EXC_VEC (CKSEG1_BASE + 0x00000100) 216 #define GEN_EXC_VEC (CKSEG1_BASE + 0x00000180) 217 218 /* 219 * Coprocessor 0 registers: 220 */ 221 #define COP_0_TLB_INDEX $0 222 #define COP_0_TLB_RANDOM $1 223 #define COP_0_TLB_LO0 $2 224 #define COP_0_TLB_LO1 $3 225 #define COP_0_TLB_CONTEXT $4 226 #define COP_0_TLB_PG_MASK $5 227 #define COP_0_TLB_WIRED $6 228 #define COP_0_BAD_VADDR $8 229 #define COP_0_COUNT $9 230 #define COP_0_TLB_HI $10 231 #define COP_0_COMPARE $11 232 #define COP_0_STATUS_REG $12 233 #define COP_0_CAUSE_REG $13 234 #define COP_0_EXC_PC $14 235 #define COP_0_PRID $15 236 #define COP_0_CONFIG $16 237 #define COP_0_LLADDR $17 238 #define COP_0_WATCH_LO $18 239 #define COP_0_WATCH_HI $19 240 #define COP_0_TLB_XCONTEXT $20 241 #define COP_0_TLB_FR_MASK $21 /* R10000 onwards */ 242 #define COP_0_DIAG $22 /* Loongson 2F */ 243 #define COP_0_ECC $26 244 #define COP_0_CACHE_ERR $27 245 #define COP_0_TAG_LO $28 246 #define COP_0_TAG_HI $29 247 #define COP_0_ERROR_PC $30 248 249 /* 250 * RM7000 specific 251 */ 252 #define COP_0_WATCH_1 $18 253 #define COP_0_WATCH_2 $19 254 #define COP_0_WATCH_M $24 255 #define COP_0_PC_COUNT $25 256 #define COP_0_PC_CTRL $22 257 258 #define COP_0_ICR $20 /* Use cfc0/ctc0 to access */ 259 260 /* 261 * Octeon specific 262 */ 263 #define COP_0_TLB_PG_GRAIN $5, 1 264 #define COP_0_CVMCTL $9, 7 265 #define COP_0_CVMMEMCTL $11, 7 266 #define COP_0_EBASE $15, 1 267 268 /* 269 * Values for the code field in a break instruction. 270 */ 271 #define BREAK_INSTR 0x0000000d 272 #define BREAK_VAL_MASK 0x03ff0000 273 #define BREAK_VAL_SHIFT 16 274 #define BREAK_KDB_VAL 512 275 #define BREAK_SSTEP_VAL 513 276 #define BREAK_BRKPT_VAL 514 277 #define BREAK_SOVER_VAL 515 278 #define BREAK_DDB_VAL 516 279 #define BREAK_FPUEMUL_VAL 517 280 #define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 281 #define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 282 #define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 283 #define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 284 #define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 285 #define BREAK_FPUEMUL (BREAK_INSTR | (BREAK_FPUEMUL_VAL << BREAK_VAL_SHIFT)) 286 287 /* 288 * The floating point version and status registers. 289 */ 290 #define FPC_ID $0 291 #define FPC_CSR $31 292 293 /* 294 * The low part of the TLB entry. 295 */ 296 #define VMTLB_PF_NUM 0x3fffffc0 297 #define VMTLB_ATTR_MASK 0x00000038 298 #define VMTLB_MOD_BIT 0x00000004 299 #define VMTLB_VALID_BIT 0x00000002 300 #define VMTLB_GLOBAL_BIT 0x00000001 301 302 #define VMTLB_PHYS_PAGE_SHIFT 6 303 304 /* 305 * The high part of the TLB entry. 306 */ 307 #define VMTLB_VIRT_PAGE_NUM 0xffffe000 308 #define VMTLB_PID 0x000000ff 309 #define VMTLB_PID_SHIFT 0 310 #define VMTLB_VIRT_PAGE_SHIFT 12 311 312 /* 313 * The number of process id entries. 314 */ 315 #define VMNUM_PIDS 256 316 317 /* 318 * TLB probe return codes. 319 */ 320 #define VMTLB_NOT_FOUND 0 321 #define VMTLB_FOUND 1 322 #define VMTLB_FOUND_WITH_PATCH 2 323 #define VMTLB_PROBE_ERROR 3 324 325 #endif /* _KERNEL || _STANDALONE */ 326 327 /* 328 * Exported definitions unique to mips cpu support. 329 */ 330 331 #if defined(_KERNEL) && !defined(_LOCORE) 332 333 #include <sys/device.h> 334 #include <sys/lock.h> 335 #include <machine/intr.h> 336 #include <sys/sched.h> 337 338 struct cpu_hwinfo { 339 uint32_t c0prid; 340 uint32_t c1prid; 341 uint32_t clock; /* Hz */ 342 uint32_t tlbsize; 343 uint type; 344 uint32_t l2size; 345 }; 346 347 struct cpu_info { 348 struct device *ci_dev; /* our device */ 349 struct cpu_info *ci_self; /* pointer to this structure */ 350 struct cpu_info *ci_next; /* next cpu */ 351 struct proc *ci_curproc; 352 struct user *ci_curprocpaddr; 353 struct proc *ci_fpuproc; /* pointer to last proc to use FP */ 354 uint32_t ci_delayconst; 355 struct cpu_hwinfo 356 ci_hw; 357 358 /* cache information */ 359 uint ci_cacheconfiguration; 360 uint ci_cacheways; 361 uint ci_l1instcachesize; 362 uint ci_l1instcacheline; 363 uint ci_l1instcacheset; 364 uint ci_l1datacachesize; 365 uint ci_l1datacacheline; 366 uint ci_l1datacacheset; 367 uint ci_l2size; 368 uint ci_l2line; 369 uint ci_l3size; 370 371 /* function pointers for the cache handling routines */ 372 void (*ci_SyncCache)(struct cpu_info *); 373 void (*ci_InvalidateICache)(struct cpu_info *, vaddr_t, 374 size_t); 375 void (*ci_SyncDCachePage)(struct cpu_info *, vaddr_t, 376 paddr_t); 377 void (*ci_HitSyncDCache)(struct cpu_info *, vaddr_t, size_t); 378 void (*ci_HitInvalidateDCache)(struct cpu_info *, vaddr_t, 379 size_t); 380 void (*ci_IOSyncDCache)(struct cpu_info *, vaddr_t, size_t, 381 int); 382 383 struct schedstate_percpu 384 ci_schedstate; 385 int ci_want_resched; /* need_resched() invoked */ 386 cpuid_t ci_cpuid; /* our CPU ID */ 387 uint32_t ci_randseed; /* per cpu random seed */ 388 int ci_ipl; /* software IPL */ 389 uint32_t ci_softpending; /* pending soft interrupts */ 390 int ci_clock_started; 391 u_int32_t ci_cpu_counter_last; /* last compare value loaded */ 392 u_int32_t ci_cpu_counter_interval; /* # of counter ticks/tick */ 393 394 u_int32_t ci_pendingticks; 395 struct pmap *ci_curpmap; 396 uint ci_intrdepth; /* interrupt depth */ 397 #ifdef MULTIPROCESSOR 398 u_long ci_flags; /* flags; see below */ 399 struct intrhand ci_ipiih; 400 #endif 401 volatile int ci_ddb; 402 #define CI_DDB_RUNNING 0 403 #define CI_DDB_SHOULDSTOP 1 404 #define CI_DDB_STOPPED 2 405 #define CI_DDB_ENTERDDB 3 406 #define CI_DDB_INDDB 4 407 408 #ifdef DIAGNOSTIC 409 int ci_mutex_level; 410 #endif 411 }; 412 413 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 414 #define CPUF_PRESENT 0x02 /* CPU is present */ 415 #define CPUF_RUNNING 0x04 /* CPU is running */ 416 417 extern struct cpu_info cpu_info_primary; 418 extern struct cpu_info *cpu_info_list; 419 #define CPU_INFO_ITERATOR int 420 #define CPU_INFO_FOREACH(cii, ci) for (cii = 0, ci = cpu_info_list; \ 421 ci != NULL; ci = ci->ci_next) 422 423 #define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0) 424 425 #ifdef MULTIPROCESSOR 426 #define MAXCPUS 4 427 #define getcurcpu() hw_getcurcpu() 428 #define setcurcpu(ci) hw_setcurcpu(ci) 429 extern struct cpu_info *get_cpu_info(int); 430 #define curcpu() getcurcpu() 431 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 432 #define cpu_number() (curcpu()->ci_cpuid) 433 434 extern struct cpuset cpus_running; 435 void cpu_unidle(struct cpu_info *); 436 void cpu_boot_secondary_processors(void); 437 #define cpu_boot_secondary(ci) hw_cpu_boot_secondary(ci) 438 #define cpu_hatch(ci) hw_cpu_hatch(ci) 439 440 vaddr_t alloc_contiguous_pages(size_t); 441 442 #define MIPS64_IPI_NOP 0x00000001 443 #define MIPS64_IPI_RENDEZVOUS 0x00000002 444 #define MIPS64_IPI_DDB 0x00000004 445 #define MIPS64_NIPIS 3 /* must not exceed 32 */ 446 447 void mips64_ipi_init(void); 448 void mips64_send_ipi(unsigned int, unsigned int); 449 void smp_rendezvous_cpus(unsigned long, void (*)(void *), void *arg); 450 451 #include <sys/mplock.h> 452 #else 453 #define MAXCPUS 1 454 #define curcpu() (&cpu_info_primary) 455 #define CPU_IS_PRIMARY(ci) 1 456 #define cpu_number() 0 457 #define cpu_unidle(ci) 458 #define get_cpu_info(i) (&cpu_info_primary) 459 #endif 460 461 void cpu_startclock(struct cpu_info *); 462 463 #include <machine/frame.h> 464 465 /* 466 * Arguments to hardclock encapsulate the previous machine state in 467 * an opaque clockframe. 468 */ 469 #define clockframe trap_frame /* Use normal trap frame */ 470 471 #define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 472 #define CLKF_PC(framep) ((framep)->pc) 473 #define CLKF_INTR(framep) (curcpu()->ci_intrdepth > 1) /* XXX */ 474 475 /* 476 * This is used during profiling to integrate system time. 477 */ 478 #define PROC_PC(p) ((p)->p_md.md_regs->pc) 479 480 /* 481 * Preempt the current process if in interrupt from user mode, 482 * or after the current trap/syscall if in system mode. 483 */ 484 #define need_resched(ci) \ 485 do { \ 486 (ci)->ci_want_resched = 1; \ 487 if ((ci)->ci_curproc != NULL) \ 488 aston((ci)->ci_curproc); \ 489 } while(0) 490 #define clear_resched(ci) (ci)->ci_want_resched = 0 491 492 /* 493 * Give a profiling tick to the current process when the user profiling 494 * buffer pages are invalid. On the PICA, request an ast to send us 495 * through trap, marking the proc as needing a profiling tick. 496 */ 497 #define need_proftick(p) aston(p) 498 499 /* 500 * Notify the current process (p) that it has a signal pending, 501 * process as soon as possible. 502 */ 503 #ifdef MULTIPROCESSOR 504 #define signotify(p) (aston(p), cpu_unidle(p->p_cpu)) 505 #else 506 #define signotify(p) aston(p) 507 #endif 508 509 #define aston(p) p->p_md.md_astpending = 1 510 511 #endif /* _KERNEL && !_LOCORE */ 512 513 /* 514 * CTL_MACHDEP definitions. 515 */ 516 #define CPU_ALLOWAPERTURE 1 /* allow mmap of /dev/xf86 */ 517 /* 2 formerly: keyboard reset */ 518 #define CPU_MAXID 3 /* number of valid machdep ids */ 519 520 #define CTL_MACHDEP_NAMES { \ 521 { 0, 0 }, \ 522 { "allowaperture", CTLTYPE_INT }, \ 523 { 0, 0 }, \ 524 } 525 526 /* 527 * MIPS CPU types (cp_imp). 528 */ 529 #define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 530 #define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 531 #define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 532 #define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 533 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 534 #define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 535 #define MIPS_OCTEON 0x06 /* Cavium OCTEON MIPS64R2*/ 536 #define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 537 #define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 538 #define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 539 #define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 540 #define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 541 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 542 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 543 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 544 #define MIPS_R4600 0x20 /* PMCS R4600 Orion ISA III */ 545 #define MIPS_R4700 0x21 /* PMCS R4700 Orion ISA III */ 546 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 547 #define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 548 #define MIPS_RM7000 0x27 /* PMCS RM7000 CPU ISA IV */ 549 #define MIPS_RM52X0 0x28 /* PMCS RM52X0 CPU ISA IV */ 550 #define MIPS_RM9000 0x34 /* PMCS RM9000 CPU ISA IV */ 551 #define MIPS_LOONGSON 0x42 /* STC LoongSon CPU ISA III */ 552 #define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 553 #define MIPS_LOONGSON2 0x63 /* STC LoongSon2/3 CPU ISA III+ */ 554 555 /* 556 * MIPS FPU types. Only soft, rest is the same as cpu type. 557 */ 558 #define MIPS_SOFT 0x00 /* Software emulation ISA I */ 559 560 561 #if defined(_KERNEL) && !defined(_LOCORE) 562 563 struct exec_package; 564 struct tlb_entry; 565 struct user; 566 567 u_int cp0_get_count(void); 568 uint32_t cp0_get_config(void); 569 uint32_t cp0_get_config_1(void); 570 uint32_t cp0_get_config_2(void); 571 uint32_t cp0_get_config_3(void); 572 uint32_t cp0_get_prid(void); 573 void cp0_set_compare(u_int); 574 void cp0_set_config(uint32_t); 575 u_int cp1_get_prid(void); 576 u_int tlb_get_pid(void); 577 void tlb_set_page_mask(uint32_t); 578 void tlb_set_pid(u_int); 579 void tlb_set_wired(int); 580 581 void tlb_flush(int); 582 void tlb_flush_addr(vaddr_t); 583 void tlb_write_indexed(int, struct tlb_entry *); 584 int tlb_update(vaddr_t, unsigned); 585 void tlb_read(int, struct tlb_entry *); 586 587 void build_trampoline(vaddr_t, vaddr_t); 588 void cpu_switchto_asm(struct proc *, struct proc *); 589 int exec_md_map(struct proc *, struct exec_package *); 590 void savectx(struct user *, int); 591 592 void enable_fpu(struct proc *); 593 void save_fpu(void); 594 int fpe_branch_emulate(struct proc *, struct trap_frame *, uint32_t, 595 vaddr_t); 596 void MipsSaveCurFPState(struct proc *); 597 void MipsSaveCurFPState16(struct proc *); 598 void MipsSwitchFPState(struct proc *, struct trap_frame *); 599 void MipsSwitchFPState16(struct proc *, struct trap_frame *); 600 601 int guarded_read_1(paddr_t, uint8_t *); 602 int guarded_read_2(paddr_t, uint16_t *); 603 int guarded_read_4(paddr_t, uint32_t *); 604 int guarded_write_4(paddr_t, uint32_t); 605 606 void MipsFPTrap(struct trap_frame *); 607 register_t MipsEmulateBranch(struct trap_frame *, vaddr_t, uint32_t, uint32_t); 608 609 /* 610 * Low level access routines to CPU registers 611 */ 612 613 void setsoftintr0(void); 614 void clearsoftintr0(void); 615 void setsoftintr1(void); 616 void clearsoftintr1(void); 617 uint32_t enableintr(void); 618 uint32_t disableintr(void); 619 uint32_t getsr(void); 620 uint32_t setsr(uint32_t); 621 622 /* 623 * Cache routines (may be overriden) 624 */ 625 626 #ifndef Mips_SyncCache 627 #define Mips_SyncCache(ci) \ 628 ((ci)->ci_SyncCache)(ci) 629 #endif 630 #ifndef Mips_InvalidateICache 631 #define Mips_InvalidateICache(ci, va, l) \ 632 ((ci)->ci_InvalidateICache)(ci, va, l) 633 #endif 634 #ifndef Mips_SyncDCachePage 635 #define Mips_SyncDCachePage(ci, va, pa) \ 636 ((ci)->ci_SyncDCachePage)(ci, va, pa) 637 #endif 638 #ifndef Mips_HitSyncDCache 639 #define Mips_HitSyncDCache(ci, va, l) \ 640 ((ci)->ci_HitSyncDCache)(ci, va, l) 641 #endif 642 #ifndef Mips_HitInvalidateDCache 643 #define Mips_HitInvalidateDCache(ci, va, l) \ 644 ((ci)->ci_HitInvalidateDCache)(ci, va, l) 645 #endif 646 #ifndef Mips_IOSyncDCache 647 #define Mips_IOSyncDCache(ci, va, l, h) \ 648 ((ci)->ci_IOSyncDCache)(ci, va, l, h) 649 #endif 650 651 #endif /* _KERNEL && !_LOCORE */ 652 #endif /* !_MIPS64_CPU_H_ */ 653