1 /* $OpenBSD: cpu.h,v 1.30 2009/03/26 17:24:33 oga Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 */ 44 45 #ifndef _MIPS_CPU_H_ 46 #define _MIPS_CPU_H_ 47 48 #include <machine/psl.h> 49 50 /* 51 * MIPS32-style segment definitions. 52 * They only cover the first 512MB of physical addresses. 53 */ 54 #define KSEG0_BASE 0xffffffff80000000 55 #define KSEG1_BASE 0xffffffffa0000000 56 #define KSSEG_BASE 0xffffffffc0000000 57 #define KSEG3_BASE 0xffffffffe0000000 58 #define KSEG_SIZE 0x0000000020000000 59 60 #define KSEG0_TO_PHYS(x) ((u_long)(x) & (KSEG_SIZE - 1)) 61 #define KSEG1_TO_PHYS(x) ((u_long)(x) & (KSEG_SIZE - 1)) 62 #define PHYS_TO_KSEG0(x) ((u_long)(x) | KSEG0_BASE) 63 #define PHYS_TO_KSEG1(x) ((u_long)(x) | KSEG1_BASE) 64 #define PHYS_TO_KSEG3(x) ((u_long)(x) | KSEG3_BASE) 65 66 /* 67 * MIPS64-style segment definitions. 68 * These allow for 36 bits of addressable physical memory, thus 64GB. 69 */ 70 71 #ifndef _LOCORE 72 73 /* 74 * Cache Coherency Attributes. 75 */ 76 /* r8k only */ 77 #define CCA_NC_COPROCESSOR 0UL /* uncached, coprocessor ordered */ 78 /* common to r4, r5k, r8k and r1xk */ 79 #define CCA_NC 2UL /* uncached, write-around */ 80 #define CCA_NONCOHERENT 3UL /* cached, non-coherent, write-back */ 81 /* r8k, r1xk only */ 82 #define CCA_COHERENT_EXCL 4UL /* cached, coherent, exclusive */ 83 #define CCA_COHERENT_EXCLWRITE 5UL /* cached, coherent, exclusive write */ 84 /* r1xk only */ 85 #define CCA_NC_ACCELERATED 7UL /* uncached accelerated */ 86 /* r4k only */ 87 #define CCA_COHERENT_UPDWRITE 6UL /* cached, coherent, update on write */ 88 89 #ifdef TGT_COHERENT 90 #define CCA_CACHED CCA_COHERENT_EXCLWRITE 91 #else 92 #define CCA_CACHED CCA_NONCOHERENT 93 #endif 94 95 /* 96 * Uncached spaces. 97 * R1x000 processors use bits 58:57 of uncached virtual addresses (CCA_NC) 98 * to select different spaces. Unfortunately, other processors need these 99 * bits to be zero, so uncached address have to be decided at runtime. 100 */ 101 #define SP_HUB 0UL /* Hub space */ 102 #define SP_IO 1UL /* I/O space */ 103 #define SP_SPECIAL 2UL /* Memory Special space */ 104 #define SP_NC 3UL /* Memory Uncached space */ 105 106 extern vaddr_t uncached_base; 107 108 #endif /* _LOCORE */ 109 110 #define XKPHYS_BASE 0x8000000000000000UL 111 #define XKPHYS_TO_PHYS(x) ((paddr_t)(x) & 0x0000000fffffffffUL) 112 #define PHYS_TO_XKPHYS(x,c) ((paddr_t)(x) | XKPHYS_BASE | ((c) << 59)) 113 #define PHYS_TO_XKPHYS_UNCACHED(x,s) \ 114 (PHYS_TO_XKPHYS(x, CCA_NC) | ((s) << 57)) 115 #define PHYS_TO_UNCACHED(x) ((paddr_t)(x) | uncached_base) 116 #define IS_XKPHYS(va) (((va) >> 62) == 2) 117 #define XKPHYS_TO_CCA(x) (((x) >> 59) & 0x07) 118 #define XKPHYS_TO_SP(x) (((x) >> 57) & 0x03) 119 120 #ifdef _KERNEL 121 122 /* 123 * Status register. 124 */ 125 #define SR_XX 0x80000000 126 #define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */ 127 #define SR_COP_0_BIT 0x10000000 128 #define SR_COP_1_BIT 0x20000000 129 #define SR_RP 0x08000000 130 #define SR_FR_32 0x04000000 131 #define SR_RE 0x02000000 132 #define SR_DSD 0x01000000 /* Only on R12000 */ 133 #define SR_BOOT_EXC_VEC 0x00400000 134 #define SR_TLB_SHUTDOWN 0x00200000 135 #define SR_SOFT_RESET 0x00100000 136 #define SR_DIAG_CH 0x00040000 137 #define SR_DIAG_CE 0x00020000 138 #define SR_DIAG_DE 0x00010000 139 #define SR_KX 0x00000080 140 #define SR_SX 0x00000040 141 #define SR_UX 0x00000020 142 #define SR_KSU_MASK 0x00000018 143 #define SR_KSU_USER 0x00000010 144 #define SR_KSU_SUPER 0x00000008 145 #define SR_KSU_KERNEL 0x00000000 146 #define SR_ERL 0x00000004 147 #define SR_EXL 0x00000002 148 #define SR_INT_ENAB 0x00000001 149 150 #define SR_INT_MASK 0x0000ff00 151 #define SOFT_INT_MASK_0 0x00000100 152 #define SOFT_INT_MASK_1 0x00000200 153 #define SR_INT_MASK_0 0x00000400 154 #define SR_INT_MASK_1 0x00000800 155 #define SR_INT_MASK_2 0x00001000 156 #define SR_INT_MASK_3 0x00002000 157 #define SR_INT_MASK_4 0x00004000 158 #define SR_INT_MASK_5 0x00008000 159 /* 160 * Interrupt control register in RM7000. Expansion of interrupts. 161 */ 162 #define IC_INT_MASK 0x00003f00 /* Two msb reserved */ 163 #define IC_INT_MASK_6 0x00000100 164 #define IC_INT_MASK_7 0x00000200 165 #define IC_INT_MASK_8 0x00000400 166 #define IC_INT_MASK_9 0x00000800 167 #define IC_INT_TIMR 0x00001000 /* 12 Timer */ 168 #define IC_INT_PERF 0x00002000 /* 13 Performance counter */ 169 #define IC_INT_TE 0x00000080 /* Timer on INT11 */ 170 171 #define ALL_INT_MASK ((IC_INT_MASK << 8) | SR_INT_MASK) 172 #define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 173 #define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK) 174 175 176 /* 177 * The bits in the cause register. 178 * 179 * CR_BR_DELAY Exception happened in branch delay slot. 180 * CR_COP_ERR Coprocessor error. 181 * CR_IP Interrupt pending bits defined below. 182 * CR_EXC_CODE The exception type (see exception codes below). 183 */ 184 #define CR_BR_DELAY 0x80000000 185 #define CR_COP_ERR 0x30000000 186 #define CR_EXC_CODE 0x0000007c 187 #define CR_EXC_CODE_SHIFT 2 188 #define CR_IPEND 0x003fff00 189 #define CR_INT_SOFT0 0x00000100 190 #define CR_INT_SOFT1 0x00000200 191 #define CR_INT_0 0x00000400 192 #define CR_INT_1 0x00000800 193 #define CR_INT_2 0x00001000 194 #define CR_INT_3 0x00002000 195 #define CR_INT_4 0x00004000 196 #define CR_INT_5 0x00008000 197 /* Following on RM7000 */ 198 #define CR_INT_6 0x00010000 199 #define CR_INT_7 0x00020000 200 #define CR_INT_8 0x00040000 201 #define CR_INT_9 0x00080000 202 #define CR_INT_HARD 0x000ffc00 203 #define CR_INT_TIMR 0x00100000 /* 12 Timer */ 204 #define CR_INT_PERF 0x00200000 /* 13 Performance counter */ 205 206 /* 207 * The bits in the context register. 208 */ 209 #define CNTXT_PTE_BASE 0xff800000 210 #define CNTXT_BAD_VPN2 0x007ffff0 211 212 /* 213 * Location of exception vectors. 214 */ 215 #define RESET_EXC_VEC (KSEG0_BASE + 0x3fc00000) 216 #define TLB_MISS_EXC_VEC (KSEG0_BASE + 0x00000000) 217 #define XTLB_MISS_EXC_VEC (KSEG0_BASE + 0x00000080) 218 #define CACHE_ERR_EXC_VEC (KSEG0_BASE + 0x00000100) 219 #define GEN_EXC_VEC (KSEG0_BASE + 0x00000180) 220 221 /* 222 * Coprocessor 0 registers: 223 */ 224 #define COP_0_TLB_INDEX $0 225 #define COP_0_TLB_RANDOM $1 226 #define COP_0_TLB_LO0 $2 227 #define COP_0_TLB_LO1 $3 228 #define COP_0_TLB_CONTEXT $4 229 #define COP_0_TLB_PG_MASK $5 230 #define COP_0_TLB_WIRED $6 231 #define COP_0_BAD_VADDR $8 232 #define COP_0_COUNT $9 233 #define COP_0_TLB_HI $10 234 #define COP_0_COMPARE $11 235 #define COP_0_STATUS_REG $12 236 #define COP_0_CAUSE_REG $13 237 #define COP_0_EXC_PC $14 238 #define COP_0_PRID $15 239 #define COP_0_CONFIG $16 240 #define COP_0_LLADDR $17 241 #define COP_0_WATCH_LO $18 242 #define COP_0_WATCH_HI $19 243 #define COP_0_TLB_XCONTEXT $20 244 #define COP_0_ECC $26 245 #define COP_0_CACHE_ERR $27 246 #define COP_0_TAG_LO $28 247 #define COP_0_TAG_HI $29 248 #define COP_0_ERROR_PC $30 249 250 /* 251 * RM7000 specific 252 */ 253 #define COP_0_WATCH_1 $18 254 #define COP_0_WATCH_2 $19 255 #define COP_0_WATCH_M $24 256 #define COP_0_PC_COUNT $25 257 #define COP_0_PC_CTRL $22 258 259 #define COP_0_ICR $20 /* Use cfc0/ctc0 to access */ 260 261 /* 262 * Values for the code field in a break instruction. 263 */ 264 #define BREAK_INSTR 0x0000000d 265 #define BREAK_VAL_MASK 0x03ff0000 266 #define BREAK_VAL_SHIFT 16 267 #define BREAK_KDB_VAL 512 268 #define BREAK_SSTEP_VAL 513 269 #define BREAK_BRKPT_VAL 514 270 #define BREAK_SOVER_VAL 515 271 #define BREAK_DDB_VAL 516 272 #define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 273 #define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 274 #define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 275 #define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 276 #define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 277 278 /* 279 * Mininum and maximum cache sizes. 280 */ 281 #define MIN_CACHE_SIZE (16 * 1024) 282 #define MAX_CACHE_SIZE (256 * 1024) 283 284 /* 285 * The floating point version and status registers. 286 */ 287 #define FPC_ID $0 288 #define FPC_CSR $31 289 290 /* 291 * The floating point coprocessor status register bits. 292 */ 293 #define FPC_ROUNDING_BITS 0x00000003 294 #define FPC_ROUND_RN 0x00000000 295 #define FPC_ROUND_RZ 0x00000001 296 #define FPC_ROUND_RP 0x00000002 297 #define FPC_ROUND_RM 0x00000003 298 #define FPC_STICKY_BITS 0x0000007c 299 #define FPC_STICKY_INEXACT 0x00000004 300 #define FPC_STICKY_UNDERFLOW 0x00000008 301 #define FPC_STICKY_OVERFLOW 0x00000010 302 #define FPC_STICKY_DIV0 0x00000020 303 #define FPC_STICKY_INVALID 0x00000040 304 #define FPC_ENABLE_BITS 0x00000f80 305 #define FPC_ENABLE_INEXACT 0x00000080 306 #define FPC_ENABLE_UNDERFLOW 0x00000100 307 #define FPC_ENABLE_OVERFLOW 0x00000200 308 #define FPC_ENABLE_DIV0 0x00000400 309 #define FPC_ENABLE_INVALID 0x00000800 310 #define FPC_EXCEPTION_BITS 0x0003f000 311 #define FPC_EXCEPTION_INEXACT 0x00001000 312 #define FPC_EXCEPTION_UNDERFLOW 0x00002000 313 #define FPC_EXCEPTION_OVERFLOW 0x00004000 314 #define FPC_EXCEPTION_DIV0 0x00008000 315 #define FPC_EXCEPTION_INVALID 0x00010000 316 #define FPC_EXCEPTION_UNIMPL 0x00020000 317 #define FPC_COND_BIT 0x00800000 318 #define FPC_FLUSH_BIT 0x01000000 319 #define FPC_MBZ_BITS 0xfe7c0000 320 321 /* 322 * Constants to determine if have a floating point instruction. 323 */ 324 #define OPCODE_SHIFT 26 325 #define OPCODE_C1 0x11 326 327 /* 328 * The low part of the TLB entry. 329 */ 330 #define VMTLB_PF_NUM 0x3fffffc0 331 #define VMTLB_ATTR_MASK 0x00000038 332 #define VMTLB_MOD_BIT 0x00000004 333 #define VMTLB_VALID_BIT 0x00000002 334 #define VMTLB_GLOBAL_BIT 0x00000001 335 336 #define VMTLB_PHYS_PAGE_SHIFT 6 337 338 /* 339 * The high part of the TLB entry. 340 */ 341 #define VMTLB_VIRT_PAGE_NUM 0xffffe000 342 #define VMTLB_PID 0x000000ff 343 #define VMTLB_PID_SHIFT 0 344 #define VMTLB_VIRT_PAGE_SHIFT 12 345 346 /* 347 * The number of process id entries. 348 */ 349 #define VMNUM_PIDS 256 350 351 /* 352 * TLB probe return codes. 353 */ 354 #define VMTLB_NOT_FOUND 0 355 #define VMTLB_FOUND 1 356 #define VMTLB_FOUND_WITH_PATCH 2 357 #define VMTLB_PROBE_ERROR 3 358 359 /* 360 * Exported definitions unique to mips cpu support. 361 */ 362 363 #ifndef _LOCORE 364 365 #include <sys/sched.h> 366 367 struct cpu_info { 368 struct schedstate_percpu ci_schedstate; 369 370 struct proc *ci_curproc; 371 u_int32_t ci_randseed; 372 }; 373 374 extern struct cpu_info cpu_info_primary; 375 376 #define curcpu() (&cpu_info_primary) 377 378 #define CPU_IS_PRIMARY(ci) 1 379 #define CPU_INFO_ITERATOR int 380 #define CPU_INFO_FOREACH(cii, ci) \ 381 for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL) 382 #define CPU_INFO_UNIT(ci) 0 383 #define MAXCPUS 1 384 #define cpu_unidle(ci) 385 386 #define cpu_number() 0 387 388 #include <machine/frame.h> 389 /* 390 * Arguments to hardclock and gatherstats encapsulate the previous 391 * machine state in an opaque clockframe. 392 */ 393 extern int int_nest_cntr; 394 #define clockframe trap_frame /* Use normal trap frame */ 395 396 #define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 397 #define CLKF_PC(framep) ((framep)->pc) 398 #define CLKF_INTR(framep) (int_nest_cntr > 0) 399 400 /* 401 * This is used during profiling to integrate system time. 402 */ 403 #define PROC_PC(p) ((p)->p_md.md_regs->pc) 404 405 /* 406 * Preempt the current process if in interrupt from user mode, 407 * or after the current trap/syscall if in system mode. 408 */ 409 #define need_resched(info) { want_resched = 1; aston(); } 410 #define clear_resched(ci) want_resched = 0 411 412 /* 413 * Give a profiling tick to the current process when the user profiling 414 * buffer pages are invalid. On the PICA, request an ast to send us 415 * through trap, marking the proc as needing a profiling tick. 416 */ 417 #define need_proftick(p) aston() 418 419 /* 420 * Notify the current process (p) that it has a signal pending, 421 * process as soon as possible. 422 */ 423 #define signotify(p) aston() 424 425 #define aston() (astpending = 1) 426 427 extern int want_resched; /* resched() was called */ 428 429 #endif /* !_LOCORE */ 430 #endif /* _KERNEL */ 431 432 /* 433 * CTL_MACHDEP definitions. 434 */ 435 #define CPU_ALLOWAPERTURE 1 /* allow mmap of /dev/xf86 */ 436 #define CPU_KBDRESET 2 /* keyboard reset */ 437 #define CPU_MAXID 3 /* number of valid machdep ids */ 438 439 #define CTL_MACHDEP_NAMES { \ 440 { 0, 0 }, \ 441 { "allowaperture", CTLTYPE_INT }, \ 442 { "kbdreset", CTLTYPE_INT }, \ 443 } 444 445 /* 446 * MIPS CPU types (cp_imp). 447 */ 448 #define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 449 #define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 450 #define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 451 #define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 452 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 453 #define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 454 #define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 455 #define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 456 #define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 457 #define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 458 #define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 459 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 460 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 461 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 462 #define MIPS_R4600 0x20 /* PMCS R4600 Orion ISA III */ 463 #define MIPS_R4700 0x21 /* PMCS R4700 Orion ISA III */ 464 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 465 #define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 466 #define MIPS_RM7000 0x27 /* PMCS RM7000 CPU ISA IV */ 467 #define MIPS_RM52X0 0x28 /* PMCS RM52X0 CPU ISA IV */ 468 #define MIPS_RM9000 0x34 /* PMCS RM9000 CPU ISA IV */ 469 #define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 470 471 /* 472 * MIPS FPU types. Only soft, rest is the same as cpu type. 473 */ 474 #define MIPS_SOFT 0x00 /* Software emulation ISA I */ 475 476 477 #if defined(_KERNEL) && !defined(_LOCORE) 478 479 extern u_int CpuPrimaryInstCacheSize; 480 extern u_int CpuPrimaryInstCacheLSize; 481 extern u_int CpuPrimaryInstSetSize; 482 extern u_int CpuPrimaryDataCacheSize; 483 extern u_int CpuPrimaryDataCacheLSize; 484 extern u_int CpuPrimaryDataSetSize; 485 extern u_int CpuCacheAliasMask; 486 extern u_int CpuSecondaryCacheSize; 487 extern u_int CpuTertiaryCacheSize; 488 extern u_int CpuNWayCache; 489 extern u_int CpuCacheType; /* R4K, R5K, RM7K */ 490 extern u_int CpuConfigRegister; 491 extern u_int CpuStatusRegister; 492 extern u_int CpuExternalCacheOn; /* R5K, RM7K */ 493 extern u_int CpuOnboardCacheOn; /* RM7K */ 494 495 struct tlb_entry; 496 struct user; 497 498 void tlb_set_wired(int); 499 void tlb_set_pid(int); 500 u_int cp0_get_prid(void); 501 u_int cp1_get_prid(void); 502 u_int cp0_get_count(void); 503 void cp0_set_compare(u_int); 504 505 /* 506 * Define soft selected cache functions. 507 */ 508 #define Mips_SyncCache() (*(sys_config._SyncCache))() 509 #define Mips_InvalidateICache(a, l) \ 510 (*(sys_config._InvalidateICache))((a), (l)) 511 #define Mips_InvalidateICachePage(a) \ 512 (*(sys_config._InvalidateICachePage))((a)) 513 #define Mips_SyncDCachePage(a) \ 514 (*(sys_config._SyncDCachePage))((a)) 515 #define Mips_HitSyncDCache(a, l) \ 516 (*(sys_config._HitSyncDCache))((a), (l)) 517 #define Mips_IOSyncDCache(a, l, h) \ 518 (*(sys_config._IOSyncDCache))((a), (l), (h)) 519 #define Mips_HitInvalidateDCache(a, l) \ 520 (*(sys_config._HitInvalidateDCache))((a), (l)) 521 522 int Mips5k_ConfigCache(void); 523 void Mips5k_SyncCache(void); 524 void Mips5k_InvalidateICache(vaddr_t, int); 525 void Mips5k_InvalidateICachePage(vaddr_t); 526 void Mips5k_SyncDCachePage(vaddr_t); 527 void Mips5k_HitSyncDCache(vaddr_t, int); 528 void Mips5k_IOSyncDCache(vaddr_t, int, int); 529 void Mips5k_HitInvalidateDCache(vaddr_t, int); 530 531 int Mips10k_ConfigCache(void); 532 void Mips10k_SyncCache(void); 533 void Mips10k_InvalidateICache(vaddr_t, int); 534 void Mips10k_InvalidateICachePage(vaddr_t); 535 void Mips10k_SyncDCachePage(vaddr_t); 536 void Mips10k_HitSyncDCache(vaddr_t, int); 537 void Mips10k_IOSyncDCache(vaddr_t, int, int); 538 void Mips10k_HitInvalidateDCache(vaddr_t, int); 539 540 void tlb_flush(int); 541 void tlb_flush_addr(vaddr_t); 542 void tlb_write_indexed(int, struct tlb_entry *); 543 int tlb_update(vaddr_t, unsigned); 544 void tlb_read(int, struct tlb_entry *); 545 546 void savectx(struct user *, int); 547 void MipsSaveCurFPState(struct proc *); 548 void MipsSaveCurFPState16(struct proc *); 549 550 int guarded_read_4(paddr_t, uint32_t *); 551 int guarded_write_4(paddr_t, uint32_t); 552 553 extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */ 554 extern u_int32_t cpu_counter_last; /* Last compare value loaded */ 555 556 /* 557 * Low level access routines to CPU registers 558 */ 559 560 void setsoftintr0(void); 561 void clearsoftintr0(void); 562 void setsoftintr1(void); 563 void clearsoftintr1(void); 564 u_int32_t enableintr(void); 565 u_int32_t disableintr(void); 566 u_int32_t updateimask(intrmask_t); 567 void setsr(u_int32_t); 568 u_int32_t getsr(void); 569 570 #endif /* _KERNEL */ 571 #endif /* !_MIPS_CPU_H_ */ 572