1 /* $OpenBSD: bus.h,v 1.25 2016/05/03 12:23:25 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Per Fogelstrom. All rights reserved. 5 * Copyright (c) 1996 Niklas Hallqvist. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Christopher G. Demetriou 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _MACHINE_BUS_H_ 35 #define _MACHINE_BUS_H_ 36 37 #include <machine/pio.h> 38 39 #ifdef __STDC__ 40 #define CAT(a,b) a##b 41 #define CAT3(a,b,c) a##b##c 42 #else 43 #define CAT(a,b) a/**/b 44 #define CAT3(a,b,c) a/**/b/**/c 45 #endif 46 47 /* 48 * Bus access types. 49 */ 50 typedef u_long bus_addr_t; 51 typedef u_long bus_size_t; 52 typedef u_long bus_space_handle_t; 53 typedef struct ppc_bus_space *bus_space_tag_t; 54 55 struct ppc_bus_space { 56 u_int32_t bus_base; 57 u_int32_t bus_size; 58 u_int8_t bus_io; /* IO or memory */ 59 }; 60 #define POWERPC_BUS_TAG_BASE(x) ((x)->bus_base) 61 62 extern struct ppc_bus_space ppc_isa_io, ppc_isa_mem; 63 64 /* 65 * Access methods for bus resources 66 */ 67 int bus_space_map(bus_space_tag_t t, bus_addr_t addr, 68 bus_size_t size, int flags, bus_space_handle_t *bshp); 69 void bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, 70 bus_size_t size); 71 int bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh, 72 bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp); 73 int bus_space_alloc(bus_space_tag_t tag, bus_addr_t rstart, 74 bus_addr_t rend, bus_size_t size, bus_size_t alignment, 75 bus_size_t boundary, int flags, bus_addr_t *addrp, 76 bus_space_handle_t *handlep); 77 void bus_space_free(bus_space_tag_t tag, bus_space_handle_t handle, 78 bus_size_t size); 79 paddr_t bus_space_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 80 81 #define BUS_SPACE_MAP_CACHEABLE 0x01 82 #define BUS_SPACE_MAP_LINEAR 0x02 83 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 84 85 /* 86 * void *bus_space_vaddr(bus_space_tag_t, bus_space_handle_t); 87 * 88 * Get the kernel virtual address for the mapped bus space. 89 * Only allowed for regions mapped with BUS_SPACE_MAP_LINEAR. 90 */ 91 #define bus_space_vaddr(t, h) ((void *)(h)) 92 93 #define bus_space_read(n,m) \ 94 static __inline CAT3(u_int,m,_t) \ 95 CAT(bus_space_read_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \ 96 bus_addr_t ba) \ 97 { \ 98 return CAT3(in,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (ba))); \ 99 } 100 101 bus_space_read(1,8) 102 bus_space_read(2,16) 103 bus_space_read(4,32) 104 105 #define bus_space_read_8 !!! bus_space_read_8 unimplemented !!! 106 107 #define bus_space_write(n,m) \ 108 static __inline void \ 109 CAT(bus_space_write_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \ 110 bus_addr_t ba, CAT3(u_int,m,_t) x) \ 111 { \ 112 CAT3(out,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (ba)), x); \ 113 } 114 115 bus_space_write(1,8) 116 bus_space_write(2,16) 117 bus_space_write(4,32) 118 119 #define bus_space_write_8 !!! bus_space_write_8 unimplemented !!! 120 121 #define bus_space_read_raw(n,m) \ 122 static __inline CAT3(u_int,m,_t) \ 123 CAT(bus_space_read_raw_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \ 124 bus_addr_t ba) \ 125 { \ 126 return CAT(in,m)((volatile CAT3(u_int,m,_t) *)(bsh + (ba))); \ 127 } 128 129 bus_space_read_raw(1,8) 130 bus_space_read_raw(2,16) 131 bus_space_read_raw(4,32) 132 133 #define bus_space_read_raw_8 !!! bus_space_read_raw_8 unimplemented !!! 134 135 #define bus_space_write_raw(n,m) \ 136 static __inline void \ 137 CAT(bus_space_write_raw_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \ 138 bus_addr_t ba, CAT3(u_int,m,_t) x) \ 139 { \ 140 CAT(out,m)((volatile CAT3(u_int,m,_t) *)(bsh + (ba)), x); \ 141 } 142 143 bus_space_write_raw(1,8) 144 bus_space_write_raw(2,16) 145 bus_space_write_raw(4,32) 146 147 #define bus_space_write_raw_8 !!! bus_space_write_raw_8 unimplemented !!! 148 149 #define bus_space_read_multi(n, m) \ 150 static __inline void \ 151 CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \ 152 bus_size_t ba, CAT3(u_int,m,_t) *buf, bus_size_t cnt) \ 153 { \ 154 while (cnt--) \ 155 *buf++ = CAT(bus_space_read_,n)(bst, bsh, ba); \ 156 } 157 158 bus_space_read_multi(1,8) 159 bus_space_read_multi(2,16) 160 bus_space_read_multi(4,32) 161 162 #define bus_space_read_multi_8 !!! bus_space_read_multi_8 not implemented !!! 163 164 165 #define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!! 166 167 #define bus_space_write_multi(n, m) \ 168 static __inline void \ 169 CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \ 170 bus_size_t ba, const CAT3(u_int,m,_t) *buf, bus_size_t cnt) \ 171 { \ 172 while (cnt--) \ 173 CAT(bus_space_write_,n)(bst, bsh, ba, *buf++); \ 174 } 175 176 bus_space_write_multi(1,8) 177 bus_space_write_multi(2,16) 178 bus_space_write_multi(4,32) 179 180 #define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!! 181 182 /* 183 * void bus_space_read_region_N(bus_space_tag_t tag, 184 * bus_space_handle_t bsh, bus_size_t offset, 185 * u_intN_t *addr, size_t count); 186 * 187 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 188 * described by tag/handle and starting at `offset' and copy into 189 * buffer provided. 190 */ 191 #define __BA(t, h, o) ((void *)((h) + (o))) 192 193 static __inline void 194 bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, 195 bus_size_t offset, u_int8_t *addr, size_t count) 196 { 197 volatile u_int8_t *s = __BA(tag, bsh, offset); 198 199 while (count--) 200 *addr++ = *s++; 201 __asm volatile("eieio; sync"); 202 } 203 204 static __inline void 205 bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, 206 bus_size_t offset, u_int16_t *addr, size_t count) 207 { 208 volatile u_int16_t *s = __BA(tag, bsh, offset); 209 210 while (count--) 211 __asm volatile("lhbrx %0, 0, %1" : 212 "=r"(*addr++) : "r"(s++)); 213 __asm volatile("eieio; sync"); 214 } 215 216 static __inline void 217 bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, 218 bus_size_t offset, u_int32_t *addr, size_t count) 219 { 220 volatile u_int32_t *s = __BA(tag, bsh, offset); 221 222 while (count--) 223 __asm volatile("lwbrx %0, 0, %1" : 224 "=r"(*addr++) : "r"(s++)); 225 __asm volatile("eieio; sync"); 226 } 227 228 #if 0 /* Cause a link error for bus_space_read_region_8 */ 229 #define bus_space_read_region_8 !!! unimplemented !!! 230 #endif 231 232 233 /* 234 * void bus_space_write_region_N(bus_space_tag_t tag, 235 * bus_space_handle_t bsh, bus_size_t offset, 236 * const u_intN_t *addr, size_t count); 237 * 238 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided 239 * to bus space described by tag/handle starting at `offset'. 240 */ 241 242 static __inline void 243 bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, 244 bus_size_t offset, const u_int8_t *addr, size_t count) 245 { 246 volatile u_int8_t *d = __BA(tag, bsh, offset); 247 248 while (count--) 249 *d++ = *addr++; 250 __asm volatile("eieio; sync"); 251 } 252 253 static __inline void 254 bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, 255 bus_size_t offset, const u_int16_t *addr, size_t count) 256 { 257 volatile u_int16_t *d = __BA(tag, bsh, offset); 258 259 while (count--) 260 __asm volatile("sthbrx %0, 0, %1" :: 261 "r"(*addr++), "r"(d++)); 262 __asm volatile("eieio; sync"); 263 } 264 265 static __inline void 266 bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, 267 bus_size_t offset, const u_int32_t *addr, size_t count) 268 { 269 volatile u_int32_t *d = __BA(tag, bsh, offset); 270 271 while (count--) 272 __asm volatile("stwbrx %0, 0, %1" :: 273 "r"(*addr++), "r"(d++)); 274 __asm volatile("eieio; sync"); 275 } 276 277 #if 0 278 #define bus_space_write_region_8 !!! bus_space_write_region_8 unimplemented !!! 279 #endif 280 281 /* 282 * void bus_space_read_raw_region_N(bus_space_tag_t tag, 283 * bus_space_handle_t bsh, bus_size_t offset, 284 * u_intN_t *addr, size_t count); 285 * 286 * Read `count' bytes from bus space described by tag/handle and starting 287 * at `offset' and copy into buffer provided w/o bus-host byte swapping. 288 */ 289 290 static __inline void 291 bus_space_read_raw_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, 292 bus_size_t offset, u_int8_t *addr, size_t count) 293 { 294 volatile u_int16_t *s = __BA(tag, bsh, offset); 295 u_int16_t *laddr = (void *)addr; 296 297 count = count >> 1; 298 299 while (count--) 300 *laddr++ = *s++; 301 __asm volatile("eieio; sync"); 302 } 303 304 static __inline void 305 bus_space_read_raw_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, 306 bus_size_t offset, u_int8_t *addr, size_t count) 307 { 308 volatile u_int32_t *s = __BA(tag, bsh, offset); 309 u_int32_t *laddr = (void *)addr; 310 311 count = count >> 2; 312 313 while (count--) 314 *laddr++ = *s++; 315 __asm volatile("eieio; sync"); 316 } 317 318 #if 0 /* Cause a link error for bus_space_read_raw_region_8 */ 319 #define bus_space_read_raw_region_8 \ 320 !!! bus_space_read_raw_region_8 unimplemented !!! 321 #endif 322 323 324 /* 325 * void bus_space_write_raw_region_N(bus_space_tag_t tag, 326 * bus_space_handle_t bsh, bus_size_t offset, 327 * const u_intN_t *addr, size_t count); 328 * 329 * Write `count' bytes from the buffer provided to bus space described 330 * by tag/handle starting at `offset' w/o host-bus byte swapping. 331 */ 332 333 static __inline void 334 bus_space_write_raw_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, 335 bus_size_t offset, const u_int8_t *addr, size_t count) 336 { 337 volatile u_int16_t *d = __BA(tag, bsh, offset); 338 const u_int16_t *laddr = (void *)addr; 339 340 count = count >> 1; 341 342 while (count--) 343 *d++ = *laddr++; 344 __asm volatile("eieio; sync"); 345 } 346 347 static __inline void 348 bus_space_write_raw_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, 349 bus_size_t offset, const u_int8_t *addr, size_t count) 350 { 351 volatile u_int32_t *d = __BA(tag, bsh, offset); 352 const u_int32_t *laddr = (void *)addr; 353 354 count = count >> 2; 355 356 while (count--) 357 *d++ = *laddr++; 358 __asm volatile("eieio; sync"); 359 } 360 361 #if 0 362 #define bus_space_write_raw_region_8 \ 363 !!! bus_space_write_raw_region_8 unimplemented !!! 364 #endif 365 366 /* 367 * void bus_space_set_multi_N(bus_space_tag_t tag, 368 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val, 369 * size_t count); 370 * 371 * Write the 1, 2, 4, or 8 byte value `val' to bus space described 372 * by tag/handle/offset `count' times. 373 */ 374 static __inline void bus_space_set_multi_1(bus_space_tag_t, 375 bus_space_handle_t, bus_size_t, u_int8_t, size_t); 376 static __inline void bus_space_set_multi_2(bus_space_tag_t, 377 bus_space_handle_t, bus_size_t, u_int16_t, size_t); 378 static __inline void bus_space_set_multi_4(bus_space_tag_t, 379 bus_space_handle_t, bus_size_t, u_int32_t, size_t); 380 381 static __inline void 382 bus_space_set_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, 383 bus_size_t offset, u_int8_t val, size_t count) 384 { 385 volatile u_int8_t *d = __BA(tag, bsh, offset); 386 387 while (count--) 388 *d = val; 389 __asm__ volatile("eieio; sync"); 390 } 391 392 static __inline void 393 bus_space_set_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, 394 bus_size_t offset, u_int16_t val, size_t count) 395 { 396 volatile u_int16_t *d = __BA(tag, bsh, offset); 397 398 while (count--) 399 __asm__ volatile("sthbrx %0, 0, %1" :: 400 "r"(val), "r"(d)); 401 __asm__ volatile("eieio; sync"); 402 } 403 404 static __inline void 405 bus_space_set_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh, 406 bus_size_t offset, u_int32_t val, size_t count) 407 { 408 volatile u_int32_t *d = __BA(tag, bsh, offset); 409 410 while (count--) 411 __asm__ volatile("stwbrx %0, 0, %1" :: 412 "r"(val), "r"(d)); 413 __asm__ volatile("eieio; sync"); 414 } 415 416 #define bus_space_set_multi_8 !!! bus_space_set_multi_8 unimplemented !!! 417 418 /* These are OpenBSD extensions to the general NetBSD bus interface. */ 419 void 420 bus_space_read_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, 421 bus_addr_t ba, u_int8_t *dst, bus_size_t size); 422 void 423 bus_space_read_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, 424 bus_addr_t ba, u_int8_t *dst, bus_size_t size); 425 #define bus_space_read_raw_multi_8 \ 426 !!! bus_space_read_raw_multi_8 not implemented !!! 427 428 void 429 bus_space_write_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh, 430 bus_addr_t ba, const u_int8_t *src, bus_size_t size); 431 void 432 bus_space_write_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh, 433 bus_addr_t ba, const u_int8_t *src, bus_size_t size); 434 #define bus_space_write_raw_multi_8 \ 435 !!! bus_space_write_raw_multi_8 not implemented !!! 436 437 void 438 bus_space_set_region_1(bus_space_tag_t bst, bus_space_handle_t h, bus_size_t o, 439 u_int8_t val, bus_size_t c); 440 void 441 bus_space_set_region_2(bus_space_tag_t bst, bus_space_handle_t h, bus_size_t o, 442 u_int16_t val, bus_size_t c); 443 void 444 bus_space_set_region_4(bus_space_tag_t bst, bus_space_handle_t h, bus_size_t o, 445 u_int32_t val, bus_size_t c); 446 #define bus_space_set_region_8 \ 447 !!! bus_space_set_region_8 not implemented !!! 448 449 void 450 bus_space_copy_1(void *v, bus_space_handle_t h1, bus_space_handle_t h2, 451 bus_size_t o1, bus_size_t o2, bus_size_t c); 452 void 453 bus_space_copy_2(void *v, bus_space_handle_t h1, bus_space_handle_t h2, 454 bus_size_t o1, bus_size_t o2, bus_size_t c); 455 void 456 bus_space_copy_4(void *v, bus_space_handle_t h1, bus_space_handle_t h2, 457 bus_size_t o1, bus_size_t o2, bus_size_t c); 458 #define bus_space_copy_8 \ 459 !!! bus_space_copy_8 not implemented !!! 460 461 /* 462 * Bus read/write barrier methods. 463 * 464 * void bus_space_barrier(bus_space_tag_t tag, 465 * bus_space_handle_t bsh, bus_size_t offset, 466 * bus_size_t len, int flags); 467 * 468 * Note: powerpc does not currently implement barriers, but we must 469 * provide the flags to MI code. 470 * the processor does have eieio which is effectively the barrier 471 * operator, however due to how memory is mapped this should? not 472 * be required. 473 */ 474 #define bus_space_barrier(t, h, o, l, f) \ 475 ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f))) 476 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 477 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 478 479 #define BUS_DMA_WAITOK 0x0000 /* safe to sleep (pseudo-flag) */ 480 #define BUS_DMA_NOWAIT 0x0001 /* not safe to sleep */ 481 #define BUS_DMA_ALLOCNOW 0x0002 /* perform resource allocation now */ 482 #define BUS_DMA_COHERENT 0x0008 /* hint: map memory DMA coherent */ 483 #define BUS_DMA_BUS1 0x0010 /* placeholders for bus functions... */ 484 #define BUS_DMA_BUS2 0x0020 485 #define BUS_DMA_BUS3 0x0040 486 #define BUS_DMA_BUS4 0x0080 487 #define BUS_DMA_READ 0x0100 /* mapping is device -> memory only */ 488 #define BUS_DMA_WRITE 0x0200 /* mapping is memory -> device only */ 489 #define BUS_DMA_STREAMING 0x0400 /* hint: sequential, unidirectional */ 490 #define BUS_DMA_ZERO 0x0800 /* zero memory in dmamem_alloc */ 491 #define BUS_DMA_NOCACHE 0x1000 /* map memory uncached */ 492 493 494 /* Forwards needed by prototypes below. */ 495 struct mbuf; 496 struct proc; 497 struct uio; 498 499 #define BUS_DMASYNC_POSTREAD 0x01 500 #define BUS_DMASYNC_POSTWRITE 0x02 501 #define BUS_DMASYNC_PREREAD 0x04 502 #define BUS_DMASYNC_PREWRITE 0x08 503 504 typedef struct powerpc_bus_dma_tag *bus_dma_tag_t; 505 typedef struct powerpc_bus_dmamap *bus_dmamap_t; 506 507 /* 508 * bus_dma_segment_t 509 * 510 * Describes a single contiguous DMA transaction. Values 511 * are suitable for programming into DMA registers. 512 */ 513 struct powerpc_bus_dma_segment { 514 bus_addr_t ds_addr; /* DMA address */ 515 bus_size_t ds_len; /* length of transfer */ 516 }; 517 typedef struct powerpc_bus_dma_segment bus_dma_segment_t; 518 519 /* 520 * bus_dma_tag_t 521 * 522 * A machine-dependent opaque type describing the implementation of 523 * DMA for a given bus. 524 */ 525 526 struct powerpc_bus_dma_tag { 527 void *_cookie; /* cookie used in the guts */ 528 529 /* 530 * DMA mapping methods. 531 */ 532 int (*_dmamap_create)(bus_dma_tag_t , bus_size_t, int, 533 bus_size_t, bus_size_t, int, bus_dmamap_t *); 534 void (*_dmamap_destroy)(bus_dma_tag_t , bus_dmamap_t); 535 int (*_dmamap_load)(bus_dma_tag_t , bus_dmamap_t, void *, 536 bus_size_t, struct proc *, int); 537 int (*_dmamap_load_mbuf)(bus_dma_tag_t , bus_dmamap_t, 538 struct mbuf *, int); 539 int (*_dmamap_load_uio)(bus_dma_tag_t , bus_dmamap_t, 540 struct uio *, int); 541 int (*_dmamap_load_raw)(bus_dma_tag_t , bus_dmamap_t, 542 bus_dma_segment_t *, int, bus_size_t, int); 543 void (*_dmamap_unload)(bus_dma_tag_t , bus_dmamap_t); 544 void (*_dmamap_sync)(bus_dma_tag_t , bus_dmamap_t, 545 bus_addr_t, bus_size_t, int); 546 547 /* 548 * DMA memory utility functions. 549 */ 550 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 551 bus_size_t, bus_dma_segment_t *, int, int *, int); 552 int (*_dmamem_alloc_range)(bus_dma_tag_t, bus_size_t, bus_size_t, 553 bus_size_t, bus_dma_segment_t *, int, int *, int, 554 bus_addr_t, bus_addr_t); 555 void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int); 556 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 557 int, size_t, caddr_t *, int); 558 void (*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t); 559 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 560 int, off_t, int, int); 561 }; 562 563 #define bus_dmamap_create(t, s, n, m, b, f, p) \ 564 (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p)) 565 #define bus_dmamap_destroy(t, p) \ 566 (*(t)->_dmamap_destroy)((t), (p)) 567 #define bus_dmamap_load(t, m, b, s, p, f) \ 568 (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f)) 569 #define bus_dmamap_load_mbuf(t, m, b, f) \ 570 (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f)) 571 #define bus_dmamap_load_uio(t, m, u, f) \ 572 (*(t)->_dmamap_load_uio)((t), (m), (u), (f)) 573 #define bus_dmamap_load_raw(t, m, sg, n, s, f) \ 574 (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f)) 575 #define bus_dmamap_unload(t, p) \ 576 (*(t)->_dmamap_unload)((t), (p)) 577 #define bus_dmamap_sync(t, p, a, l, o) \ 578 (void)((t)->_dmamap_sync ? \ 579 (*(t)->_dmamap_sync)((t), (p), (a), (l), (o)) : (void)0) 580 581 #define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \ 582 (*(t)->_dmamem_alloc)((t)->_cookie, (s), (a), (b), (sg), (n), (r), (f)) 583 #define bus_dmamem_alloc_range(t, s, a, b, sg, n, r, f, l, h) \ 584 (*(t)->_dmamem_alloc_range)((t), (s), (a), (b), (sg), \ 585 (n), (r), (f), (l), (h)) 586 #define bus_dmamem_free(t, sg, n) \ 587 (*(t)->_dmamem_free)((t)->_cookie, (sg), (n)) 588 #define bus_dmamem_map(t, sg, n, s, k, f) \ 589 (*(t)->_dmamem_map)((t)->_cookie, (sg), (n), (s), (k), (f)) 590 #define bus_dmamem_unmap(t, k, s) \ 591 (*(t)->_dmamem_unmap)((t)->_cookie, (k), (s)) 592 #define bus_dmamem_mmap(t, sg, n, o, p, f) \ 593 (*(t)->_dmamem_mmap)((t)->_cookie, (sg), (n), (o), (p), (f)) 594 595 int _dmamap_create(bus_dma_tag_t, bus_size_t, int, 596 bus_size_t, bus_size_t, int, bus_dmamap_t *); 597 void _dmamap_destroy(bus_dma_tag_t, bus_dmamap_t); 598 int _dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, 599 bus_size_t, struct proc *, int); 600 int _dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int); 601 int _dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int); 602 int _dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t, 603 bus_dma_segment_t *, int, bus_size_t, int); 604 void _dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 605 void _dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, bus_size_t, 606 int); 607 608 int _dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t, 609 bus_size_t, bus_dma_segment_t *, int, int *, int); 610 int _dmamem_alloc_range( bus_dma_tag_t, bus_size_t, bus_size_t, 611 bus_size_t, bus_dma_segment_t *, int, int *, int, 612 bus_addr_t, bus_addr_t); 613 void _dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int); 614 int _dmamem_map(bus_dma_tag_t, bus_dma_segment_t *, 615 int, size_t, caddr_t *, int); 616 void _dmamem_unmap(bus_dma_tag_t, caddr_t, size_t); 617 paddr_t _dmamem_mmap(bus_dma_tag_t, bus_dma_segment_t *, int, off_t, int, int); 618 619 /* 620 * bus_dmamap_t 621 * 622 * Describes a DMA mapping. 623 */ 624 struct powerpc_bus_dmamap { 625 /* 626 * PRIVATE MEMBERS: not for use by machine-independent code. 627 */ 628 bus_size_t _dm_size; /* largest DMA transfer mappable */ 629 int _dm_segcnt; /* number of segs this map can map */ 630 bus_size_t _dm_maxsegsz; /* largest possible segment */ 631 bus_size_t _dm_boundary; /* don't cross this */ 632 int _dm_flags; /* misc. flags */ 633 634 void *_dm_cookie; /* cookie for bus-specific functions */ 635 636 /* 637 * PUBLIC MEMBERS: these are used by machine-independent code. 638 */ 639 bus_size_t dm_mapsize; /* size of the mapping */ 640 int dm_nsegs; /* # valid segments in mapping */ 641 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 642 }; 643 644 #endif /* _MACHINE_BUS_H_ */ 645