1 /* $OpenBSD: if_mc.c,v 1.14 2010/04/21 03:03:26 deraadt Exp $ */ 2 /* $NetBSD: if_mc.c,v 1.9.16.1 2006/06/21 14:53:13 yamt Exp $ */ 3 4 /*- 5 * Copyright (c) 1997 David Huang <khym@bga.com> 6 * All rights reserved. 7 * 8 * Portions of this code are based on code by Denton Gentry <denny1@home.com> 9 * and Yanagisawa Takeshi <yanagisw@aa.ap.titech.ac.jp>. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * AMD AM79C940 (MACE) driver with DBDMA bus attachment and DMA routines 34 * for onboard ethernet found on most old world macs. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/buf.h> 41 #include <sys/protosw.h> 42 #include <sys/socket.h> 43 #include <sys/syslog.h> 44 #include <sys/ioctl.h> 45 #include <sys/errno.h> 46 #include <sys/device.h> 47 #include <sys/timeout.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/if_ether.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #endif 62 63 #include "bpfilter.h" 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #include <net/bpfdesc.h> 67 #endif 68 69 #include <dev/ofw/openfirm.h> 70 #include <machine/pio.h> 71 #include <machine/bus.h> 72 #include <machine/autoconf.h> 73 74 #include <macppc/dev/dbdma.h> 75 76 #define MC_REGSPACING 16 77 #define MC_REGSIZE MACE_NREGS * MC_REGSPACING 78 #define MACE_REG(x) ((x)*MC_REGSPACING) 79 #define MACE_BUFLEN 2048 80 #define MACE_TXBUFS 2 81 #define MACE_RXBUFS 8 82 83 #define MC_RXDMABUFS 4 84 85 #define MACE_BUFSZ ((MACE_RXBUFS + MACE_TXBUFS + 2) * MACE_BUFLEN) 86 87 #define NIC_GET(sc, reg) (in8rb(sc->sc_reg + MACE_REG(reg))) 88 89 #define NIC_PUT(sc, reg, val) (out8rb(sc->sc_reg + MACE_REG(reg), (val))) 90 91 /* 92 * AMD MACE (Am79C940) register definitions 93 */ 94 #define MACE_RCVFIFO 0 /* Receive FIFO [15-00] (read only) */ 95 #define MACE_XMTFIFO 1 /* Transmit FIFO [15-00] (write only) */ 96 #define MACE_XMTFC 2 /* Transmit Frame Control (read/write) */ 97 #define MACE_XMTFS 3 /* Transmit Frame Status (read only) */ 98 #define MACE_XMTRC 4 /* Transmit Retry Count (read only) */ 99 #define MACE_RCVFC 5 /* Receive Frame Control (read/write) */ 100 #define MACE_RCVFS 6 /* Receive Frame Status (4 bytes) (read only) */ 101 #define MACE_FIFOFC 7 /* FIFO Frame Count (read only) */ 102 #define MACE_IR 8 /* Interrupt Register (read only) */ 103 #define MACE_IMR 9 /* Interrupt Mask Register (read/write) */ 104 #define MACE_PR 10 /* Poll Register (read only) */ 105 #define MACE_BIUCC 11 /* BIU Configuration Control (read/write) */ 106 #define MACE_FIFOCC 12 /* FIFO Configuration Control (read/write) */ 107 #define MACE_MACCC 13 /* MAC Configuration Control (read/write) */ 108 #define MACE_PLSCC 14 /* PLS Configuration Control (read/write) */ 109 #define MACE_PHYCC 15 /* PHY Confiuration Control (read/write) */ 110 #define MACE_CHIPIDL 16 /* Chip ID Register [07-00] (read only) */ 111 #define MACE_CHIPIDH 17 /* Chip ID Register [15-08] (read only) */ 112 #define MACE_IAC 18 /* Internal Address Configuration (read/write) */ 113 /* RESERVED 19 Reserved (read/write as 0) */ 114 #define MACE_LADRF 20 /* Logical Address Filter (8 bytes) (read/write) */ 115 #define MACE_PADR 21 /* Physical Address (6 bytes) (read/write) */ 116 /* RESERVED 22 Reserved (read/write as 0) */ 117 /* RESERVED 23 Reserved (read/write as 0) */ 118 #define MACE_MPC 24 /* Missed Packet Count (read only) */ 119 /* RESERVED 25 Reserved (read/write as 0) */ 120 #define MACE_RNTPC 26 /* Runt Packet Count (read only) */ 121 #define MACE_RCVCC 27 /* Receive Collision Count (read only) */ 122 /* RESERVED 28 Reserved (read/write as 0) */ 123 #define MACE_UTR 29 /* User Test Register (read/write) */ 124 #define MACE_RTR1 30 /* Reserved Test Register 1 (read/write as 0) */ 125 #define MACE_RTR2 31 /* Reserved Test Register 2 (read/write as 0) */ 126 127 #define MACE_NREGS 32 128 129 /* 2: Transmit Frame Control (XMTFC) */ 130 #define DRTRY 0x80 /* Disable Retry */ 131 #define DXMTFCS 0x08 /* Disable Transmit FCS */ 132 #define APADXMT 0x01 /* Auto Pad Transmit */ 133 134 /* 3: Transmit Frame Status (XMTFS) */ 135 #define XMTSV 0x80 /* Transmit Status Valid */ 136 #define UFLO 0x40 /* Underflow */ 137 #define LCOL 0x20 /* Late Collision */ 138 #define MORE 0x10 /* More than one retry needed */ 139 #define ONE 0x08 /* Exactly one retry needed */ 140 #define DEFER 0x04 /* Transmission deferred */ 141 #define LCAR 0x02 /* Loss of Carrier */ 142 #define RTRY 0x01 /* Retry Error */ 143 144 /* 4: Transmit Retry Count (XMTRC) */ 145 #define EXDEF 0x80 /* Excessive Defer */ 146 #define XMTRC 0x0f /* Transmit Retry Count */ 147 148 /* 5: Receive Frame Control (RCVFC) */ 149 #define LLRCV 0x08 /* Low Latency Receive */ 150 #define MR 0x04 /* Match/Reject */ 151 #define ASTRPRCV 0x01 /* Auto Strip Receive */ 152 153 /* 6: Receive Frame Status (RCVFS) */ 154 /* 4 byte register; read 4 times to get all of the bytes */ 155 /* Read 1: RFS0 - Receive Message Byte Count [7-0] (RCVCNT) */ 156 157 /* Read 2: RFS1 - Receive Status (RCVSTS) */ 158 #define OFLO 0x80 /* Overflow flag */ 159 #define CLSN 0x40 /* Collision flag */ 160 #define FRAM 0x20 /* Framing Error flag */ 161 #define FCS 0x10 /* FCS Error flag */ 162 #define RCVCNT 0x0f /* Receive Message Byte Count [11-8] */ 163 164 /* Read 3: RFS2 - Runt Packet Count (RNTPC) [7-0] */ 165 166 /* Read 4: RFS3 - Receive Collision Count (RCVCC) [7-0] */ 167 168 /* 7: FIFO Frame Count (FIFOFC) */ 169 #define RCVFC 0xf0 /* Receive Frame Count */ 170 #define XMTFC 0x0f /* Transmit Frame Count */ 171 172 /* 8: Interrupt Register (IR) */ 173 #define JAB 0x80 /* Jabber Error */ 174 #define BABL 0x40 /* Babble Error */ 175 #define CERR 0x20 /* Collision Error */ 176 #define RCVCCO 0x10 /* Receive Collision Count Overflow */ 177 #define RNTPCO 0x08 /* Runt Packet Count Overflow */ 178 #define MPCO 0x04 /* Missed Packet Count Overflow */ 179 #define RCVINT 0x02 /* Receive Interrupt */ 180 #define XMTINT 0x01 /* Transmit Interrupt */ 181 182 /* 9: Interrut Mask Register (IMR) */ 183 #define JABM 0x80 /* Jabber Error Mask */ 184 #define BABLM 0x40 /* Babble Error Mask */ 185 #define CERRM 0x20 /* Collision Error Mask */ 186 #define RCVCCOM 0x10 /* Receive Collision Count Overflow Mask */ 187 #define RNTPCOM 0x08 /* Runt Packet Count Overflow Mask */ 188 #define MPCOM 0x04 /* Missed Packet Count Overflow Mask */ 189 #define RCVINTM 0x02 /* Receive Interrupt Mask */ 190 #define XMTINTM 0x01 /* Transmit Interrupt Mask */ 191 192 /* 10: Poll Register (PR) */ 193 #define XMTSV 0x80 /* Transmit Status Valid */ 194 #define TDTREQ 0x40 /* Transmit Data Transfer Request */ 195 #define RDTREQ 0x20 /* Receive Data Transfer Request */ 196 197 /* 11: BIU Configuration Control (BIUCC) */ 198 #define BSWP 0x40 /* Byte Swap */ 199 #define XMTSP 0x30 /* Transmit Start Point */ 200 #define XMTSP_4 0x00 /* 4 bytes */ 201 #define XMTSP_16 0x10 /* 16 bytes */ 202 #define XMTSP_64 0x20 /* 64 bytes */ 203 #define XMTSP_112 0x30 /* 112 bytes */ 204 #define SWRST 0x01 /* Software Reset */ 205 206 /* 12: FIFO Configuration Control (FIFOCC) */ 207 #define XMTFW 0xc0 /* Transmit FIFO Watermark */ 208 #define XMTFW_8 0x00 /* 8 write cycles */ 209 #define XMTFW_16 0x40 /* 16 write cycles */ 210 #define XMTFW_32 0x80 /* 32 write cycles */ 211 #define RCVFW 0x30 /* Receive FIFO Watermark */ 212 #define RCVFW_16 0x00 /* 16 bytes */ 213 #define RCVFW_32 0x10 /* 32 bytes */ 214 #define RCVFW_64 0x20 /* 64 bytes */ 215 #define XMTFWU 0x08 /* Transmit FIFO Watermark Update */ 216 #define RCVFWU 0x04 /* Receive FIFO Watermark Update */ 217 #define XMTBRST 0x02 /* Transmit Burst */ 218 #define RCVBRST 0x01 /* Receive Burst */ 219 220 /* 13: MAC Configuration (MACCC) */ 221 #define PROM 0x80 /* Promiscuous */ 222 #define DXMT2PD 0x40 /* Disable Transmit Two Part Deferral */ 223 #define EMBA 0x20 /* Enable Modified Back-off Algorithm */ 224 #define DRCVPA 0x08 /* Disable Receive Physical Address */ 225 #define DRCVBC 0x04 /* Disable Receive Broadcast */ 226 #define ENXMT 0x02 /* Enable Transmit */ 227 #define ENRCV 0x01 /* Enable Receive */ 228 229 /* 14: PLS Configuration Control (PLSCC) */ 230 #define XMTSEL 0x08 /* Transmit Mode Select */ 231 #define PORTSEL 0x06 /* Port Select */ 232 #define PORTSEL_AUI 0x00 /* Select AUI */ 233 #define PORTSEL_10BT 0x02 /* Select 10BASE-T */ 234 #define PORTSEL_DAI 0x04 /* Select DAI port */ 235 #define PORTSEL_GPSI 0x06 /* Select GPSI */ 236 #define ENPLSIO 0x01 /* Enable PLS I/O */ 237 238 /* 15: PHY Configuration (PHYCC) */ 239 #define LNKFL 0x80 /* Link Fail */ 240 #define DLNKTST 0x40 /* Disable Link Test */ 241 #define REVPOL 0x20 /* Reversed Polarity */ 242 #define DAPC 0x10 /* Disable Auto Polarity Correction */ 243 #define LRT 0x08 /* Low Receive Threshold */ 244 #define ASEL 0x04 /* Auto Select */ 245 #define RWAKE 0x02 /* Remote Wake */ 246 #define AWAKE 0x01 /* Auto Wake */ 247 248 /* 18: Internal Address Configuration (IAC) */ 249 #define ADDRCHG 0x80 /* Address Change */ 250 #define PHYADDR 0x04 /* Physical Address Reset */ 251 #define LOGADDR 0x02 /* Logical Address Reset */ 252 253 /* 28: User Test Register (UTR) */ 254 #define RTRE 0x80 /* Reserved Test Register Enable */ 255 #define RTRD 0x40 /* Reserved Test Register Disable */ 256 #define RPA 0x20 /* Run Packet Accept */ 257 #define FCOLL 0x10 /* Force Collision */ 258 #define RCVFCSE 0x08 /* Receive FCS Enable */ 259 #define LOOP 0x06 /* Loopback Control */ 260 #define LOOP_NONE 0x00 /* No Loopback */ 261 #define LOOP_EXT 0x02 /* External Loopback */ 262 #define LOOP_INT 0x04 /* Internal Loopback, excludes MENDEC */ 263 #define LOOP_INT_MENDEC 0x06 /* Internal Loopback, includes MENDEC */ 264 265 struct mc_rxframe { 266 u_int8_t rx_rcvcnt; 267 u_int8_t rx_rcvsts; 268 u_int8_t rx_rntpc; 269 u_int8_t rx_rcvcc; 270 u_char *rx_frame; 271 }; 272 273 struct mc_softc { 274 struct device sc_dev; /* base device glue */ 275 struct arpcom sc_arpcom; /* Ethernet common part */ 276 struct timeout sc_tick_ch; 277 278 struct mc_rxframe sc_rxframe; 279 u_int8_t sc_biucc; 280 u_int8_t sc_fifocc; 281 u_int8_t sc_plscc; 282 u_int8_t sc_enaddr[6]; 283 u_int8_t sc_pad[2]; 284 int sc_havecarrier; /* carrier status */ 285 286 char *sc_reg; 287 bus_dma_tag_t sc_dmat; 288 bus_dmamap_t sc_bufmap; 289 bus_dma_segment_t sc_bufseg[1]; 290 291 dbdma_regmap_t *sc_txdma; 292 dbdma_regmap_t *sc_rxdma; 293 dbdma_command_t *sc_txdmacmd; 294 dbdma_command_t *sc_rxdmacmd; 295 dbdma_t sc_txdbdma; 296 dbdma_t sc_rxdbdma; 297 298 caddr_t sc_txbuf; 299 caddr_t sc_rxbuf; 300 paddr_t sc_txbuf_pa; 301 paddr_t sc_rxbuf_pa; 302 int sc_tail; 303 int sc_rxset; 304 int sc_txset; 305 int sc_txseti; 306 }; 307 308 int mc_match(struct device *, void *, void *); 309 void mc_attach(struct device *, struct device *, void *); 310 311 struct cfattach mc_ca = { 312 sizeof(struct mc_softc), mc_match, mc_attach 313 }; 314 315 struct cfdriver mc_cd = { 316 NULL, "mc", DV_IFNET 317 }; 318 319 void mc_init(struct mc_softc *sc); 320 void mc_put(struct mc_softc *sc, u_int len); 321 int mc_dmaintr(void *arg); 322 void mc_reset_rxdma(struct mc_softc *sc); 323 void mc_reset_txdma(struct mc_softc *sc); 324 int mc_stop(struct mc_softc *sc); 325 int mc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 326 void mc_start(struct ifnet *ifp); 327 void mc_reset(struct mc_softc *sc); 328 void mc_tint(struct mc_softc *sc); 329 void mc_rint(struct mc_softc *sc); 330 int mc_intr(void *); 331 void mc_watchdog(struct ifnet *ifp); 332 333 u_int maceput(struct mc_softc *sc, struct mbuf *); 334 void mace_read(struct mc_softc *, caddr_t, int); 335 struct mbuf *mace_get(struct mc_softc *, caddr_t, int); 336 static void mace_calcladrf(struct mc_softc *, u_int8_t *); 337 void mc_putpacket(struct mc_softc *, u_int); 338 339 int 340 mc_match(struct device *parent, void *arg, void *aux) 341 { 342 struct confargs *ca = aux; 343 344 if (strcmp(ca->ca_name, "mace") != 0) 345 return 0; 346 347 /* requires 6 regs */ 348 if (ca->ca_nreg / sizeof(int) != 6) 349 return 0; 350 351 /* requires 3 intrs */ 352 if (ca->ca_nintr / sizeof(int) != 3) 353 return 0; 354 355 return 1; 356 } 357 358 void 359 mc_attach(struct device *parent, struct device *self, void *aux) 360 { 361 struct confargs *ca = aux; 362 struct mc_softc *sc = (struct mc_softc *)self; 363 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 364 u_int8_t lladdr[ETHER_ADDR_LEN]; 365 int nseg, error; 366 367 if (OF_getprop(ca->ca_node, "local-mac-address", lladdr, 368 ETHER_ADDR_LEN) != ETHER_ADDR_LEN) { 369 printf(": failed to get MAC address.\n"); 370 return; 371 } 372 373 ca->ca_reg[0] += ca->ca_baseaddr; 374 ca->ca_reg[2] += ca->ca_baseaddr; 375 ca->ca_reg[4] += ca->ca_baseaddr; 376 377 if ((sc->sc_reg = mapiodev(ca->ca_reg[0], ca->ca_reg[1])) == NULL) { 378 printf(": cannot map registers\n"); 379 return; 380 } 381 382 sc->sc_dmat = ca->ca_dmat; 383 sc->sc_tail = 0; 384 385 if ((sc->sc_txdma = mapiodev(ca->ca_reg[2], ca->ca_reg[3])) == NULL) { 386 printf(": cannot map TX DMA registers\n"); 387 goto notxdma; 388 } 389 if ((sc->sc_rxdma = mapiodev(ca->ca_reg[4], ca->ca_reg[5])) == NULL) { 390 printf(": cannot map RX DMA registers\n"); 391 goto norxdma; 392 } 393 if ((sc->sc_txdbdma = dbdma_alloc(sc->sc_dmat, 2)) == NULL) { 394 printf(": cannot alloc TX DMA descriptors\n"); 395 goto notxdbdma; 396 } 397 sc->sc_txdmacmd = sc->sc_txdbdma->d_addr; 398 399 if ((sc->sc_rxdbdma = dbdma_alloc(sc->sc_dmat, 8 + 1)) == NULL) { 400 printf(": cannot alloc RX DMA descriptors\n"); 401 goto norxdbdma; 402 } 403 sc->sc_rxdmacmd = sc->sc_rxdbdma->d_addr; 404 405 if ((error = bus_dmamem_alloc(sc->sc_dmat, MACE_BUFSZ, PAGE_SIZE, 0, 406 sc->sc_bufseg, 1, &nseg, BUS_DMA_NOWAIT))) { 407 printf(": cannot allocate DMA mem (%d)\n", error); 408 goto nodmamem; 409 } 410 411 if ((error = bus_dmamem_map(sc->sc_dmat, sc->sc_bufseg, nseg, 412 MACE_BUFSZ, &sc->sc_txbuf, BUS_DMA_NOWAIT))) { 413 printf(": cannot map DMA mem (%d)\n", error); 414 goto nodmamap; 415 } 416 417 if ((error = bus_dmamap_create(sc->sc_dmat, MACE_BUFSZ, 1, MACE_BUFSZ, 418 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_bufmap))) { 419 printf(": cannot create DMA map (%d)\n", error); 420 goto nodmacreate; 421 } 422 423 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_bufmap, sc->sc_txbuf, 424 MACE_BUFSZ, NULL, BUS_DMA_NOWAIT))) { 425 printf(": cannot load DMA map (%d)\n", error); 426 goto nodmaload; 427 } 428 429 sc->sc_txbuf_pa = sc->sc_bufmap->dm_segs->ds_addr; 430 sc->sc_rxbuf = sc->sc_txbuf + MACE_BUFLEN * MACE_TXBUFS; 431 sc->sc_rxbuf_pa = sc->sc_txbuf_pa + MACE_BUFLEN * MACE_TXBUFS; 432 433 printf(": irq %d,%d,%d", ca->ca_intr[0], ca->ca_intr[1], 434 ca->ca_intr[2]); 435 436 /* disable receive DMA */ 437 dbdma_reset(sc->sc_rxdma); 438 439 /* disable transmit DMA */ 440 dbdma_reset(sc->sc_txdma); 441 442 /* install interrupt handlers */ 443 mac_intr_establish(parent, ca->ca_intr[2], IST_LEVEL, IPL_NET, 444 mc_dmaintr, sc, sc->sc_dev.dv_xname); 445 mac_intr_establish(parent, ca->ca_intr[0], IST_LEVEL, IPL_NET, 446 mc_intr, sc, sc->sc_dev.dv_xname); 447 448 sc->sc_biucc = XMTSP_64; 449 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | 450 XMTBRST | RCVBRST; 451 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 452 453 /* reset the chip and disable all interrupts */ 454 NIC_PUT(sc, MACE_BIUCC, SWRST); 455 DELAY(100); 456 457 NIC_PUT(sc, MACE_IMR, ~0); 458 459 bcopy(lladdr, sc->sc_enaddr, ETHER_ADDR_LEN); 460 bcopy(sc->sc_enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 461 printf(": address %s\n", ether_sprintf(lladdr)); 462 463 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 464 ifp->if_softc = sc; 465 ifp->if_ioctl = mc_ioctl; 466 ifp->if_start = mc_start; 467 ifp->if_flags = 468 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 469 ifp->if_watchdog = mc_watchdog; 470 ifp->if_timer = 0; 471 IFQ_SET_READY(&ifp->if_snd); 472 473 if_attach(ifp); 474 ether_ifattach(ifp); 475 476 return; 477 nodmaload: 478 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bufmap); 479 nodmacreate: 480 bus_dmamem_unmap(sc->sc_dmat, sc->sc_txbuf, MACE_BUFSZ); 481 nodmamap: 482 bus_dmamem_free(sc->sc_dmat, sc->sc_bufseg, 1); 483 nodmamem: 484 dbdma_free(sc->sc_rxdbdma); 485 norxdbdma: 486 dbdma_free(sc->sc_txdbdma); 487 notxdbdma: 488 unmapiodev((void *)sc->sc_rxdma, ca->ca_reg[5]); 489 norxdma: 490 unmapiodev((void *)sc->sc_txdma, ca->ca_reg[3]); 491 notxdma: 492 unmapiodev(sc->sc_reg, ca->ca_reg[1]); 493 } 494 495 int 496 mc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 497 { 498 struct mc_softc *sc = ifp->if_softc; 499 struct ifaddr *ifa = (struct ifaddr *)data; 500 int s, err = 0; 501 502 s = splnet(); 503 504 switch (cmd) { 505 case SIOCSIFADDR: 506 ifp->if_flags |= IFF_UP; 507 if (!(ifp->if_flags & IFF_RUNNING)) 508 mc_init(sc); 509 #ifdef INET 510 if (ifa->ifa_addr->sa_family == AF_INET) 511 arp_ifinit(&sc->sc_arpcom, ifa); 512 #endif 513 break; 514 515 case SIOCSIFFLAGS: 516 if ((ifp->if_flags & IFF_UP) == 0 && 517 (ifp->if_flags & IFF_RUNNING) != 0) { 518 /* 519 * If interface is marked down and it is running, 520 * then stop it. 521 */ 522 mc_stop(sc); 523 } else if ((ifp->if_flags & IFF_UP) != 0 && 524 (ifp->if_flags & IFF_RUNNING) == 0) { 525 /* 526 * If interface is marked up and it is stopped, 527 * then start it. 528 */ 529 mc_init(sc); 530 } else { 531 /* 532 * reset the interface to pick up any other changes 533 * in flags 534 */ 535 mc_reset(sc); 536 mc_start(ifp); 537 } 538 break; 539 540 default: 541 err = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 542 } 543 544 if (err == ENETRESET) { 545 if (ifp->if_flags & IFF_RUNNING) 546 mc_reset(sc); 547 err = 0; 548 } 549 550 splx(s); 551 return (err); 552 } 553 554 /* 555 * Encapsulate a packet of type family for the local net. 556 */ 557 void 558 mc_start(struct ifnet *ifp) 559 { 560 struct mc_softc *sc = ifp->if_softc; 561 struct mbuf *m; 562 563 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 564 return; 565 566 while (1) { 567 if (ifp->if_flags & IFF_OACTIVE) 568 return; 569 570 IFQ_DEQUEUE(&ifp->if_snd, m); 571 if (m == NULL) 572 return; 573 574 #if NBPFILTER > 0 575 /* 576 * If bpf is listening on this interface, let it 577 * see the packet before we commit it to the wire. 578 */ 579 if (ifp->if_bpf) 580 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 581 #endif 582 583 /* 584 * Copy the mbuf chain into the transmit buffer. 585 */ 586 ifp->if_flags |= IFF_OACTIVE; 587 maceput(sc, m); 588 589 ifp->if_opackets++; /* # of pkts */ 590 } 591 } 592 593 /* 594 * reset and restart the MACE. Called in case of fatal 595 * hardware/software errors. 596 */ 597 void 598 mc_reset(struct mc_softc *sc) 599 { 600 mc_stop(sc); 601 mc_init(sc); 602 } 603 604 void 605 mc_init(struct mc_softc *sc) 606 { 607 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 608 u_int8_t maccc, ladrf[8]; 609 int s, i; 610 611 s = splnet(); 612 613 NIC_PUT(sc, MACE_BIUCC, sc->sc_biucc); 614 NIC_PUT(sc, MACE_FIFOCC, sc->sc_fifocc); 615 NIC_PUT(sc, MACE_IMR, ~0); /* disable all interrupts */ 616 NIC_PUT(sc, MACE_PLSCC, sc->sc_plscc); 617 618 NIC_PUT(sc, MACE_UTR, RTRD); /* disable reserved test registers */ 619 620 /* set MAC address */ 621 NIC_PUT(sc, MACE_IAC, ADDRCHG); 622 while (NIC_GET(sc, MACE_IAC) & ADDRCHG) 623 ; 624 NIC_PUT(sc, MACE_IAC, PHYADDR); 625 for (i = 0; i < ETHER_ADDR_LEN; i++) 626 out8rb(sc->sc_reg + MACE_REG(MACE_PADR) + i, 627 sc->sc_enaddr[i]); 628 629 /* set logical address filter */ 630 mace_calcladrf(sc, ladrf); 631 632 NIC_PUT(sc, MACE_IAC, ADDRCHG); 633 while (NIC_GET(sc, MACE_IAC) & ADDRCHG) 634 ; 635 NIC_PUT(sc, MACE_IAC, LOGADDR); 636 for (i = 0; i < 8; i++) 637 out8rb(sc->sc_reg + MACE_REG(MACE_LADRF) + i, 638 ladrf[i]); 639 640 NIC_PUT(sc, MACE_XMTFC, APADXMT); 641 /* 642 * No need to autostrip padding on receive... Ethernet frames 643 * don't have a length field, unlike 802.3 frames, so the MACE 644 * can't figure out the length of the packet anyways. 645 */ 646 NIC_PUT(sc, MACE_RCVFC, 0); 647 648 maccc = ENXMT | ENRCV; 649 if (ifp->if_flags & IFF_PROMISC) 650 maccc |= PROM; 651 652 NIC_PUT(sc, MACE_MACCC, maccc); 653 654 mc_reset_rxdma(sc); 655 mc_reset_txdma(sc); 656 /* 657 * Enable all interrupts except receive, since we use the DMA 658 * completion interrupt for that. 659 */ 660 NIC_PUT(sc, MACE_IMR, RCVINTM); 661 662 /* flag interface as "running" */ 663 ifp->if_flags |= IFF_RUNNING; 664 ifp->if_flags &= ~IFF_OACTIVE; 665 666 splx(s); 667 } 668 669 /* 670 * Close down an interface and free its buffers. 671 * Called on final close of device, or if mcinit() fails 672 * part way through. 673 */ 674 int 675 mc_stop(struct mc_softc *sc) 676 { 677 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 678 int s; 679 680 s = splnet(); 681 682 NIC_PUT(sc, MACE_BIUCC, SWRST); 683 DELAY(100); 684 685 ifp->if_timer = 0; 686 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 687 688 splx(s); 689 return (0); 690 } 691 692 /* 693 * Called if any Tx packets remain unsent after 5 seconds, 694 * In all cases we just reset the chip, and any retransmission 695 * will be handled by higher level protocol timeouts. 696 */ 697 void 698 mc_watchdog(struct ifnet *ifp) 699 { 700 struct mc_softc *sc = ifp->if_softc; 701 702 printf("mcwatchdog: resetting chip\n"); 703 mc_reset(sc); 704 } 705 706 int 707 mc_intr(void *arg) 708 { 709 struct mc_softc *sc = arg; 710 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 711 u_int8_t ir; 712 713 ir = NIC_GET(sc, MACE_IR) & ~NIC_GET(sc, MACE_IMR); 714 715 if (ir & JAB) { 716 #ifdef MCDEBUG 717 printf("%s: jabber error\n", sc->sc_dev.dv_xname); 718 #endif 719 ifp->if_oerrors++; 720 } 721 722 if (ir & BABL) { 723 #ifdef MCDEBUG 724 printf("%s: babble\n", sc->sc_dev.dv_xname); 725 #endif 726 ifp->if_oerrors++; 727 } 728 729 if (ir & CERR) { 730 #ifdef MCDEBUG 731 printf("%s: collision error\n", sc->sc_dev.dv_xname); 732 #endif 733 ifp->if_collisions++; 734 } 735 736 /* 737 * Pretend we have carrier; if we don't this will be cleared 738 * shortly. 739 */ 740 sc->sc_havecarrier = 1; 741 742 if (ir & XMTINT) 743 mc_tint(sc); 744 745 if (ir & RCVINT) 746 mc_rint(sc); 747 748 return(1); 749 } 750 751 void 752 mc_tint(struct mc_softc *sc) 753 { 754 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 755 u_int8_t xmtrc, xmtfs; 756 757 xmtrc = NIC_GET(sc, MACE_XMTRC); 758 xmtfs = NIC_GET(sc, MACE_XMTFS); 759 760 if ((xmtfs & XMTSV) == 0) 761 return; 762 763 if (xmtfs & UFLO) { 764 printf("%s: underflow\n", sc->sc_dev.dv_xname); 765 mc_reset(sc); 766 return; 767 } 768 769 if (xmtfs & LCOL) { 770 printf("%s: late collision\n", sc->sc_dev.dv_xname); 771 ifp->if_oerrors++; 772 ifp->if_collisions++; 773 } 774 775 if (xmtfs & MORE) 776 /* Real number is unknown. */ 777 ifp->if_collisions += 2; 778 else if (xmtfs & ONE) 779 ifp->if_collisions++; 780 else if (xmtfs & RTRY) { 781 printf("%s: excessive collisions\n", sc->sc_dev.dv_xname); 782 ifp->if_collisions += 16; 783 ifp->if_oerrors++; 784 } 785 786 if (xmtfs & LCAR) { 787 sc->sc_havecarrier = 0; 788 printf("%s: lost carrier\n", sc->sc_dev.dv_xname); 789 ifp->if_oerrors++; 790 } 791 792 ifp->if_flags &= ~IFF_OACTIVE; 793 ifp->if_timer = 0; 794 mc_start(ifp); 795 } 796 797 void 798 mc_rint(struct mc_softc *sc) 799 { 800 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 801 #define rxf sc->sc_rxframe 802 u_int len; 803 804 len = (rxf.rx_rcvcnt | ((rxf.rx_rcvsts & 0xf) << 8)) - 4; 805 806 #ifdef MCDEBUG 807 if (rxf.rx_rcvsts & 0xf0) 808 printf("%s: rcvcnt %02x rcvsts %02x rntpc 0x%02x rcvcc 0x%02x\n", 809 sc->sc_dev.dv_xname, rxf.rx_rcvcnt, rxf.rx_rcvsts, 810 rxf.rx_rntpc, rxf.rx_rcvcc); 811 #endif 812 813 if (rxf.rx_rcvsts & OFLO) { 814 #ifdef MCDEBUG 815 printf("%s: receive FIFO overflow\n", sc->sc_dev.dv_xname); 816 #endif 817 ifp->if_ierrors++; 818 return; 819 } 820 821 if (rxf.rx_rcvsts & CLSN) 822 ifp->if_collisions++; 823 824 if (rxf.rx_rcvsts & FRAM) { 825 #ifdef MCDEBUG 826 printf("%s: framing error\n", sc->sc_dev.dv_xname); 827 #endif 828 ifp->if_ierrors++; 829 return; 830 } 831 832 if (rxf.rx_rcvsts & FCS) { 833 #ifdef MCDEBUG 834 printf("%s: frame control checksum error\n", sc->sc_dev.dv_xname); 835 #endif 836 ifp->if_ierrors++; 837 return; 838 } 839 840 mace_read(sc, rxf.rx_frame, len); 841 #undef rxf 842 } 843 /* 844 * stuff packet into MACE (at splnet) 845 */ 846 u_int 847 maceput(struct mc_softc *sc, struct mbuf *m) 848 { 849 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 850 struct mbuf *n; 851 u_int len, totlen = 0; 852 u_char *buff; 853 854 buff = sc->sc_txbuf; 855 856 for (; m; m = n) { 857 u_char *data = mtod(m, u_char *); 858 len = m->m_len; 859 totlen += len; 860 bcopy(data, buff, len); 861 buff += len; 862 MFREE(m, n); 863 } 864 865 if (totlen > PAGE_SIZE) 866 panic("%s: maceput: packet overflow", sc->sc_dev.dv_xname); 867 868 #if 0 869 if (totlen < ETHERMIN + sizeof(struct ether_header)) { 870 int pad = ETHERMIN + sizeof(struct ether_header) - totlen; 871 bzero(sc->sc_txbuf + totlen, pad); 872 totlen = ETHERMIN + sizeof(struct ether_header); 873 } 874 #endif 875 876 877 /* 5 seconds to watch for failing to transmit */ 878 ifp->if_timer = 5; 879 mc_putpacket(sc, totlen); 880 return (totlen); 881 } 882 883 void 884 mace_read(struct mc_softc *sc, caddr_t pkt, int len) 885 { 886 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 887 struct mbuf *m; 888 889 if (len <= sizeof(struct ether_header) || 890 len > ETHERMTU + sizeof(struct ether_header)) { 891 #ifdef MCDEBUG 892 printf("%s: invalid packet size %d; dropping\n", 893 sc->sc_dev.dv_xname, len); 894 #endif 895 ifp->if_ierrors++; 896 return; 897 } 898 899 m = mace_get(sc, pkt, len); 900 if (m == NULL) { 901 ifp->if_ierrors++; 902 return; 903 } 904 905 ifp->if_ipackets++; 906 907 #if NBPFILTER > 0 908 /* Pass the packet to any BPF listeners. */ 909 if (ifp->if_bpf) 910 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 911 #endif 912 913 /* Pass the packet up. */ 914 ether_input_mbuf(ifp, m); 915 } 916 917 /* 918 * Pull data off an interface. 919 * Len is length of data, with local net header stripped. 920 * We copy the data into mbufs. When full cluster sized units are present 921 * we copy into clusters. 922 */ 923 struct mbuf * 924 mace_get(struct mc_softc *sc, caddr_t pkt, int totlen) 925 { 926 struct mbuf *m; 927 struct mbuf *top, **mp; 928 int len; 929 930 MGETHDR(m, M_DONTWAIT, MT_DATA); 931 if (m == NULL) 932 return (NULL); 933 934 m->m_pkthdr.rcvif = &sc->sc_arpcom.ac_if; 935 m->m_pkthdr.len = totlen; 936 len = MHLEN; 937 top = 0; 938 mp = ⊤ 939 940 while (totlen > 0) { 941 if (top) { 942 MGET(m, M_DONTWAIT, MT_DATA); 943 if (m == NULL) { 944 m_freem(top); 945 return (NULL); 946 } 947 len = MLEN; 948 } 949 if (totlen >= MINCLSIZE) { 950 MCLGET(m, M_DONTWAIT); 951 if ((m->m_flags & M_EXT) == 0) { 952 m_free(m); 953 m_freem(top); 954 return (NULL); 955 } 956 len = MCLBYTES; 957 } 958 m->m_len = len = min(totlen, len); 959 bcopy(pkt, mtod(m, caddr_t), len); 960 pkt += len; 961 totlen -= len; 962 *mp = m; 963 mp = &m->m_next; 964 } 965 966 return (top); 967 } 968 969 void 970 mc_putpacket(struct mc_softc *sc, u_int len) 971 { 972 dbdma_command_t *cmd = sc->sc_txdmacmd; 973 974 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, sc->sc_txbuf_pa, 975 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 976 cmd++; 977 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, DBDMA_INT_ALWAYS, 978 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 979 980 dbdma_start(sc->sc_txdma, sc->sc_txdbdma); 981 } 982 983 /* 984 * Interrupt handler for the MACE DMA completion interrupts 985 */ 986 int 987 mc_dmaintr(void *arg) 988 { 989 struct mc_softc *sc = arg; 990 int status, offset, statoff; 991 int datalen, resid; 992 int i, n, count; 993 dbdma_command_t *cmd; 994 995 /* We've received some packets from the MACE */ 996 /* Loop through, processing each of the packets */ 997 i = sc->sc_tail; 998 for (n = 0; n < MC_RXDMABUFS; n++, i++) { 999 if (i == MC_RXDMABUFS) 1000 i = 0; 1001 1002 cmd = &sc->sc_rxdmacmd[i]; 1003 status = dbdma_ld16(&cmd->d_status); 1004 resid = dbdma_ld16(&cmd->d_resid); 1005 1006 if ((status & DBDMA_CNTRL_ACTIVE) == 0) { 1007 continue; 1008 } 1009 1010 count = dbdma_ld16(&cmd->d_count); 1011 datalen = count - resid; 1012 datalen -= 4; /* 4 == status bytes */ 1013 1014 if (datalen < 4 + sizeof(struct ether_header)) { 1015 printf("short packet len=%d\n", datalen); 1016 /* continue; */ 1017 goto next; 1018 } 1019 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0); 1020 1021 offset = i * MACE_BUFLEN; 1022 statoff = offset + datalen; 1023 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[statoff + 0]; 1024 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[statoff + 1]; 1025 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[statoff + 2]; 1026 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[statoff + 3]; 1027 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset; 1028 1029 mc_rint(sc); 1030 1031 next: 1032 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS, 1033 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 1034 1035 cmd->d_status = 0; 1036 cmd->d_resid = 0; 1037 sc->sc_tail = i + 1; 1038 } 1039 1040 dbdma_continue(sc->sc_rxdma); 1041 1042 return 1; 1043 } 1044 1045 void 1046 mc_reset_rxdma(struct mc_softc *sc) 1047 { 1048 dbdma_command_t *cmd = sc->sc_rxdmacmd; 1049 int i; 1050 u_int8_t maccc; 1051 1052 /* Disable receiver, reset the DMA channels */ 1053 maccc = NIC_GET(sc, MACE_MACCC); 1054 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV); 1055 1056 dbdma_reset(sc->sc_rxdma); 1057 1058 bzero(sc->sc_rxdmacmd, 8 * sizeof(dbdma_command_t)); 1059 for (i = 0; i < MC_RXDMABUFS; i++) { 1060 DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, MACE_BUFLEN, 1061 sc->sc_rxbuf_pa + MACE_BUFLEN * i, DBDMA_INT_ALWAYS, 1062 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 1063 cmd++; 1064 } 1065 1066 DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0, 1067 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS); 1068 dbdma_st32(&cmd->d_cmddep, sc->sc_rxdbdma->d_paddr); 1069 cmd++; 1070 1071 sc->sc_tail = 0; 1072 1073 dbdma_start(sc->sc_rxdma, sc->sc_rxdbdma); 1074 /* Reenable receiver, reenable DMA */ 1075 NIC_PUT(sc, MACE_MACCC, maccc); 1076 } 1077 1078 void 1079 mc_reset_txdma(struct mc_softc *sc) 1080 { 1081 dbdma_command_t *cmd = sc->sc_txdmacmd; 1082 dbdma_regmap_t *dmareg = sc->sc_txdma; 1083 u_int8_t maccc; 1084 1085 /* disable transmitter */ 1086 maccc = NIC_GET(sc, MACE_MACCC); 1087 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT); 1088 1089 dbdma_reset(sc->sc_txdma); 1090 1091 bzero(sc->sc_txdmacmd, 2 * sizeof(dbdma_command_t)); 1092 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, 0, sc->sc_txbuf_pa, 1093 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 1094 cmd++; 1095 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 1096 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 1097 1098 out32rb(&dmareg->d_cmdptrhi, 0); 1099 out32rb(&dmareg->d_cmdptrlo, sc->sc_txdbdma->d_paddr); 1100 1101 /* restore old value */ 1102 NIC_PUT(sc, MACE_MACCC, maccc); 1103 } 1104 1105 /* 1106 * Go through the list of multicast addresses and calculate the logical 1107 * address filter. 1108 */ 1109 void 1110 mace_calcladrf(struct mc_softc *sc, u_int8_t *af) 1111 { 1112 struct ether_multi *enm; 1113 u_int32_t crc; 1114 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1115 struct arpcom *ac = &sc->sc_arpcom; 1116 struct ether_multistep step; 1117 /* 1118 * Set up multicast address filter by passing all multicast addresses 1119 * through a crc generator, and then using the high order 6 bits as an 1120 * index into the 64 bit logical address filter. The high order bit 1121 * selects the word, while the rest of the bits select the bit within 1122 * the word. 1123 */ 1124 1125 *((u_int32_t *)af) = *((u_int32_t *)af + 1) = 0; 1126 ETHER_FIRST_MULTI(step, ac, enm); 1127 while (enm != NULL) { 1128 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1129 /* 1130 * We must listen to a range of multicast addresses. 1131 * For now, just accept all multicasts, rather than 1132 * trying to set only those filter bits needed to match 1133 * the range. (At this time, the only use of address 1134 * ranges is for IP multicast routing, for which the 1135 * range is big enough to require all bits set.) 1136 */ 1137 goto allmulti; 1138 } 1139 1140 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1141 1142 /* Just want the 6 most significant bits. */ 1143 crc >>= 26; 1144 1145 /* Set the corresponding bit in the filter. */ 1146 af[crc >> 3] |= 1 << (crc & 7); 1147 1148 ETHER_NEXT_MULTI(step, enm); 1149 } 1150 ifp->if_flags &= ~IFF_ALLMULTI; 1151 return; 1152 1153 allmulti: 1154 ifp->if_flags |= IFF_ALLMULTI; 1155 *((u_int32_t *)af) = *((u_int32_t *)af + 1) = 0xffffffff; 1156 } 1157