1 /* $OpenBSD: if_mc.c,v 1.13 2008/11/28 02:44:17 brad Exp $ */ 2 /* $NetBSD: if_mc.c,v 1.9.16.1 2006/06/21 14:53:13 yamt Exp $ */ 3 4 /*- 5 * Copyright (c) 1997 David Huang <khym@bga.com> 6 * All rights reserved. 7 * 8 * Portions of this code are based on code by Denton Gentry <denny1@home.com> 9 * and Yanagisawa Takeshi <yanagisw@aa.ap.titech.ac.jp>. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * AMD AM79C940 (MACE) driver with DBDMA bus attachment and DMA routines 34 * for onboard ethernet found on most old world macs. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/buf.h> 41 #include <sys/protosw.h> 42 #include <sys/socket.h> 43 #include <sys/syslog.h> 44 #include <sys/ioctl.h> 45 #include <sys/errno.h> 46 #include <sys/device.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #ifdef INET 55 #include <netinet/in.h> 56 #include <netinet/if_ether.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #endif 61 62 #include "bpfilter.h" 63 #if NBPFILTER > 0 64 #include <net/bpf.h> 65 #include <net/bpfdesc.h> 66 #endif 67 68 #include <dev/ofw/openfirm.h> 69 #include <machine/pio.h> 70 #include <machine/bus.h> 71 #include <machine/autoconf.h> 72 73 #include <macppc/dev/dbdma.h> 74 75 #define MC_REGSPACING 16 76 #define MC_REGSIZE MACE_NREGS * MC_REGSPACING 77 #define MACE_REG(x) ((x)*MC_REGSPACING) 78 #define MACE_BUFLEN 2048 79 #define MACE_TXBUFS 2 80 #define MACE_RXBUFS 8 81 82 #define MC_RXDMABUFS 4 83 84 #define MACE_BUFSZ ((MACE_RXBUFS + MACE_TXBUFS + 2) * MACE_BUFLEN) 85 86 #define NIC_GET(sc, reg) (in8rb(sc->sc_reg + MACE_REG(reg))) 87 88 #define NIC_PUT(sc, reg, val) (out8rb(sc->sc_reg + MACE_REG(reg), (val))) 89 90 /* 91 * AMD MACE (Am79C940) register definitions 92 */ 93 #define MACE_RCVFIFO 0 /* Receive FIFO [15-00] (read only) */ 94 #define MACE_XMTFIFO 1 /* Transmit FIFO [15-00] (write only) */ 95 #define MACE_XMTFC 2 /* Transmit Frame Control (read/write) */ 96 #define MACE_XMTFS 3 /* Transmit Frame Status (read only) */ 97 #define MACE_XMTRC 4 /* Transmit Retry Count (read only) */ 98 #define MACE_RCVFC 5 /* Receive Frame Control (read/write) */ 99 #define MACE_RCVFS 6 /* Receive Frame Status (4 bytes) (read only) */ 100 #define MACE_FIFOFC 7 /* FIFO Frame Count (read only) */ 101 #define MACE_IR 8 /* Interrupt Register (read only) */ 102 #define MACE_IMR 9 /* Interrupt Mask Register (read/write) */ 103 #define MACE_PR 10 /* Poll Register (read only) */ 104 #define MACE_BIUCC 11 /* BIU Configuration Control (read/write) */ 105 #define MACE_FIFOCC 12 /* FIFO Configuration Control (read/write) */ 106 #define MACE_MACCC 13 /* MAC Configuration Control (read/write) */ 107 #define MACE_PLSCC 14 /* PLS Configuration Control (read/write) */ 108 #define MACE_PHYCC 15 /* PHY Confiuration Control (read/write) */ 109 #define MACE_CHIPIDL 16 /* Chip ID Register [07-00] (read only) */ 110 #define MACE_CHIPIDH 17 /* Chip ID Register [15-08] (read only) */ 111 #define MACE_IAC 18 /* Internal Address Configuration (read/write) */ 112 /* RESERVED 19 Reserved (read/write as 0) */ 113 #define MACE_LADRF 20 /* Logical Address Filter (8 bytes) (read/write) */ 114 #define MACE_PADR 21 /* Physical Address (6 bytes) (read/write) */ 115 /* RESERVED 22 Reserved (read/write as 0) */ 116 /* RESERVED 23 Reserved (read/write as 0) */ 117 #define MACE_MPC 24 /* Missed Packet Count (read only) */ 118 /* RESERVED 25 Reserved (read/write as 0) */ 119 #define MACE_RNTPC 26 /* Runt Packet Count (read only) */ 120 #define MACE_RCVCC 27 /* Receive Collision Count (read only) */ 121 /* RESERVED 28 Reserved (read/write as 0) */ 122 #define MACE_UTR 29 /* User Test Register (read/write) */ 123 #define MACE_RTR1 30 /* Reserved Test Register 1 (read/write as 0) */ 124 #define MACE_RTR2 31 /* Reserved Test Register 2 (read/write as 0) */ 125 126 #define MACE_NREGS 32 127 128 /* 2: Transmit Frame Control (XMTFC) */ 129 #define DRTRY 0x80 /* Disable Retry */ 130 #define DXMTFCS 0x08 /* Disable Transmit FCS */ 131 #define APADXMT 0x01 /* Auto Pad Transmit */ 132 133 /* 3: Transmit Frame Status (XMTFS) */ 134 #define XMTSV 0x80 /* Transmit Status Valid */ 135 #define UFLO 0x40 /* Underflow */ 136 #define LCOL 0x20 /* Late Collision */ 137 #define MORE 0x10 /* More than one retry needed */ 138 #define ONE 0x08 /* Exactly one retry needed */ 139 #define DEFER 0x04 /* Transmission deferred */ 140 #define LCAR 0x02 /* Loss of Carrier */ 141 #define RTRY 0x01 /* Retry Error */ 142 143 /* 4: Transmit Retry Count (XMTRC) */ 144 #define EXDEF 0x80 /* Excessive Defer */ 145 #define XMTRC 0x0f /* Transmit Retry Count */ 146 147 /* 5: Receive Frame Control (RCVFC) */ 148 #define LLRCV 0x08 /* Low Latency Receive */ 149 #define MR 0x04 /* Match/Reject */ 150 #define ASTRPRCV 0x01 /* Auto Strip Receive */ 151 152 /* 6: Receive Frame Status (RCVFS) */ 153 /* 4 byte register; read 4 times to get all of the bytes */ 154 /* Read 1: RFS0 - Receive Message Byte Count [7-0] (RCVCNT) */ 155 156 /* Read 2: RFS1 - Receive Status (RCVSTS) */ 157 #define OFLO 0x80 /* Overflow flag */ 158 #define CLSN 0x40 /* Collision flag */ 159 #define FRAM 0x20 /* Framing Error flag */ 160 #define FCS 0x10 /* FCS Error flag */ 161 #define RCVCNT 0x0f /* Receive Message Byte Count [11-8] */ 162 163 /* Read 3: RFS2 - Runt Packet Count (RNTPC) [7-0] */ 164 165 /* Read 4: RFS3 - Receive Collision Count (RCVCC) [7-0] */ 166 167 /* 7: FIFO Frame Count (FIFOFC) */ 168 #define RCVFC 0xf0 /* Receive Frame Count */ 169 #define XMTFC 0x0f /* Transmit Frame Count */ 170 171 /* 8: Interrupt Register (IR) */ 172 #define JAB 0x80 /* Jabber Error */ 173 #define BABL 0x40 /* Babble Error */ 174 #define CERR 0x20 /* Collision Error */ 175 #define RCVCCO 0x10 /* Receive Collision Count Overflow */ 176 #define RNTPCO 0x08 /* Runt Packet Count Overflow */ 177 #define MPCO 0x04 /* Missed Packet Count Overflow */ 178 #define RCVINT 0x02 /* Receive Interrupt */ 179 #define XMTINT 0x01 /* Transmit Interrupt */ 180 181 /* 9: Interrut Mask Register (IMR) */ 182 #define JABM 0x80 /* Jabber Error Mask */ 183 #define BABLM 0x40 /* Babble Error Mask */ 184 #define CERRM 0x20 /* Collision Error Mask */ 185 #define RCVCCOM 0x10 /* Receive Collision Count Overflow Mask */ 186 #define RNTPCOM 0x08 /* Runt Packet Count Overflow Mask */ 187 #define MPCOM 0x04 /* Missed Packet Count Overflow Mask */ 188 #define RCVINTM 0x02 /* Receive Interrupt Mask */ 189 #define XMTINTM 0x01 /* Transmit Interrupt Mask */ 190 191 /* 10: Poll Register (PR) */ 192 #define XMTSV 0x80 /* Transmit Status Valid */ 193 #define TDTREQ 0x40 /* Transmit Data Transfer Request */ 194 #define RDTREQ 0x20 /* Receive Data Transfer Request */ 195 196 /* 11: BIU Configuration Control (BIUCC) */ 197 #define BSWP 0x40 /* Byte Swap */ 198 #define XMTSP 0x30 /* Transmit Start Point */ 199 #define XMTSP_4 0x00 /* 4 bytes */ 200 #define XMTSP_16 0x10 /* 16 bytes */ 201 #define XMTSP_64 0x20 /* 64 bytes */ 202 #define XMTSP_112 0x30 /* 112 bytes */ 203 #define SWRST 0x01 /* Software Reset */ 204 205 /* 12: FIFO Configuration Control (FIFOCC) */ 206 #define XMTFW 0xc0 /* Transmit FIFO Watermark */ 207 #define XMTFW_8 0x00 /* 8 write cycles */ 208 #define XMTFW_16 0x40 /* 16 write cycles */ 209 #define XMTFW_32 0x80 /* 32 write cycles */ 210 #define RCVFW 0x30 /* Receive FIFO Watermark */ 211 #define RCVFW_16 0x00 /* 16 bytes */ 212 #define RCVFW_32 0x10 /* 32 bytes */ 213 #define RCVFW_64 0x20 /* 64 bytes */ 214 #define XMTFWU 0x08 /* Transmit FIFO Watermark Update */ 215 #define RCVFWU 0x04 /* Receive FIFO Watermark Update */ 216 #define XMTBRST 0x02 /* Transmit Burst */ 217 #define RCVBRST 0x01 /* Receive Burst */ 218 219 /* 13: MAC Configuration (MACCC) */ 220 #define PROM 0x80 /* Promiscuous */ 221 #define DXMT2PD 0x40 /* Disable Transmit Two Part Deferral */ 222 #define EMBA 0x20 /* Enable Modified Back-off Algorithm */ 223 #define DRCVPA 0x08 /* Disable Receive Physical Address */ 224 #define DRCVBC 0x04 /* Disable Receive Broadcast */ 225 #define ENXMT 0x02 /* Enable Transmit */ 226 #define ENRCV 0x01 /* Enable Receive */ 227 228 /* 14: PLS Configuration Control (PLSCC) */ 229 #define XMTSEL 0x08 /* Transmit Mode Select */ 230 #define PORTSEL 0x06 /* Port Select */ 231 #define PORTSEL_AUI 0x00 /* Select AUI */ 232 #define PORTSEL_10BT 0x02 /* Select 10BASE-T */ 233 #define PORTSEL_DAI 0x04 /* Select DAI port */ 234 #define PORTSEL_GPSI 0x06 /* Select GPSI */ 235 #define ENPLSIO 0x01 /* Enable PLS I/O */ 236 237 /* 15: PHY Configuration (PHYCC) */ 238 #define LNKFL 0x80 /* Link Fail */ 239 #define DLNKTST 0x40 /* Disable Link Test */ 240 #define REVPOL 0x20 /* Reversed Polarity */ 241 #define DAPC 0x10 /* Disable Auto Polarity Correction */ 242 #define LRT 0x08 /* Low Receive Threshold */ 243 #define ASEL 0x04 /* Auto Select */ 244 #define RWAKE 0x02 /* Remote Wake */ 245 #define AWAKE 0x01 /* Auto Wake */ 246 247 /* 18: Internal Address Configuration (IAC) */ 248 #define ADDRCHG 0x80 /* Address Change */ 249 #define PHYADDR 0x04 /* Physical Address Reset */ 250 #define LOGADDR 0x02 /* Logical Address Reset */ 251 252 /* 28: User Test Register (UTR) */ 253 #define RTRE 0x80 /* Reserved Test Register Enable */ 254 #define RTRD 0x40 /* Reserved Test Register Disable */ 255 #define RPA 0x20 /* Run Packet Accept */ 256 #define FCOLL 0x10 /* Force Collision */ 257 #define RCVFCSE 0x08 /* Receive FCS Enable */ 258 #define LOOP 0x06 /* Loopback Control */ 259 #define LOOP_NONE 0x00 /* No Loopback */ 260 #define LOOP_EXT 0x02 /* External Loopback */ 261 #define LOOP_INT 0x04 /* Internal Loopback, excludes MENDEC */ 262 #define LOOP_INT_MENDEC 0x06 /* Internal Loopback, includes MENDEC */ 263 264 struct mc_rxframe { 265 u_int8_t rx_rcvcnt; 266 u_int8_t rx_rcvsts; 267 u_int8_t rx_rntpc; 268 u_int8_t rx_rcvcc; 269 u_char *rx_frame; 270 }; 271 272 struct mc_softc { 273 struct device sc_dev; /* base device glue */ 274 struct arpcom sc_arpcom; /* Ethernet common part */ 275 struct timeout sc_tick_ch; 276 277 struct mc_rxframe sc_rxframe; 278 u_int8_t sc_biucc; 279 u_int8_t sc_fifocc; 280 u_int8_t sc_plscc; 281 u_int8_t sc_enaddr[6]; 282 u_int8_t sc_pad[2]; 283 int sc_havecarrier; /* carrier status */ 284 285 char *sc_reg; 286 bus_dma_tag_t sc_dmat; 287 bus_dmamap_t sc_bufmap; 288 bus_dma_segment_t sc_bufseg[1]; 289 290 dbdma_regmap_t *sc_txdma; 291 dbdma_regmap_t *sc_rxdma; 292 dbdma_command_t *sc_txdmacmd; 293 dbdma_command_t *sc_rxdmacmd; 294 dbdma_t sc_txdbdma; 295 dbdma_t sc_rxdbdma; 296 297 caddr_t sc_txbuf; 298 caddr_t sc_rxbuf; 299 paddr_t sc_txbuf_pa; 300 paddr_t sc_rxbuf_pa; 301 int sc_tail; 302 int sc_rxset; 303 int sc_txset; 304 int sc_txseti; 305 }; 306 307 int mc_match(struct device *, void *, void *); 308 void mc_attach(struct device *, struct device *, void *); 309 310 struct cfattach mc_ca = { 311 sizeof(struct mc_softc), mc_match, mc_attach 312 }; 313 314 struct cfdriver mc_cd = { 315 NULL, "mc", DV_IFNET 316 }; 317 318 void mc_init(struct mc_softc *sc); 319 void mc_put(struct mc_softc *sc, u_int len); 320 int mc_dmaintr(void *arg); 321 void mc_reset_rxdma(struct mc_softc *sc); 322 void mc_reset_txdma(struct mc_softc *sc); 323 int mc_stop(struct mc_softc *sc); 324 int mc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 325 void mc_start(struct ifnet *ifp); 326 void mc_reset(struct mc_softc *sc); 327 void mc_tint(struct mc_softc *sc); 328 void mc_rint(struct mc_softc *sc); 329 int mc_intr(void *); 330 void mc_watchdog(struct ifnet *ifp); 331 332 u_int maceput(struct mc_softc *sc, struct mbuf *); 333 void mace_read(struct mc_softc *, caddr_t, int); 334 struct mbuf *mace_get(struct mc_softc *, caddr_t, int); 335 static void mace_calcladrf(struct mc_softc *, u_int8_t *); 336 void mc_putpacket(struct mc_softc *, u_int); 337 338 int 339 mc_match(struct device *parent, void *arg, void *aux) 340 { 341 struct confargs *ca = aux; 342 343 if (strcmp(ca->ca_name, "mace") != 0) 344 return 0; 345 346 /* requires 6 regs */ 347 if (ca->ca_nreg / sizeof(int) != 6) 348 return 0; 349 350 /* requires 3 intrs */ 351 if (ca->ca_nintr / sizeof(int) != 3) 352 return 0; 353 354 return 1; 355 } 356 357 void 358 mc_attach(struct device *parent, struct device *self, void *aux) 359 { 360 struct confargs *ca = aux; 361 struct mc_softc *sc = (struct mc_softc *)self; 362 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 363 u_int8_t lladdr[ETHER_ADDR_LEN]; 364 int nseg, error; 365 366 if (OF_getprop(ca->ca_node, "local-mac-address", lladdr, 367 ETHER_ADDR_LEN) != ETHER_ADDR_LEN) { 368 printf(": failed to get MAC address.\n"); 369 return; 370 } 371 372 ca->ca_reg[0] += ca->ca_baseaddr; 373 ca->ca_reg[2] += ca->ca_baseaddr; 374 ca->ca_reg[4] += ca->ca_baseaddr; 375 376 if ((sc->sc_reg = mapiodev(ca->ca_reg[0], ca->ca_reg[1])) == NULL) { 377 printf(": cannot map registers\n"); 378 return; 379 } 380 381 sc->sc_dmat = ca->ca_dmat; 382 sc->sc_tail = 0; 383 384 if ((sc->sc_txdma = mapiodev(ca->ca_reg[2], ca->ca_reg[3])) == NULL) { 385 printf(": cannot map TX DMA registers\n"); 386 goto notxdma; 387 } 388 if ((sc->sc_rxdma = mapiodev(ca->ca_reg[4], ca->ca_reg[5])) == NULL) { 389 printf(": cannot map RX DMA registers\n"); 390 goto norxdma; 391 } 392 if ((sc->sc_txdbdma = dbdma_alloc(sc->sc_dmat, 2)) == NULL) { 393 printf(": cannot alloc TX DMA descriptors\n"); 394 goto notxdbdma; 395 } 396 sc->sc_txdmacmd = sc->sc_txdbdma->d_addr; 397 398 if ((sc->sc_rxdbdma = dbdma_alloc(sc->sc_dmat, 8 + 1)) == NULL) { 399 printf(": cannot alloc RX DMA descriptors\n"); 400 goto norxdbdma; 401 } 402 sc->sc_rxdmacmd = sc->sc_rxdbdma->d_addr; 403 404 if ((error = bus_dmamem_alloc(sc->sc_dmat, MACE_BUFSZ, PAGE_SIZE, 0, 405 sc->sc_bufseg, 1, &nseg, BUS_DMA_NOWAIT))) { 406 printf(": cannot allocate DMA mem (%d)\n", error); 407 goto nodmamem; 408 } 409 410 if ((error = bus_dmamem_map(sc->sc_dmat, sc->sc_bufseg, nseg, 411 MACE_BUFSZ, &sc->sc_txbuf, BUS_DMA_NOWAIT))) { 412 printf(": cannot map DMA mem (%d)\n", error); 413 goto nodmamap; 414 } 415 416 if ((error = bus_dmamap_create(sc->sc_dmat, MACE_BUFSZ, 1, MACE_BUFSZ, 417 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_bufmap))) { 418 printf(": cannot create DMA map (%d)\n", error); 419 goto nodmacreate; 420 } 421 422 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_bufmap, sc->sc_txbuf, 423 MACE_BUFSZ, NULL, BUS_DMA_NOWAIT))) { 424 printf(": cannot load DMA map (%d)\n", error); 425 goto nodmaload; 426 } 427 428 sc->sc_txbuf_pa = sc->sc_bufmap->dm_segs->ds_addr; 429 sc->sc_rxbuf = sc->sc_txbuf + MACE_BUFLEN * MACE_TXBUFS; 430 sc->sc_rxbuf_pa = sc->sc_txbuf_pa + MACE_BUFLEN * MACE_TXBUFS; 431 432 printf(": irq %d,%d,%d", ca->ca_intr[0], ca->ca_intr[1], 433 ca->ca_intr[2]); 434 435 /* disable receive DMA */ 436 dbdma_reset(sc->sc_rxdma); 437 438 /* disable transmit DMA */ 439 dbdma_reset(sc->sc_txdma); 440 441 /* install interrupt handlers */ 442 mac_intr_establish(parent, ca->ca_intr[2], IST_LEVEL, IPL_NET, 443 mc_dmaintr, sc, sc->sc_dev.dv_xname); 444 mac_intr_establish(parent, ca->ca_intr[0], IST_LEVEL, IPL_NET, 445 mc_intr, sc, sc->sc_dev.dv_xname); 446 447 sc->sc_biucc = XMTSP_64; 448 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | 449 XMTBRST | RCVBRST; 450 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 451 452 /* reset the chip and disable all interrupts */ 453 NIC_PUT(sc, MACE_BIUCC, SWRST); 454 DELAY(100); 455 456 NIC_PUT(sc, MACE_IMR, ~0); 457 458 bcopy(lladdr, sc->sc_enaddr, ETHER_ADDR_LEN); 459 bcopy(sc->sc_enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 460 printf(": address %s\n", ether_sprintf(lladdr)); 461 462 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 463 ifp->if_softc = sc; 464 ifp->if_ioctl = mc_ioctl; 465 ifp->if_start = mc_start; 466 ifp->if_flags = 467 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 468 ifp->if_watchdog = mc_watchdog; 469 ifp->if_timer = 0; 470 IFQ_SET_READY(&ifp->if_snd); 471 472 if_attach(ifp); 473 ether_ifattach(ifp); 474 475 return; 476 nodmaload: 477 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bufmap); 478 nodmacreate: 479 bus_dmamem_unmap(sc->sc_dmat, sc->sc_txbuf, MACE_BUFSZ); 480 nodmamap: 481 bus_dmamem_free(sc->sc_dmat, sc->sc_bufseg, 1); 482 nodmamem: 483 dbdma_free(sc->sc_rxdbdma); 484 norxdbdma: 485 dbdma_free(sc->sc_txdbdma); 486 notxdbdma: 487 unmapiodev((void *)sc->sc_rxdma, ca->ca_reg[5]); 488 norxdma: 489 unmapiodev((void *)sc->sc_txdma, ca->ca_reg[3]); 490 notxdma: 491 unmapiodev(sc->sc_reg, ca->ca_reg[1]); 492 } 493 494 int 495 mc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 496 { 497 struct mc_softc *sc = ifp->if_softc; 498 struct ifaddr *ifa = (struct ifaddr *)data; 499 int s, err = 0; 500 501 s = splnet(); 502 503 switch (cmd) { 504 case SIOCSIFADDR: 505 ifp->if_flags |= IFF_UP; 506 if (!(ifp->if_flags & IFF_RUNNING)) 507 mc_init(sc); 508 #ifdef INET 509 if (ifa->ifa_addr->sa_family == AF_INET) 510 arp_ifinit(&sc->sc_arpcom, ifa); 511 #endif 512 break; 513 514 case SIOCSIFFLAGS: 515 if ((ifp->if_flags & IFF_UP) == 0 && 516 (ifp->if_flags & IFF_RUNNING) != 0) { 517 /* 518 * If interface is marked down and it is running, 519 * then stop it. 520 */ 521 mc_stop(sc); 522 } else if ((ifp->if_flags & IFF_UP) != 0 && 523 (ifp->if_flags & IFF_RUNNING) == 0) { 524 /* 525 * If interface is marked up and it is stopped, 526 * then start it. 527 */ 528 mc_init(sc); 529 } else { 530 /* 531 * reset the interface to pick up any other changes 532 * in flags 533 */ 534 mc_reset(sc); 535 mc_start(ifp); 536 } 537 break; 538 539 default: 540 err = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 541 } 542 543 if (err == ENETRESET) { 544 if (ifp->if_flags & IFF_RUNNING) 545 mc_reset(sc); 546 err = 0; 547 } 548 549 splx(s); 550 return (err); 551 } 552 553 /* 554 * Encapsulate a packet of type family for the local net. 555 */ 556 void 557 mc_start(struct ifnet *ifp) 558 { 559 struct mc_softc *sc = ifp->if_softc; 560 struct mbuf *m; 561 562 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 563 return; 564 565 while (1) { 566 if (ifp->if_flags & IFF_OACTIVE) 567 return; 568 569 IFQ_DEQUEUE(&ifp->if_snd, m); 570 if (m == NULL) 571 return; 572 573 #if NBPFILTER > 0 574 /* 575 * If bpf is listening on this interface, let it 576 * see the packet before we commit it to the wire. 577 */ 578 if (ifp->if_bpf) 579 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 580 #endif 581 582 /* 583 * Copy the mbuf chain into the transmit buffer. 584 */ 585 ifp->if_flags |= IFF_OACTIVE; 586 maceput(sc, m); 587 588 ifp->if_opackets++; /* # of pkts */ 589 } 590 } 591 592 /* 593 * reset and restart the MACE. Called in case of fatal 594 * hardware/software errors. 595 */ 596 void 597 mc_reset(struct mc_softc *sc) 598 { 599 mc_stop(sc); 600 mc_init(sc); 601 } 602 603 void 604 mc_init(struct mc_softc *sc) 605 { 606 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 607 u_int8_t maccc, ladrf[8]; 608 int s, i; 609 610 s = splnet(); 611 612 NIC_PUT(sc, MACE_BIUCC, sc->sc_biucc); 613 NIC_PUT(sc, MACE_FIFOCC, sc->sc_fifocc); 614 NIC_PUT(sc, MACE_IMR, ~0); /* disable all interrupts */ 615 NIC_PUT(sc, MACE_PLSCC, sc->sc_plscc); 616 617 NIC_PUT(sc, MACE_UTR, RTRD); /* disable reserved test registers */ 618 619 /* set MAC address */ 620 NIC_PUT(sc, MACE_IAC, ADDRCHG); 621 while (NIC_GET(sc, MACE_IAC) & ADDRCHG) 622 ; 623 NIC_PUT(sc, MACE_IAC, PHYADDR); 624 for (i = 0; i < ETHER_ADDR_LEN; i++) 625 out8rb(sc->sc_reg + MACE_REG(MACE_PADR) + i, 626 sc->sc_enaddr[i]); 627 628 /* set logical address filter */ 629 mace_calcladrf(sc, ladrf); 630 631 NIC_PUT(sc, MACE_IAC, ADDRCHG); 632 while (NIC_GET(sc, MACE_IAC) & ADDRCHG) 633 ; 634 NIC_PUT(sc, MACE_IAC, LOGADDR); 635 for (i = 0; i < 8; i++) 636 out8rb(sc->sc_reg + MACE_REG(MACE_LADRF) + i, 637 ladrf[i]); 638 639 NIC_PUT(sc, MACE_XMTFC, APADXMT); 640 /* 641 * No need to autostrip padding on receive... Ethernet frames 642 * don't have a length field, unlike 802.3 frames, so the MACE 643 * can't figure out the length of the packet anyways. 644 */ 645 NIC_PUT(sc, MACE_RCVFC, 0); 646 647 maccc = ENXMT | ENRCV; 648 if (ifp->if_flags & IFF_PROMISC) 649 maccc |= PROM; 650 651 NIC_PUT(sc, MACE_MACCC, maccc); 652 653 mc_reset_rxdma(sc); 654 mc_reset_txdma(sc); 655 /* 656 * Enable all interrupts except receive, since we use the DMA 657 * completion interrupt for that. 658 */ 659 NIC_PUT(sc, MACE_IMR, RCVINTM); 660 661 /* flag interface as "running" */ 662 ifp->if_flags |= IFF_RUNNING; 663 ifp->if_flags &= ~IFF_OACTIVE; 664 665 splx(s); 666 } 667 668 /* 669 * Close down an interface and free its buffers. 670 * Called on final close of device, or if mcinit() fails 671 * part way through. 672 */ 673 int 674 mc_stop(struct mc_softc *sc) 675 { 676 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 677 int s; 678 679 s = splnet(); 680 681 NIC_PUT(sc, MACE_BIUCC, SWRST); 682 DELAY(100); 683 684 ifp->if_timer = 0; 685 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 686 687 splx(s); 688 return (0); 689 } 690 691 /* 692 * Called if any Tx packets remain unsent after 5 seconds, 693 * In all cases we just reset the chip, and any retransmission 694 * will be handled by higher level protocol timeouts. 695 */ 696 void 697 mc_watchdog(struct ifnet *ifp) 698 { 699 struct mc_softc *sc = ifp->if_softc; 700 701 printf("mcwatchdog: resetting chip\n"); 702 mc_reset(sc); 703 } 704 705 int 706 mc_intr(void *arg) 707 { 708 struct mc_softc *sc = arg; 709 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 710 u_int8_t ir; 711 712 ir = NIC_GET(sc, MACE_IR) & ~NIC_GET(sc, MACE_IMR); 713 714 if (ir & JAB) { 715 #ifdef MCDEBUG 716 printf("%s: jabber error\n", sc->sc_dev.dv_xname); 717 #endif 718 ifp->if_oerrors++; 719 } 720 721 if (ir & BABL) { 722 #ifdef MCDEBUG 723 printf("%s: babble\n", sc->sc_dev.dv_xname); 724 #endif 725 ifp->if_oerrors++; 726 } 727 728 if (ir & CERR) { 729 #ifdef MCDEBUG 730 printf("%s: collision error\n", sc->sc_dev.dv_xname); 731 #endif 732 ifp->if_collisions++; 733 } 734 735 /* 736 * Pretend we have carrier; if we don't this will be cleared 737 * shortly. 738 */ 739 sc->sc_havecarrier = 1; 740 741 if (ir & XMTINT) 742 mc_tint(sc); 743 744 if (ir & RCVINT) 745 mc_rint(sc); 746 747 return(1); 748 } 749 750 void 751 mc_tint(struct mc_softc *sc) 752 { 753 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 754 u_int8_t xmtrc, xmtfs; 755 756 xmtrc = NIC_GET(sc, MACE_XMTRC); 757 xmtfs = NIC_GET(sc, MACE_XMTFS); 758 759 if ((xmtfs & XMTSV) == 0) 760 return; 761 762 if (xmtfs & UFLO) { 763 printf("%s: underflow\n", sc->sc_dev.dv_xname); 764 mc_reset(sc); 765 return; 766 } 767 768 if (xmtfs & LCOL) { 769 printf("%s: late collision\n", sc->sc_dev.dv_xname); 770 ifp->if_oerrors++; 771 ifp->if_collisions++; 772 } 773 774 if (xmtfs & MORE) 775 /* Real number is unknown. */ 776 ifp->if_collisions += 2; 777 else if (xmtfs & ONE) 778 ifp->if_collisions++; 779 else if (xmtfs & RTRY) { 780 printf("%s: excessive collisions\n", sc->sc_dev.dv_xname); 781 ifp->if_collisions += 16; 782 ifp->if_oerrors++; 783 } 784 785 if (xmtfs & LCAR) { 786 sc->sc_havecarrier = 0; 787 printf("%s: lost carrier\n", sc->sc_dev.dv_xname); 788 ifp->if_oerrors++; 789 } 790 791 ifp->if_flags &= ~IFF_OACTIVE; 792 ifp->if_timer = 0; 793 mc_start(ifp); 794 } 795 796 void 797 mc_rint(struct mc_softc *sc) 798 { 799 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 800 #define rxf sc->sc_rxframe 801 u_int len; 802 803 len = (rxf.rx_rcvcnt | ((rxf.rx_rcvsts & 0xf) << 8)) - 4; 804 805 #ifdef MCDEBUG 806 if (rxf.rx_rcvsts & 0xf0) 807 printf("%s: rcvcnt %02x rcvsts %02x rntpc 0x%02x rcvcc 0x%02x\n", 808 sc->sc_dev.dv_xname, rxf.rx_rcvcnt, rxf.rx_rcvsts, 809 rxf.rx_rntpc, rxf.rx_rcvcc); 810 #endif 811 812 if (rxf.rx_rcvsts & OFLO) { 813 #ifdef MCDEBUG 814 printf("%s: receive FIFO overflow\n", sc->sc_dev.dv_xname); 815 #endif 816 ifp->if_ierrors++; 817 return; 818 } 819 820 if (rxf.rx_rcvsts & CLSN) 821 ifp->if_collisions++; 822 823 if (rxf.rx_rcvsts & FRAM) { 824 #ifdef MCDEBUG 825 printf("%s: framing error\n", sc->sc_dev.dv_xname); 826 #endif 827 ifp->if_ierrors++; 828 return; 829 } 830 831 if (rxf.rx_rcvsts & FCS) { 832 #ifdef MCDEBUG 833 printf("%s: frame control checksum error\n", sc->sc_dev.dv_xname); 834 #endif 835 ifp->if_ierrors++; 836 return; 837 } 838 839 mace_read(sc, rxf.rx_frame, len); 840 #undef rxf 841 } 842 /* 843 * stuff packet into MACE (at splnet) 844 */ 845 u_int 846 maceput(struct mc_softc *sc, struct mbuf *m) 847 { 848 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 849 struct mbuf *n; 850 u_int len, totlen = 0; 851 u_char *buff; 852 853 buff = sc->sc_txbuf; 854 855 for (; m; m = n) { 856 u_char *data = mtod(m, u_char *); 857 len = m->m_len; 858 totlen += len; 859 bcopy(data, buff, len); 860 buff += len; 861 MFREE(m, n); 862 } 863 864 if (totlen > PAGE_SIZE) 865 panic("%s: maceput: packet overflow", sc->sc_dev.dv_xname); 866 867 #if 0 868 if (totlen < ETHERMIN + sizeof(struct ether_header)) { 869 int pad = ETHERMIN + sizeof(struct ether_header) - totlen; 870 bzero(sc->sc_txbuf + totlen, pad); 871 totlen = ETHERMIN + sizeof(struct ether_header); 872 } 873 #endif 874 875 876 /* 5 seconds to watch for failing to transmit */ 877 ifp->if_timer = 5; 878 mc_putpacket(sc, totlen); 879 return (totlen); 880 } 881 882 void 883 mace_read(struct mc_softc *sc, caddr_t pkt, int len) 884 { 885 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 886 struct mbuf *m; 887 888 if (len <= sizeof(struct ether_header) || 889 len > ETHERMTU + sizeof(struct ether_header)) { 890 #ifdef MCDEBUG 891 printf("%s: invalid packet size %d; dropping\n", 892 sc->sc_dev.dv_xname, len); 893 #endif 894 ifp->if_ierrors++; 895 return; 896 } 897 898 m = mace_get(sc, pkt, len); 899 if (m == NULL) { 900 ifp->if_ierrors++; 901 return; 902 } 903 904 ifp->if_ipackets++; 905 906 #if NBPFILTER > 0 907 /* Pass the packet to any BPF listeners. */ 908 if (ifp->if_bpf) 909 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 910 #endif 911 912 /* Pass the packet up. */ 913 ether_input_mbuf(ifp, m); 914 } 915 916 /* 917 * Pull data off an interface. 918 * Len is length of data, with local net header stripped. 919 * We copy the data into mbufs. When full cluster sized units are present 920 * we copy into clusters. 921 */ 922 struct mbuf * 923 mace_get(struct mc_softc *sc, caddr_t pkt, int totlen) 924 { 925 struct mbuf *m; 926 struct mbuf *top, **mp; 927 int len; 928 929 MGETHDR(m, M_DONTWAIT, MT_DATA); 930 if (m == NULL) 931 return (NULL); 932 933 m->m_pkthdr.rcvif = &sc->sc_arpcom.ac_if; 934 m->m_pkthdr.len = totlen; 935 len = MHLEN; 936 top = 0; 937 mp = ⊤ 938 939 while (totlen > 0) { 940 if (top) { 941 MGET(m, M_DONTWAIT, MT_DATA); 942 if (m == NULL) { 943 m_freem(top); 944 return (NULL); 945 } 946 len = MLEN; 947 } 948 if (totlen >= MINCLSIZE) { 949 MCLGET(m, M_DONTWAIT); 950 if ((m->m_flags & M_EXT) == 0) { 951 m_free(m); 952 m_freem(top); 953 return (NULL); 954 } 955 len = MCLBYTES; 956 } 957 m->m_len = len = min(totlen, len); 958 bcopy(pkt, mtod(m, caddr_t), len); 959 pkt += len; 960 totlen -= len; 961 *mp = m; 962 mp = &m->m_next; 963 } 964 965 return (top); 966 } 967 968 void 969 mc_putpacket(struct mc_softc *sc, u_int len) 970 { 971 dbdma_command_t *cmd = sc->sc_txdmacmd; 972 973 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, sc->sc_txbuf_pa, 974 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 975 cmd++; 976 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, DBDMA_INT_ALWAYS, 977 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 978 979 dbdma_start(sc->sc_txdma, sc->sc_txdbdma); 980 } 981 982 /* 983 * Interrupt handler for the MACE DMA completion interrupts 984 */ 985 int 986 mc_dmaintr(void *arg) 987 { 988 struct mc_softc *sc = arg; 989 int status, offset, statoff; 990 int datalen, resid; 991 int i, n, count; 992 dbdma_command_t *cmd; 993 994 /* We've received some packets from the MACE */ 995 /* Loop through, processing each of the packets */ 996 i = sc->sc_tail; 997 for (n = 0; n < MC_RXDMABUFS; n++, i++) { 998 if (i == MC_RXDMABUFS) 999 i = 0; 1000 1001 cmd = &sc->sc_rxdmacmd[i]; 1002 status = dbdma_ld16(&cmd->d_status); 1003 resid = dbdma_ld16(&cmd->d_resid); 1004 1005 if ((status & DBDMA_CNTRL_ACTIVE) == 0) { 1006 continue; 1007 } 1008 1009 count = dbdma_ld16(&cmd->d_count); 1010 datalen = count - resid; 1011 datalen -= 4; /* 4 == status bytes */ 1012 1013 if (datalen < 4 + sizeof(struct ether_header)) { 1014 printf("short packet len=%d\n", datalen); 1015 /* continue; */ 1016 goto next; 1017 } 1018 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0); 1019 1020 offset = i * MACE_BUFLEN; 1021 statoff = offset + datalen; 1022 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[statoff + 0]; 1023 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[statoff + 1]; 1024 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[statoff + 2]; 1025 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[statoff + 3]; 1026 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset; 1027 1028 mc_rint(sc); 1029 1030 next: 1031 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS, 1032 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 1033 1034 cmd->d_status = 0; 1035 cmd->d_resid = 0; 1036 sc->sc_tail = i + 1; 1037 } 1038 1039 dbdma_continue(sc->sc_rxdma); 1040 1041 return 1; 1042 } 1043 1044 void 1045 mc_reset_rxdma(struct mc_softc *sc) 1046 { 1047 dbdma_command_t *cmd = sc->sc_rxdmacmd; 1048 int i; 1049 u_int8_t maccc; 1050 1051 /* Disable receiver, reset the DMA channels */ 1052 maccc = NIC_GET(sc, MACE_MACCC); 1053 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV); 1054 1055 dbdma_reset(sc->sc_rxdma); 1056 1057 bzero(sc->sc_rxdmacmd, 8 * sizeof(dbdma_command_t)); 1058 for (i = 0; i < MC_RXDMABUFS; i++) { 1059 DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, MACE_BUFLEN, 1060 sc->sc_rxbuf_pa + MACE_BUFLEN * i, DBDMA_INT_ALWAYS, 1061 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 1062 cmd++; 1063 } 1064 1065 DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0, 1066 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS); 1067 dbdma_st32(&cmd->d_cmddep, sc->sc_rxdbdma->d_paddr); 1068 cmd++; 1069 1070 sc->sc_tail = 0; 1071 1072 dbdma_start(sc->sc_rxdma, sc->sc_rxdbdma); 1073 /* Reenable receiver, reenable DMA */ 1074 NIC_PUT(sc, MACE_MACCC, maccc); 1075 } 1076 1077 void 1078 mc_reset_txdma(struct mc_softc *sc) 1079 { 1080 dbdma_command_t *cmd = sc->sc_txdmacmd; 1081 dbdma_regmap_t *dmareg = sc->sc_txdma; 1082 u_int8_t maccc; 1083 1084 /* disable transmitter */ 1085 maccc = NIC_GET(sc, MACE_MACCC); 1086 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT); 1087 1088 dbdma_reset(sc->sc_txdma); 1089 1090 bzero(sc->sc_txdmacmd, 2 * sizeof(dbdma_command_t)); 1091 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, 0, sc->sc_txbuf_pa, 1092 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 1093 cmd++; 1094 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 1095 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 1096 1097 out32rb(&dmareg->d_cmdptrhi, 0); 1098 out32rb(&dmareg->d_cmdptrlo, sc->sc_txdbdma->d_paddr); 1099 1100 /* restore old value */ 1101 NIC_PUT(sc, MACE_MACCC, maccc); 1102 } 1103 1104 /* 1105 * Go through the list of multicast addresses and calculate the logical 1106 * address filter. 1107 */ 1108 void 1109 mace_calcladrf(struct mc_softc *sc, u_int8_t *af) 1110 { 1111 struct ether_multi *enm; 1112 u_int32_t crc; 1113 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1114 struct arpcom *ac = &sc->sc_arpcom; 1115 struct ether_multistep step; 1116 /* 1117 * Set up multicast address filter by passing all multicast addresses 1118 * through a crc generator, and then using the high order 6 bits as an 1119 * index into the 64 bit logical address filter. The high order bit 1120 * selects the word, while the rest of the bits select the bit within 1121 * the word. 1122 */ 1123 1124 *((u_int32_t *)af) = *((u_int32_t *)af + 1) = 0; 1125 ETHER_FIRST_MULTI(step, ac, enm); 1126 while (enm != NULL) { 1127 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1128 /* 1129 * We must listen to a range of multicast addresses. 1130 * For now, just accept all multicasts, rather than 1131 * trying to set only those filter bits needed to match 1132 * the range. (At this time, the only use of address 1133 * ranges is for IP multicast routing, for which the 1134 * range is big enough to require all bits set.) 1135 */ 1136 goto allmulti; 1137 } 1138 1139 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1140 1141 /* Just want the 6 most significant bits. */ 1142 crc >>= 26; 1143 1144 /* Set the corresponding bit in the filter. */ 1145 af[crc >> 3] |= 1 << (crc & 7); 1146 1147 ETHER_NEXT_MULTI(step, enm); 1148 } 1149 ifp->if_flags &= ~IFF_ALLMULTI; 1150 return; 1151 1152 allmulti: 1153 ifp->if_flags |= IFF_ALLMULTI; 1154 *((u_int32_t *)af) = *((u_int32_t *)af + 1) = 0xffffffff; 1155 } 1156