1 /* $OpenBSD: if_mc.c,v 1.30 2020/07/10 13:22:19 patrick Exp $ */ 2 /* $NetBSD: if_mc.c,v 1.9.16.1 2006/06/21 14:53:13 yamt Exp $ */ 3 4 /*- 5 * Copyright (c) 1997 David Huang <khym@bga.com> 6 * All rights reserved. 7 * 8 * Portions of this code are based on code by Denton Gentry <denny1@home.com> 9 * and Yanagisawa Takeshi <yanagisw@aa.ap.titech.ac.jp>. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * AMD AM79C940 (MACE) driver with DBDMA bus attachment and DMA routines 34 * for onboard ethernet found on most old world macs. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/buf.h> 41 #include <sys/protosw.h> 42 #include <sys/socket.h> 43 #include <sys/syslog.h> 44 #include <sys/ioctl.h> 45 #include <sys/errno.h> 46 #include <sys/device.h> 47 #include <sys/timeout.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include "bpfilter.h" 56 #if NBPFILTER > 0 57 #include <net/bpf.h> 58 #endif 59 60 #include <dev/ofw/openfirm.h> 61 #include <machine/pio.h> 62 #include <machine/bus.h> 63 #include <machine/autoconf.h> 64 65 #include <macppc/dev/dbdma.h> 66 67 #define MC_REGSPACING 16 68 #define MC_REGSIZE MACE_NREGS * MC_REGSPACING 69 #define MACE_REG(x) ((x)*MC_REGSPACING) 70 #define MACE_BUFLEN 2048 71 #define MACE_TXBUFS 2 72 #define MACE_RXBUFS 8 73 74 #define MC_RXDMABUFS 4 75 76 #define MACE_BUFSZ ((MACE_RXBUFS + MACE_TXBUFS + 2) * MACE_BUFLEN) 77 78 #define NIC_GET(sc, reg) (in8rb(sc->sc_reg + MACE_REG(reg))) 79 80 #define NIC_PUT(sc, reg, val) (out8rb(sc->sc_reg + MACE_REG(reg), (val))) 81 82 /* 83 * AMD MACE (Am79C940) register definitions 84 */ 85 #define MACE_RCVFIFO 0 /* Receive FIFO [15-00] (read only) */ 86 #define MACE_XMTFIFO 1 /* Transmit FIFO [15-00] (write only) */ 87 #define MACE_XMTFC 2 /* Transmit Frame Control (read/write) */ 88 #define MACE_XMTFS 3 /* Transmit Frame Status (read only) */ 89 #define MACE_XMTRC 4 /* Transmit Retry Count (read only) */ 90 #define MACE_RCVFC 5 /* Receive Frame Control (read/write) */ 91 #define MACE_RCVFS 6 /* Receive Frame Status (4 bytes) (read only) */ 92 #define MACE_FIFOFC 7 /* FIFO Frame Count (read only) */ 93 #define MACE_IR 8 /* Interrupt Register (read only) */ 94 #define MACE_IMR 9 /* Interrupt Mask Register (read/write) */ 95 #define MACE_PR 10 /* Poll Register (read only) */ 96 #define MACE_BIUCC 11 /* BIU Configuration Control (read/write) */ 97 #define MACE_FIFOCC 12 /* FIFO Configuration Control (read/write) */ 98 #define MACE_MACCC 13 /* MAC Configuration Control (read/write) */ 99 #define MACE_PLSCC 14 /* PLS Configuration Control (read/write) */ 100 #define MACE_PHYCC 15 /* PHY Confiuration Control (read/write) */ 101 #define MACE_CHIPIDL 16 /* Chip ID Register [07-00] (read only) */ 102 #define MACE_CHIPIDH 17 /* Chip ID Register [15-08] (read only) */ 103 #define MACE_IAC 18 /* Internal Address Configuration (read/write) */ 104 /* RESERVED 19 Reserved (read/write as 0) */ 105 #define MACE_LADRF 20 /* Logical Address Filter (8 bytes) (read/write) */ 106 #define MACE_PADR 21 /* Physical Address (6 bytes) (read/write) */ 107 /* RESERVED 22 Reserved (read/write as 0) */ 108 /* RESERVED 23 Reserved (read/write as 0) */ 109 #define MACE_MPC 24 /* Missed Packet Count (read only) */ 110 /* RESERVED 25 Reserved (read/write as 0) */ 111 #define MACE_RNTPC 26 /* Runt Packet Count (read only) */ 112 #define MACE_RCVCC 27 /* Receive Collision Count (read only) */ 113 /* RESERVED 28 Reserved (read/write as 0) */ 114 #define MACE_UTR 29 /* User Test Register (read/write) */ 115 #define MACE_RTR1 30 /* Reserved Test Register 1 (read/write as 0) */ 116 #define MACE_RTR2 31 /* Reserved Test Register 2 (read/write as 0) */ 117 118 #define MACE_NREGS 32 119 120 /* 2: Transmit Frame Control (XMTFC) */ 121 #define DRTRY 0x80 /* Disable Retry */ 122 #define DXMTFCS 0x08 /* Disable Transmit FCS */ 123 #define APADXMT 0x01 /* Auto Pad Transmit */ 124 125 /* 3: Transmit Frame Status (XMTFS) */ 126 #define XMTSV 0x80 /* Transmit Status Valid */ 127 #define UFLO 0x40 /* Underflow */ 128 #define LCOL 0x20 /* Late Collision */ 129 #define MORE 0x10 /* More than one retry needed */ 130 #define ONE 0x08 /* Exactly one retry needed */ 131 #define DEFER 0x04 /* Transmission deferred */ 132 #define LCAR 0x02 /* Loss of Carrier */ 133 #define RTRY 0x01 /* Retry Error */ 134 135 /* 4: Transmit Retry Count (XMTRC) */ 136 #define EXDEF 0x80 /* Excessive Defer */ 137 #define XMTRC 0x0f /* Transmit Retry Count */ 138 139 /* 5: Receive Frame Control (RCVFC) */ 140 #define LLRCV 0x08 /* Low Latency Receive */ 141 #define MR 0x04 /* Match/Reject */ 142 #define ASTRPRCV 0x01 /* Auto Strip Receive */ 143 144 /* 6: Receive Frame Status (RCVFS) */ 145 /* 4 byte register; read 4 times to get all of the bytes */ 146 /* Read 1: RFS0 - Receive Message Byte Count [7-0] (RCVCNT) */ 147 148 /* Read 2: RFS1 - Receive Status (RCVSTS) */ 149 #define OFLO 0x80 /* Overflow flag */ 150 #define CLSN 0x40 /* Collision flag */ 151 #define FRAM 0x20 /* Framing Error flag */ 152 #define FCS 0x10 /* FCS Error flag */ 153 #define RCVCNT 0x0f /* Receive Message Byte Count [11-8] */ 154 155 /* Read 3: RFS2 - Runt Packet Count (RNTPC) [7-0] */ 156 157 /* Read 4: RFS3 - Receive Collision Count (RCVCC) [7-0] */ 158 159 /* 7: FIFO Frame Count (FIFOFC) */ 160 #define RCVFC 0xf0 /* Receive Frame Count */ 161 #define XMTFC 0x0f /* Transmit Frame Count */ 162 163 /* 8: Interrupt Register (IR) */ 164 #define JAB 0x80 /* Jabber Error */ 165 #define BABL 0x40 /* Babble Error */ 166 #define CERR 0x20 /* Collision Error */ 167 #define RCVCCO 0x10 /* Receive Collision Count Overflow */ 168 #define RNTPCO 0x08 /* Runt Packet Count Overflow */ 169 #define MPCO 0x04 /* Missed Packet Count Overflow */ 170 #define RCVINT 0x02 /* Receive Interrupt */ 171 #define XMTINT 0x01 /* Transmit Interrupt */ 172 173 /* 9: Interrut Mask Register (IMR) */ 174 #define JABM 0x80 /* Jabber Error Mask */ 175 #define BABLM 0x40 /* Babble Error Mask */ 176 #define CERRM 0x20 /* Collision Error Mask */ 177 #define RCVCCOM 0x10 /* Receive Collision Count Overflow Mask */ 178 #define RNTPCOM 0x08 /* Runt Packet Count Overflow Mask */ 179 #define MPCOM 0x04 /* Missed Packet Count Overflow Mask */ 180 #define RCVINTM 0x02 /* Receive Interrupt Mask */ 181 #define XMTINTM 0x01 /* Transmit Interrupt Mask */ 182 183 /* 10: Poll Register (PR) */ 184 #define XMTSV 0x80 /* Transmit Status Valid */ 185 #define TDTREQ 0x40 /* Transmit Data Transfer Request */ 186 #define RDTREQ 0x20 /* Receive Data Transfer Request */ 187 188 /* 11: BIU Configuration Control (BIUCC) */ 189 #define BSWP 0x40 /* Byte Swap */ 190 #define XMTSP 0x30 /* Transmit Start Point */ 191 #define XMTSP_4 0x00 /* 4 bytes */ 192 #define XMTSP_16 0x10 /* 16 bytes */ 193 #define XMTSP_64 0x20 /* 64 bytes */ 194 #define XMTSP_112 0x30 /* 112 bytes */ 195 #define SWRST 0x01 /* Software Reset */ 196 197 /* 12: FIFO Configuration Control (FIFOCC) */ 198 #define XMTFW 0xc0 /* Transmit FIFO Watermark */ 199 #define XMTFW_8 0x00 /* 8 write cycles */ 200 #define XMTFW_16 0x40 /* 16 write cycles */ 201 #define XMTFW_32 0x80 /* 32 write cycles */ 202 #define RCVFW 0x30 /* Receive FIFO Watermark */ 203 #define RCVFW_16 0x00 /* 16 bytes */ 204 #define RCVFW_32 0x10 /* 32 bytes */ 205 #define RCVFW_64 0x20 /* 64 bytes */ 206 #define XMTFWU 0x08 /* Transmit FIFO Watermark Update */ 207 #define RCVFWU 0x04 /* Receive FIFO Watermark Update */ 208 #define XMTBRST 0x02 /* Transmit Burst */ 209 #define RCVBRST 0x01 /* Receive Burst */ 210 211 /* 13: MAC Configuration (MACCC) */ 212 #define PROM 0x80 /* Promiscuous */ 213 #define DXMT2PD 0x40 /* Disable Transmit Two Part Deferral */ 214 #define EMBA 0x20 /* Enable Modified Back-off Algorithm */ 215 #define DRCVPA 0x08 /* Disable Receive Physical Address */ 216 #define DRCVBC 0x04 /* Disable Receive Broadcast */ 217 #define ENXMT 0x02 /* Enable Transmit */ 218 #define ENRCV 0x01 /* Enable Receive */ 219 220 /* 14: PLS Configuration Control (PLSCC) */ 221 #define XMTSEL 0x08 /* Transmit Mode Select */ 222 #define PORTSEL 0x06 /* Port Select */ 223 #define PORTSEL_AUI 0x00 /* Select AUI */ 224 #define PORTSEL_10BT 0x02 /* Select 10BASE-T */ 225 #define PORTSEL_DAI 0x04 /* Select DAI port */ 226 #define PORTSEL_GPSI 0x06 /* Select GPSI */ 227 #define ENPLSIO 0x01 /* Enable PLS I/O */ 228 229 /* 15: PHY Configuration (PHYCC) */ 230 #define LNKFL 0x80 /* Link Fail */ 231 #define DLNKTST 0x40 /* Disable Link Test */ 232 #define REVPOL 0x20 /* Reversed Polarity */ 233 #define DAPC 0x10 /* Disable Auto Polarity Correction */ 234 #define LRT 0x08 /* Low Receive Threshold */ 235 #define ASEL 0x04 /* Auto Select */ 236 #define RWAKE 0x02 /* Remote Wake */ 237 #define AWAKE 0x01 /* Auto Wake */ 238 239 /* 18: Internal Address Configuration (IAC) */ 240 #define ADDRCHG 0x80 /* Address Change */ 241 #define PHYADDR 0x04 /* Physical Address Reset */ 242 #define LOGADDR 0x02 /* Logical Address Reset */ 243 244 /* 28: User Test Register (UTR) */ 245 #define RTRE 0x80 /* Reserved Test Register Enable */ 246 #define RTRD 0x40 /* Reserved Test Register Disable */ 247 #define RPA 0x20 /* Run Packet Accept */ 248 #define FCOLL 0x10 /* Force Collision */ 249 #define RCVFCSE 0x08 /* Receive FCS Enable */ 250 #define LOOP 0x06 /* Loopback Control */ 251 #define LOOP_NONE 0x00 /* No Loopback */ 252 #define LOOP_EXT 0x02 /* External Loopback */ 253 #define LOOP_INT 0x04 /* Internal Loopback, excludes MENDEC */ 254 #define LOOP_INT_MENDEC 0x06 /* Internal Loopback, includes MENDEC */ 255 256 struct mc_rxframe { 257 u_int8_t rx_rcvcnt; 258 u_int8_t rx_rcvsts; 259 u_int8_t rx_rntpc; 260 u_int8_t rx_rcvcc; 261 u_char *rx_frame; 262 }; 263 264 struct mc_softc { 265 struct device sc_dev; /* base device glue */ 266 struct arpcom sc_arpcom; /* Ethernet common part */ 267 struct timeout sc_tick_ch; 268 269 struct mc_rxframe sc_rxframe; 270 u_int8_t sc_biucc; 271 u_int8_t sc_fifocc; 272 u_int8_t sc_plscc; 273 u_int8_t sc_enaddr[6]; 274 u_int8_t sc_pad[2]; 275 int sc_havecarrier; /* carrier status */ 276 277 char *sc_reg; 278 bus_dma_tag_t sc_dmat; 279 bus_dmamap_t sc_bufmap; 280 bus_dma_segment_t sc_bufseg[1]; 281 282 dbdma_regmap_t *sc_txdma; 283 dbdma_regmap_t *sc_rxdma; 284 dbdma_command_t *sc_txdmacmd; 285 dbdma_command_t *sc_rxdmacmd; 286 dbdma_t sc_txdbdma; 287 dbdma_t sc_rxdbdma; 288 289 caddr_t sc_txbuf; 290 caddr_t sc_rxbuf; 291 paddr_t sc_txbuf_pa; 292 paddr_t sc_rxbuf_pa; 293 int sc_tail; 294 int sc_rxset; 295 int sc_txset; 296 int sc_txseti; 297 }; 298 299 int mc_match(struct device *, void *, void *); 300 void mc_attach(struct device *, struct device *, void *); 301 302 struct cfattach mc_ca = { 303 sizeof(struct mc_softc), mc_match, mc_attach 304 }; 305 306 struct cfdriver mc_cd = { 307 NULL, "mc", DV_IFNET 308 }; 309 310 void mc_init(struct mc_softc *sc); 311 void mc_put(struct mc_softc *sc, u_int len); 312 int mc_dmaintr(void *arg); 313 void mc_reset_rxdma(struct mc_softc *sc); 314 void mc_reset_txdma(struct mc_softc *sc); 315 int mc_stop(struct mc_softc *sc); 316 int mc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 317 void mc_start(struct ifnet *ifp); 318 void mc_reset(struct mc_softc *sc); 319 void mc_tint(struct mc_softc *sc); 320 void mc_rint(struct mc_softc *sc); 321 int mc_intr(void *); 322 void mc_watchdog(struct ifnet *ifp); 323 324 u_int maceput(struct mc_softc *sc, struct mbuf *); 325 void mace_read(struct mc_softc *, caddr_t, int); 326 struct mbuf *mace_get(struct mc_softc *, caddr_t, int); 327 static void mace_calcladrf(struct mc_softc *, u_int8_t *); 328 void mc_putpacket(struct mc_softc *, u_int); 329 330 int 331 mc_match(struct device *parent, void *arg, void *aux) 332 { 333 struct confargs *ca = aux; 334 335 if (strcmp(ca->ca_name, "mace") != 0) 336 return 0; 337 338 /* requires 6 regs */ 339 if (ca->ca_nreg / sizeof(int) != 6) 340 return 0; 341 342 /* requires 3 intrs */ 343 if (ca->ca_nintr / sizeof(int) != 3) 344 return 0; 345 346 return 1; 347 } 348 349 void 350 mc_attach(struct device *parent, struct device *self, void *aux) 351 { 352 struct confargs *ca = aux; 353 struct mc_softc *sc = (struct mc_softc *)self; 354 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 355 u_int8_t lladdr[ETHER_ADDR_LEN]; 356 int nseg, error; 357 358 if (OF_getprop(ca->ca_node, "local-mac-address", lladdr, 359 ETHER_ADDR_LEN) != ETHER_ADDR_LEN) { 360 printf(": failed to get MAC address.\n"); 361 return; 362 } 363 364 ca->ca_reg[0] += ca->ca_baseaddr; 365 ca->ca_reg[2] += ca->ca_baseaddr; 366 ca->ca_reg[4] += ca->ca_baseaddr; 367 368 if ((sc->sc_reg = mapiodev(ca->ca_reg[0], ca->ca_reg[1])) == NULL) { 369 printf(": cannot map registers\n"); 370 return; 371 } 372 373 sc->sc_dmat = ca->ca_dmat; 374 sc->sc_tail = 0; 375 376 if ((sc->sc_txdma = mapiodev(ca->ca_reg[2], ca->ca_reg[3])) == NULL) { 377 printf(": cannot map TX DMA registers\n"); 378 goto notxdma; 379 } 380 if ((sc->sc_rxdma = mapiodev(ca->ca_reg[4], ca->ca_reg[5])) == NULL) { 381 printf(": cannot map RX DMA registers\n"); 382 goto norxdma; 383 } 384 if ((sc->sc_txdbdma = dbdma_alloc(sc->sc_dmat, 2)) == NULL) { 385 printf(": cannot alloc TX DMA descriptors\n"); 386 goto notxdbdma; 387 } 388 sc->sc_txdmacmd = sc->sc_txdbdma->d_addr; 389 390 if ((sc->sc_rxdbdma = dbdma_alloc(sc->sc_dmat, 8 + 1)) == NULL) { 391 printf(": cannot alloc RX DMA descriptors\n"); 392 goto norxdbdma; 393 } 394 sc->sc_rxdmacmd = sc->sc_rxdbdma->d_addr; 395 396 if ((error = bus_dmamem_alloc(sc->sc_dmat, MACE_BUFSZ, PAGE_SIZE, 0, 397 sc->sc_bufseg, 1, &nseg, BUS_DMA_NOWAIT))) { 398 printf(": cannot allocate DMA mem (%d)\n", error); 399 goto nodmamem; 400 } 401 402 if ((error = bus_dmamem_map(sc->sc_dmat, sc->sc_bufseg, nseg, 403 MACE_BUFSZ, &sc->sc_txbuf, BUS_DMA_NOWAIT))) { 404 printf(": cannot map DMA mem (%d)\n", error); 405 goto nodmamap; 406 } 407 408 if ((error = bus_dmamap_create(sc->sc_dmat, MACE_BUFSZ, 1, MACE_BUFSZ, 409 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_bufmap))) { 410 printf(": cannot create DMA map (%d)\n", error); 411 goto nodmacreate; 412 } 413 414 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_bufmap, sc->sc_txbuf, 415 MACE_BUFSZ, NULL, BUS_DMA_NOWAIT))) { 416 printf(": cannot load DMA map (%d)\n", error); 417 goto nodmaload; 418 } 419 420 sc->sc_txbuf_pa = sc->sc_bufmap->dm_segs->ds_addr; 421 sc->sc_rxbuf = sc->sc_txbuf + MACE_BUFLEN * MACE_TXBUFS; 422 sc->sc_rxbuf_pa = sc->sc_txbuf_pa + MACE_BUFLEN * MACE_TXBUFS; 423 424 printf(": irq %d,%d,%d", ca->ca_intr[0], ca->ca_intr[1], 425 ca->ca_intr[2]); 426 427 /* disable receive DMA */ 428 dbdma_reset(sc->sc_rxdma); 429 430 /* disable transmit DMA */ 431 dbdma_reset(sc->sc_txdma); 432 433 /* install interrupt handlers */ 434 mac_intr_establish(parent, ca->ca_intr[2], IST_LEVEL, IPL_NET, 435 mc_dmaintr, sc, sc->sc_dev.dv_xname); 436 mac_intr_establish(parent, ca->ca_intr[0], IST_LEVEL, IPL_NET, 437 mc_intr, sc, sc->sc_dev.dv_xname); 438 439 sc->sc_biucc = XMTSP_64; 440 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | 441 XMTBRST | RCVBRST; 442 sc->sc_plscc = PORTSEL_GPSI | ENPLSIO; 443 444 /* reset the chip and disable all interrupts */ 445 NIC_PUT(sc, MACE_BIUCC, SWRST); 446 DELAY(100); 447 448 NIC_PUT(sc, MACE_IMR, ~0); 449 450 bcopy(lladdr, sc->sc_enaddr, ETHER_ADDR_LEN); 451 bcopy(sc->sc_enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 452 printf(": address %s\n", ether_sprintf(lladdr)); 453 454 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 455 ifp->if_softc = sc; 456 ifp->if_ioctl = mc_ioctl; 457 ifp->if_start = mc_start; 458 ifp->if_flags = 459 IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 460 ifp->if_watchdog = mc_watchdog; 461 ifp->if_timer = 0; 462 463 if_attach(ifp); 464 ether_ifattach(ifp); 465 466 return; 467 nodmaload: 468 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bufmap); 469 nodmacreate: 470 bus_dmamem_unmap(sc->sc_dmat, sc->sc_txbuf, MACE_BUFSZ); 471 nodmamap: 472 bus_dmamem_free(sc->sc_dmat, sc->sc_bufseg, 1); 473 nodmamem: 474 dbdma_free(sc->sc_rxdbdma); 475 norxdbdma: 476 dbdma_free(sc->sc_txdbdma); 477 notxdbdma: 478 unmapiodev((void *)sc->sc_rxdma, ca->ca_reg[5]); 479 norxdma: 480 unmapiodev((void *)sc->sc_txdma, ca->ca_reg[3]); 481 notxdma: 482 unmapiodev(sc->sc_reg, ca->ca_reg[1]); 483 } 484 485 int 486 mc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 487 { 488 struct mc_softc *sc = ifp->if_softc; 489 int s, err = 0; 490 491 s = splnet(); 492 493 switch (cmd) { 494 case SIOCSIFADDR: 495 ifp->if_flags |= IFF_UP; 496 if (!(ifp->if_flags & IFF_RUNNING)) 497 mc_init(sc); 498 break; 499 500 case SIOCSIFFLAGS: 501 if ((ifp->if_flags & IFF_UP) == 0 && 502 (ifp->if_flags & IFF_RUNNING) != 0) { 503 /* 504 * If interface is marked down and it is running, 505 * then stop it. 506 */ 507 mc_stop(sc); 508 } else if ((ifp->if_flags & IFF_UP) != 0 && 509 (ifp->if_flags & IFF_RUNNING) == 0) { 510 /* 511 * If interface is marked up and it is stopped, 512 * then start it. 513 */ 514 mc_init(sc); 515 } else { 516 /* 517 * reset the interface to pick up any other changes 518 * in flags 519 */ 520 mc_reset(sc); 521 mc_start(ifp); 522 } 523 break; 524 525 default: 526 err = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 527 } 528 529 if (err == ENETRESET) { 530 if (ifp->if_flags & IFF_RUNNING) 531 mc_reset(sc); 532 err = 0; 533 } 534 535 splx(s); 536 return (err); 537 } 538 539 /* 540 * Encapsulate a packet of type family for the local net. 541 */ 542 void 543 mc_start(struct ifnet *ifp) 544 { 545 struct mc_softc *sc = ifp->if_softc; 546 struct mbuf *m; 547 548 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 549 return; 550 551 while (1) { 552 if (ifq_is_oactive(&ifp->if_snd)) 553 return; 554 555 m = ifq_dequeue(&ifp->if_snd); 556 if (m == NULL) 557 return; 558 559 #if NBPFILTER > 0 560 /* 561 * If bpf is listening on this interface, let it 562 * see the packet before we commit it to the wire. 563 */ 564 if (ifp->if_bpf) 565 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 566 #endif 567 568 /* 569 * Copy the mbuf chain into the transmit buffer. 570 */ 571 ifq_set_oactive(&ifp->if_snd); 572 maceput(sc, m); 573 } 574 } 575 576 /* 577 * reset and restart the MACE. Called in case of fatal 578 * hardware/software errors. 579 */ 580 void 581 mc_reset(struct mc_softc *sc) 582 { 583 mc_stop(sc); 584 mc_init(sc); 585 } 586 587 void 588 mc_init(struct mc_softc *sc) 589 { 590 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 591 u_int8_t maccc, ladrf[8]; 592 int s, i; 593 594 s = splnet(); 595 596 NIC_PUT(sc, MACE_BIUCC, sc->sc_biucc); 597 NIC_PUT(sc, MACE_FIFOCC, sc->sc_fifocc); 598 NIC_PUT(sc, MACE_IMR, ~0); /* disable all interrupts */ 599 NIC_PUT(sc, MACE_PLSCC, sc->sc_plscc); 600 601 NIC_PUT(sc, MACE_UTR, RTRD); /* disable reserved test registers */ 602 603 /* set MAC address */ 604 NIC_PUT(sc, MACE_IAC, ADDRCHG); 605 while (NIC_GET(sc, MACE_IAC) & ADDRCHG) 606 ; 607 NIC_PUT(sc, MACE_IAC, PHYADDR); 608 for (i = 0; i < ETHER_ADDR_LEN; i++) 609 out8rb(sc->sc_reg + MACE_REG(MACE_PADR) + i, 610 sc->sc_enaddr[i]); 611 612 /* set logical address filter */ 613 mace_calcladrf(sc, ladrf); 614 615 NIC_PUT(sc, MACE_IAC, ADDRCHG); 616 while (NIC_GET(sc, MACE_IAC) & ADDRCHG) 617 ; 618 NIC_PUT(sc, MACE_IAC, LOGADDR); 619 for (i = 0; i < 8; i++) 620 out8rb(sc->sc_reg + MACE_REG(MACE_LADRF) + i, 621 ladrf[i]); 622 623 NIC_PUT(sc, MACE_XMTFC, APADXMT); 624 /* 625 * No need to autostrip padding on receive... Ethernet frames 626 * don't have a length field, unlike 802.3 frames, so the MACE 627 * can't figure out the length of the packet anyways. 628 */ 629 NIC_PUT(sc, MACE_RCVFC, 0); 630 631 maccc = ENXMT | ENRCV; 632 if (ifp->if_flags & IFF_PROMISC) 633 maccc |= PROM; 634 635 NIC_PUT(sc, MACE_MACCC, maccc); 636 637 mc_reset_rxdma(sc); 638 mc_reset_txdma(sc); 639 /* 640 * Enable all interrupts except receive, since we use the DMA 641 * completion interrupt for that. 642 */ 643 NIC_PUT(sc, MACE_IMR, RCVINTM); 644 645 /* flag interface as "running" */ 646 ifp->if_flags |= IFF_RUNNING; 647 ifq_clr_oactive(&ifp->if_snd); 648 649 splx(s); 650 } 651 652 /* 653 * Close down an interface and free its buffers. 654 * Called on final close of device, or if mcinit() fails 655 * part way through. 656 */ 657 int 658 mc_stop(struct mc_softc *sc) 659 { 660 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 661 int s; 662 663 s = splnet(); 664 665 NIC_PUT(sc, MACE_BIUCC, SWRST); 666 DELAY(100); 667 668 ifp->if_timer = 0; 669 ifp->if_flags &= ~IFF_RUNNING; 670 ifq_clr_oactive(&ifp->if_snd); 671 672 splx(s); 673 return (0); 674 } 675 676 /* 677 * Called if any Tx packets remain unsent after 5 seconds, 678 * In all cases we just reset the chip, and any retransmission 679 * will be handled by higher level protocol timeouts. 680 */ 681 void 682 mc_watchdog(struct ifnet *ifp) 683 { 684 struct mc_softc *sc = ifp->if_softc; 685 686 printf("mcwatchdog: resetting chip\n"); 687 mc_reset(sc); 688 } 689 690 int 691 mc_intr(void *arg) 692 { 693 struct mc_softc *sc = arg; 694 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 695 u_int8_t ir; 696 697 ir = NIC_GET(sc, MACE_IR) & ~NIC_GET(sc, MACE_IMR); 698 699 if (ir & JAB) { 700 #ifdef MCDEBUG 701 printf("%s: jabber error\n", sc->sc_dev.dv_xname); 702 #endif 703 ifp->if_oerrors++; 704 } 705 706 if (ir & BABL) { 707 #ifdef MCDEBUG 708 printf("%s: babble\n", sc->sc_dev.dv_xname); 709 #endif 710 ifp->if_oerrors++; 711 } 712 713 if (ir & CERR) { 714 #ifdef MCDEBUG 715 printf("%s: collision error\n", sc->sc_dev.dv_xname); 716 #endif 717 ifp->if_collisions++; 718 } 719 720 /* 721 * Pretend we have carrier; if we don't this will be cleared 722 * shortly. 723 */ 724 sc->sc_havecarrier = 1; 725 726 if (ir & XMTINT) 727 mc_tint(sc); 728 729 if (ir & RCVINT) 730 mc_rint(sc); 731 732 return(1); 733 } 734 735 void 736 mc_tint(struct mc_softc *sc) 737 { 738 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 739 u_int8_t xmtrc, xmtfs; 740 741 xmtrc = NIC_GET(sc, MACE_XMTRC); 742 xmtfs = NIC_GET(sc, MACE_XMTFS); 743 744 if ((xmtfs & XMTSV) == 0) 745 return; 746 747 if (xmtfs & UFLO) { 748 printf("%s: underflow\n", sc->sc_dev.dv_xname); 749 mc_reset(sc); 750 return; 751 } 752 753 if (xmtfs & LCOL) { 754 printf("%s: late collision\n", sc->sc_dev.dv_xname); 755 ifp->if_oerrors++; 756 ifp->if_collisions++; 757 } 758 759 if (xmtfs & MORE) 760 /* Real number is unknown. */ 761 ifp->if_collisions += 2; 762 else if (xmtfs & ONE) 763 ifp->if_collisions++; 764 else if (xmtfs & RTRY) { 765 printf("%s: excessive collisions\n", sc->sc_dev.dv_xname); 766 ifp->if_collisions += 16; 767 ifp->if_oerrors++; 768 } 769 770 if (xmtfs & LCAR) { 771 sc->sc_havecarrier = 0; 772 printf("%s: lost carrier\n", sc->sc_dev.dv_xname); 773 ifp->if_oerrors++; 774 } 775 776 ifq_clr_oactive(&ifp->if_snd); 777 ifp->if_timer = 0; 778 mc_start(ifp); 779 } 780 781 void 782 mc_rint(struct mc_softc *sc) 783 { 784 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 785 #define rxf sc->sc_rxframe 786 u_int len; 787 788 len = (rxf.rx_rcvcnt | ((rxf.rx_rcvsts & 0xf) << 8)) - 4; 789 790 #ifdef MCDEBUG 791 if (rxf.rx_rcvsts & 0xf0) 792 printf("%s: rcvcnt %02x rcvsts %02x rntpc 0x%02x rcvcc 0x%02x\n", 793 sc->sc_dev.dv_xname, rxf.rx_rcvcnt, rxf.rx_rcvsts, 794 rxf.rx_rntpc, rxf.rx_rcvcc); 795 #endif 796 797 if (rxf.rx_rcvsts & OFLO) { 798 #ifdef MCDEBUG 799 printf("%s: receive FIFO overflow\n", sc->sc_dev.dv_xname); 800 #endif 801 ifp->if_ierrors++; 802 return; 803 } 804 805 if (rxf.rx_rcvsts & CLSN) 806 ifp->if_collisions++; 807 808 if (rxf.rx_rcvsts & FRAM) { 809 #ifdef MCDEBUG 810 printf("%s: framing error\n", sc->sc_dev.dv_xname); 811 #endif 812 ifp->if_ierrors++; 813 return; 814 } 815 816 if (rxf.rx_rcvsts & FCS) { 817 #ifdef MCDEBUG 818 printf("%s: frame control checksum error\n", sc->sc_dev.dv_xname); 819 #endif 820 ifp->if_ierrors++; 821 return; 822 } 823 824 mace_read(sc, rxf.rx_frame, len); 825 #undef rxf 826 } 827 /* 828 * stuff packet into MACE (at splnet) 829 */ 830 u_int 831 maceput(struct mc_softc *sc, struct mbuf *m) 832 { 833 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 834 struct mbuf *n; 835 u_int len, totlen = 0; 836 u_char *buff; 837 838 buff = sc->sc_txbuf; 839 840 for (; m; m = n) { 841 u_char *data = mtod(m, u_char *); 842 len = m->m_len; 843 totlen += len; 844 bcopy(data, buff, len); 845 buff += len; 846 n = m_free(m); 847 } 848 849 if (totlen > PAGE_SIZE) 850 panic("%s: maceput: packet overflow", sc->sc_dev.dv_xname); 851 852 #if 0 853 if (totlen < ETHERMIN + sizeof(struct ether_header)) { 854 int pad = ETHERMIN + sizeof(struct ether_header) - totlen; 855 bzero(sc->sc_txbuf + totlen, pad); 856 totlen = ETHERMIN + sizeof(struct ether_header); 857 } 858 #endif 859 860 861 /* 5 seconds to watch for failing to transmit */ 862 ifp->if_timer = 5; 863 mc_putpacket(sc, totlen); 864 return (totlen); 865 } 866 867 void 868 mace_read(struct mc_softc *sc, caddr_t pkt, int len) 869 { 870 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 871 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 872 struct mbuf *m; 873 874 if (len <= sizeof(struct ether_header) || 875 len > ETHERMTU + sizeof(struct ether_header)) { 876 #ifdef MCDEBUG 877 printf("%s: invalid packet size %d; dropping\n", 878 sc->sc_dev.dv_xname, len); 879 #endif 880 ifp->if_ierrors++; 881 return; 882 } 883 884 m = mace_get(sc, pkt, len); 885 if (m == NULL) { 886 ifp->if_ierrors++; 887 return; 888 } 889 890 ml_enqueue(&ml, m); 891 if_input(ifp, &ml); 892 } 893 894 /* 895 * Pull data off an interface. 896 * Len is length of data, with local net header stripped. 897 * We copy the data into mbufs. When full cluster sized units are present 898 * we copy into clusters. 899 */ 900 struct mbuf * 901 mace_get(struct mc_softc *sc, caddr_t pkt, int totlen) 902 { 903 struct mbuf *m; 904 struct mbuf *top, **mp; 905 int len; 906 907 MGETHDR(m, M_DONTWAIT, MT_DATA); 908 if (m == NULL) 909 return (NULL); 910 911 m->m_pkthdr.len = totlen; 912 len = MHLEN; 913 top = 0; 914 mp = ⊤ 915 916 while (totlen > 0) { 917 if (top) { 918 MGET(m, M_DONTWAIT, MT_DATA); 919 if (m == NULL) { 920 m_freem(top); 921 return (NULL); 922 } 923 len = MLEN; 924 } 925 if (totlen >= MINCLSIZE) { 926 MCLGET(m, M_DONTWAIT); 927 if ((m->m_flags & M_EXT) == 0) { 928 m_free(m); 929 m_freem(top); 930 return (NULL); 931 } 932 len = MCLBYTES; 933 } 934 m->m_len = len = min(totlen, len); 935 bcopy(pkt, mtod(m, caddr_t), len); 936 pkt += len; 937 totlen -= len; 938 *mp = m; 939 mp = &m->m_next; 940 } 941 942 return (top); 943 } 944 945 void 946 mc_putpacket(struct mc_softc *sc, u_int len) 947 { 948 dbdma_command_t *cmd = sc->sc_txdmacmd; 949 950 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, sc->sc_txbuf_pa, 951 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 952 cmd++; 953 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, DBDMA_INT_ALWAYS, 954 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 955 956 dbdma_start(sc->sc_txdma, sc->sc_txdbdma); 957 } 958 959 /* 960 * Interrupt handler for the MACE DMA completion interrupts 961 */ 962 int 963 mc_dmaintr(void *arg) 964 { 965 struct mc_softc *sc = arg; 966 int status, offset, statoff; 967 int datalen, resid; 968 int i, n, count; 969 dbdma_command_t *cmd; 970 971 /* We've received some packets from the MACE */ 972 /* Loop through, processing each of the packets */ 973 i = sc->sc_tail; 974 for (n = 0; n < MC_RXDMABUFS; n++, i++) { 975 if (i == MC_RXDMABUFS) 976 i = 0; 977 978 cmd = &sc->sc_rxdmacmd[i]; 979 status = dbdma_ld16(&cmd->d_status); 980 resid = dbdma_ld16(&cmd->d_resid); 981 982 if ((status & DBDMA_CNTRL_ACTIVE) == 0) { 983 continue; 984 } 985 986 count = dbdma_ld16(&cmd->d_count); 987 datalen = count - resid; 988 datalen -= 4; /* 4 == status bytes */ 989 990 if (datalen < 4 + sizeof(struct ether_header)) { 991 printf("short packet len=%d\n", datalen); 992 /* continue; */ 993 goto next; 994 } 995 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0); 996 997 offset = i * MACE_BUFLEN; 998 statoff = offset + datalen; 999 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[statoff + 0]; 1000 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[statoff + 1]; 1001 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[statoff + 2]; 1002 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[statoff + 3]; 1003 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset; 1004 1005 mc_rint(sc); 1006 1007 next: 1008 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS, 1009 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 1010 1011 cmd->d_status = 0; 1012 cmd->d_resid = 0; 1013 sc->sc_tail = i + 1; 1014 } 1015 1016 dbdma_continue(sc->sc_rxdma); 1017 1018 return 1; 1019 } 1020 1021 void 1022 mc_reset_rxdma(struct mc_softc *sc) 1023 { 1024 dbdma_command_t *cmd = sc->sc_rxdmacmd; 1025 int i; 1026 u_int8_t maccc; 1027 1028 /* Disable receiver, reset the DMA channels */ 1029 maccc = NIC_GET(sc, MACE_MACCC); 1030 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV); 1031 1032 dbdma_reset(sc->sc_rxdma); 1033 1034 bzero(sc->sc_rxdmacmd, 8 * sizeof(dbdma_command_t)); 1035 for (i = 0; i < MC_RXDMABUFS; i++) { 1036 DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, MACE_BUFLEN, 1037 sc->sc_rxbuf_pa + MACE_BUFLEN * i, DBDMA_INT_ALWAYS, 1038 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 1039 cmd++; 1040 } 1041 1042 DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0, 1043 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS); 1044 dbdma_st32(&cmd->d_cmddep, sc->sc_rxdbdma->d_paddr); 1045 cmd++; 1046 1047 sc->sc_tail = 0; 1048 1049 dbdma_start(sc->sc_rxdma, sc->sc_rxdbdma); 1050 /* Reenable receiver, reenable DMA */ 1051 NIC_PUT(sc, MACE_MACCC, maccc); 1052 } 1053 1054 void 1055 mc_reset_txdma(struct mc_softc *sc) 1056 { 1057 dbdma_command_t *cmd = sc->sc_txdmacmd; 1058 dbdma_regmap_t *dmareg = sc->sc_txdma; 1059 u_int8_t maccc; 1060 1061 /* disable transmitter */ 1062 maccc = NIC_GET(sc, MACE_MACCC); 1063 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT); 1064 1065 dbdma_reset(sc->sc_txdma); 1066 1067 bzero(sc->sc_txdmacmd, 2 * sizeof(dbdma_command_t)); 1068 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, 0, sc->sc_txbuf_pa, 1069 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 1070 cmd++; 1071 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 1072 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 1073 1074 out32rb(&dmareg->d_cmdptrhi, 0); 1075 out32rb(&dmareg->d_cmdptrlo, sc->sc_txdbdma->d_paddr); 1076 1077 /* restore old value */ 1078 NIC_PUT(sc, MACE_MACCC, maccc); 1079 } 1080 1081 /* 1082 * Go through the list of multicast addresses and calculate the logical 1083 * address filter. 1084 */ 1085 void 1086 mace_calcladrf(struct mc_softc *sc, u_int8_t *af) 1087 { 1088 struct ether_multi *enm; 1089 u_int32_t crc; 1090 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1091 struct arpcom *ac = &sc->sc_arpcom; 1092 struct ether_multistep step; 1093 /* 1094 * Set up multicast address filter by passing all multicast addresses 1095 * through a crc generator, and then using the high order 6 bits as an 1096 * index into the 64 bit logical address filter. The high order bit 1097 * selects the word, while the rest of the bits select the bit within 1098 * the word. 1099 */ 1100 1101 if (ac->ac_multirangecnt > 0) 1102 goto allmulti; 1103 1104 *((u_int32_t *)af) = *((u_int32_t *)af + 1) = 0; 1105 ETHER_FIRST_MULTI(step, ac, enm); 1106 while (enm != NULL) { 1107 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1108 1109 /* Just want the 6 most significant bits. */ 1110 crc >>= 26; 1111 1112 /* Set the corresponding bit in the filter. */ 1113 af[crc >> 3] |= 1 << (crc & 7); 1114 1115 ETHER_NEXT_MULTI(step, enm); 1116 } 1117 ifp->if_flags &= ~IFF_ALLMULTI; 1118 return; 1119 1120 allmulti: 1121 ifp->if_flags |= IFF_ALLMULTI; 1122 *((u_int32_t *)af) = *((u_int32_t *)af + 1) = 0xffffffff; 1123 } 1124