1 /* $OpenBSD: bonito.c,v 1.31 2016/03/06 19:42:27 mpi Exp $ */ 2 /* $NetBSD: bonito_mainbus.c,v 1.11 2008/04/28 20:23:10 martin Exp $ */ 3 /* $NetBSD: bonito_pci.c,v 1.5 2008/04/28 20:23:28 martin Exp $ */ 4 5 /* 6 * Copyright (c) 2009, 2010 Miodrag Vallat. 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 /*- 21 * Copyright (c) 2001 The NetBSD Foundation, Inc. 22 * All rights reserved. 23 * 24 * This code is derived from software contributed to The NetBSD Foundation 25 * by Jason R. Thorpe. 26 * 27 * Redistribution and use in source and binary forms, with or without 28 * modification, are permitted provided that the following conditions 29 * are met: 30 * 1. Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * 2. Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in the 34 * documentation and/or other materials provided with the distribution. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 38 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 39 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 40 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 41 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 42 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 43 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 44 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 45 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 46 * POSSIBILITY OF SUCH DAMAGE. 47 */ 48 49 /* 50 * PCI configuration space support for the Loongson PCI and memory controller 51 * chip, which is derived from the Algorithmics BONITO chip. 52 */ 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/device.h> 57 #include <sys/extent.h> 58 #include <sys/malloc.h> 59 60 #include <machine/autoconf.h> 61 #include <machine/bus.h> 62 #include <machine/cpu.h> 63 #include <mips64/mips_cpu.h> 64 #include <machine/intr.h> 65 66 #include <dev/pci/pcidevs.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/ppbreg.h> 70 71 #include <loongson/dev/bonitoreg.h> 72 #include <loongson/dev/bonitovar.h> 73 #include <loongson/dev/bonito_irq.h> 74 75 #include <uvm/uvm_extern.h> 76 77 #if 0 78 #define BONITO_DEBUG 79 #endif 80 81 int bonito_match(struct device *, void *, void *); 82 void bonito_attach(struct device *, struct device *, void *); 83 84 const struct cfattach bonito_ca = { 85 sizeof(struct bonito_softc), bonito_match, bonito_attach 86 }; 87 88 struct cfdriver bonito_cd = { 89 NULL, "bonito", DV_DULL 90 }; 91 92 #define wbflush() mips_sync() 93 94 bus_addr_t bonito_pa_to_device(paddr_t); 95 paddr_t bonito_device_to_pa(bus_addr_t); 96 97 void bonito_intr_makemasks(void); 98 uint32_t bonito_intr_2e(uint32_t, struct trapframe *); 99 uint32_t bonito_intr_2f(uint32_t, struct trapframe *); 100 void bonito_intr_dispatch(uint64_t, int, struct trapframe *); 101 102 void bonito_attach_hook(struct device *, struct device *, 103 struct pcibus_attach_args *); 104 int bonito_bus_maxdevs(void *, int); 105 pcitag_t bonito_make_tag(void *, int, int, int); 106 void bonito_decompose_tag(void *, pcitag_t, int *, int *, int *); 107 int bonito_conf_size(void *, pcitag_t); 108 pcireg_t bonito_conf_read(void *, pcitag_t, int); 109 pcireg_t bonito_conf_read_internal(const struct bonito_config *, pcitag_t, int); 110 void bonito_conf_write(void *, pcitag_t, int, pcireg_t); 111 int bonito_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 112 const char * 113 bonito_pci_intr_string(void *, pci_intr_handle_t); 114 void *bonito_pci_intr_establish(void *, pci_intr_handle_t, int, 115 int (*)(void *), void *, char *); 116 void bonito_pci_intr_disestablish(void *, void *); 117 118 int bonito_conf_addr(const struct bonito_config *, pcitag_t, int, 119 u_int32_t *, u_int32_t *); 120 121 void bonito_splx(int); 122 123 /* 124 * Bonito interrupt handling declarations. 125 * See <loongson/dev/bonito_irq.h> for details. 126 */ 127 struct intrhand *bonito_intrhand[BONITO_NINTS]; 128 uint64_t bonito_intem; 129 uint64_t bonito_imask[NIPLS]; 130 131 struct machine_bus_dma_tag bonito_bus_dma_tag = { 132 ._dmamap_create = _dmamap_create, 133 ._dmamap_destroy = _dmamap_destroy, 134 ._dmamap_load = _dmamap_load, 135 ._dmamap_load_mbuf = _dmamap_load_mbuf, 136 ._dmamap_load_uio = _dmamap_load_uio, 137 ._dmamap_load_raw = _dmamap_load_raw, 138 ._dmamap_load_buffer = _dmamap_load_buffer, 139 ._dmamap_unload = _dmamap_unload, 140 ._dmamap_sync = _dmamap_sync, 141 142 ._dmamem_alloc = _dmamem_alloc, 143 ._dmamem_free = _dmamem_free, 144 ._dmamem_map = _dmamem_map, 145 ._dmamem_unmap = _dmamem_unmap, 146 ._dmamem_mmap = _dmamem_mmap, 147 148 ._pa_to_device = bonito_pa_to_device, 149 ._device_to_pa = bonito_device_to_pa 150 }; 151 152 int bonito_io_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 153 bus_space_handle_t *); 154 int bonito_mem_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 155 bus_space_handle_t *); 156 157 struct mips_bus_space bonito_pci_io_space_tag = { 158 .bus_base = PHYS_TO_XKPHYS(BONITO_PCIIO_BASE, CCA_NC), 159 ._space_read_1 = generic_space_read_1, 160 ._space_write_1 = generic_space_write_1, 161 ._space_read_2 = generic_space_read_2, 162 ._space_write_2 = generic_space_write_2, 163 ._space_read_4 = generic_space_read_4, 164 ._space_write_4 = generic_space_write_4, 165 ._space_read_8 = generic_space_read_8, 166 ._space_write_8 = generic_space_write_8, 167 ._space_read_raw_2 = generic_space_read_raw_2, 168 ._space_write_raw_2 = generic_space_write_raw_2, 169 ._space_read_raw_4 = generic_space_read_raw_4, 170 ._space_write_raw_4 = generic_space_write_raw_4, 171 ._space_read_raw_8 = generic_space_read_raw_8, 172 ._space_write_raw_8 = generic_space_write_raw_8, 173 ._space_map = bonito_io_map, 174 ._space_unmap = generic_space_unmap, 175 ._space_subregion = generic_space_region, 176 ._space_vaddr = generic_space_vaddr, 177 ._space_mmap = generic_space_mmap 178 }; 179 180 struct mips_bus_space bonito_pci_mem_space_tag = { 181 .bus_base = PHYS_TO_XKPHYS(0, CCA_NC), 182 ._space_read_1 = generic_space_read_1, 183 ._space_write_1 = generic_space_write_1, 184 ._space_read_2 = generic_space_read_2, 185 ._space_write_2 = generic_space_write_2, 186 ._space_read_4 = generic_space_read_4, 187 ._space_write_4 = generic_space_write_4, 188 ._space_read_8 = generic_space_read_8, 189 ._space_write_8 = generic_space_write_8, 190 ._space_read_raw_2 = generic_space_read_raw_2, 191 ._space_write_raw_2 = generic_space_write_raw_2, 192 ._space_read_raw_4 = generic_space_read_raw_4, 193 ._space_write_raw_4 = generic_space_write_raw_4, 194 ._space_read_raw_8 = generic_space_read_raw_8, 195 ._space_write_raw_8 = generic_space_write_raw_8, 196 ._space_map = bonito_mem_map, 197 ._space_unmap = generic_space_unmap, 198 ._space_subregion = generic_space_region, 199 ._space_vaddr = generic_space_vaddr, 200 ._space_mmap = generic_space_mmap 201 }; 202 203 int 204 bonito_match(struct device *parent, void *vcf, void *aux) 205 { 206 struct mainbus_attach_args *maa = aux; 207 208 if (loongson_ver >= 0x3a) 209 return (0); 210 211 if (strcmp(maa->maa_name, bonito_cd.cd_name) == 0) 212 return (1); 213 214 return (0); 215 } 216 217 void 218 bonito_attach(struct device *parent, struct device *self, void *aux) 219 { 220 struct bonito_softc *sc = (struct bonito_softc *)self; 221 struct pcibus_attach_args pba; 222 pci_chipset_tag_t pc = &sc->sc_pc; 223 const struct bonito_config *bc; 224 uint32_t reg; 225 226 /* 227 * Loongson 2F processors do not use a real Bonito64 chip but 228 * their own derivative, which is no longer 100% compatible. 229 * We need to make sure we never try to access an unimplemented 230 * register... 231 */ 232 if (loongson_ver >= 0x2f) 233 sc->sc_compatible = 0; 234 else 235 sc->sc_compatible = 1; 236 237 reg = PCI_REVISION(REGVAL(BONITO_PCI_REG(PCI_CLASS_REG))); 238 if (sc->sc_compatible) { 239 printf(": BONITO Memory and PCI controller, %s rev %d.%d\n", 240 BONITO_REV_FPGA(reg) ? "FPGA" : "ASIC", 241 BONITO_REV_MAJOR(reg), BONITO_REV_MINOR(reg)); 242 } else { 243 printf(": memory and PCI-X controller, rev %d\n", 244 PCI_REVISION(REGVAL(BONITO_PCI_REG(PCI_CLASS_REG)))); 245 } 246 247 bc = sys_platform->bonito_config; 248 sc->sc_bonito = bc; 249 SLIST_INIT(&sc->sc_hook); 250 251 #ifdef BONITO_DEBUG 252 if (!sc->sc_compatible) 253 printf("ISR4C: %08x\n", REGVAL(BONITO_PCI_REG(0x4c))); 254 printf("PCIMAP: %08x\n", REGVAL(BONITO_PCIMAP)); 255 printf("MEMWIN: %08x.%08x - %08x.%08x\n", 256 REGVAL(BONITO_MEM_WIN_BASE_H), REGVAL(BONITO_MEM_WIN_BASE_L), 257 REGVAL(BONITO_MEM_WIN_MASK_H), REGVAL(BONITO_MEM_WIN_MASK_L)); 258 if (!sc->sc_compatible) { 259 printf("HITSEL0: %08x.%08x\n", 260 REGVAL(LOONGSON_PCI_HIT0_SEL_H), 261 REGVAL(LOONGSON_PCI_HIT0_SEL_L)); 262 printf("HITSEL1: %08x.%08x\n", 263 REGVAL(LOONGSON_PCI_HIT1_SEL_H), 264 REGVAL(LOONGSON_PCI_HIT1_SEL_L)); 265 printf("HITSEL2: %08x.%08x\n", 266 REGVAL(LOONGSON_PCI_HIT2_SEL_H), 267 REGVAL(LOONGSON_PCI_HIT2_SEL_L)); 268 } 269 printf("PCI BAR 0:%08x 1:%08x 2:%08x 3:%08x 4:%08x 5:%08x\n", 270 REGVAL(BONITO_PCI_REG(PCI_MAPREG_START + 0 * 4)), 271 REGVAL(BONITO_PCI_REG(PCI_MAPREG_START + 1 * 4)), 272 REGVAL(BONITO_PCI_REG(PCI_MAPREG_START + 2 * 4)), 273 REGVAL(BONITO_PCI_REG(PCI_MAPREG_START + 3 * 4)), 274 REGVAL(BONITO_PCI_REG(PCI_MAPREG_START + 4 * 4)), 275 REGVAL(BONITO_PCI_REG(PCI_MAPREG_START + 5 * 4))); 276 #endif 277 278 /* 279 * Setup proper abitration. 280 */ 281 282 if (!sc->sc_compatible) { 283 /* 284 * According to Linux, changing the value of this register 285 * ``avoids deadlock of PCI reading/writing lock operation''. 286 * 287 * Unfortunately, documentation for the Implementation 288 * Specific Registers (ISR40 to ISR5C) is only found in the 289 * chinese version of the Loongson 2F documentation. 290 * 291 * The particular bit we set here is ``mas_read_defer''. 292 */ 293 /* c2000001 -> d2000001 */ 294 REGVAL(BONITO_PCI_REG(0x4c)) |= 0x10000000; 295 296 /* all pci devices may need to hold the bus */ 297 reg = REGVAL(LOONGSON_PXARB_CFG); 298 reg &= ~LOONGSON_PXARB_RUDE_DEV_MSK; 299 reg |= 0xfe << LOONGSON_PXARB_RUDE_DEV_SHFT; 300 REGVAL(LOONGSON_PXARB_CFG) = reg; 301 (void)REGVAL(LOONGSON_PXARB_CFG); 302 } 303 304 /* 305 * Setup interrupt handling. 306 */ 307 308 REGVAL(BONITO_GPIOIE) = bc->bc_gpioIE; 309 REGVAL(BONITO_INTEDGE) = bc->bc_intEdge; 310 if (sc->sc_compatible) 311 REGVAL(BONITO_INTSTEER) = bc->bc_intSteer; 312 REGVAL(BONITO_INTPOL) = bc->bc_intPol; 313 314 REGVAL(BONITO_INTENCLR) = 0xffffffff; 315 (void)REGVAL(BONITO_INTENCLR); 316 317 if (sc->sc_compatible) { 318 bonito_intem |= BONITO_INTRMASK_MASTERERR; 319 } 320 321 if (loongson_ver >= 0x2f) 322 set_intr(INTPRI_BONITO, CR_INT_4, bonito_intr_2f); 323 else 324 set_intr(INTPRI_BONITO, CR_INT_0, bonito_intr_2e); 325 register_splx_handler(bonito_splx); 326 327 /* 328 * Attach PCI bus. 329 */ 330 331 pc->pc_conf_v = sc; 332 pc->pc_attach_hook = bonito_attach_hook; 333 pc->pc_bus_maxdevs = bonito_bus_maxdevs; 334 pc->pc_make_tag = bonito_make_tag; 335 pc->pc_decompose_tag = bonito_decompose_tag; 336 pc->pc_conf_size = bonito_conf_size; 337 pc->pc_conf_read = bonito_conf_read; 338 pc->pc_conf_write = bonito_conf_write; 339 340 pc->pc_intr_v = sc; 341 pc->pc_intr_map = bonito_pci_intr_map; 342 pc->pc_intr_string = bonito_pci_intr_string; 343 pc->pc_intr_establish = bonito_pci_intr_establish; 344 pc->pc_intr_disestablish = bonito_pci_intr_disestablish; 345 346 bzero(&pba, sizeof pba); 347 pba.pba_busname = "pci"; 348 pba.pba_iot = &bonito_pci_io_space_tag; 349 pba.pba_memt = &bonito_pci_mem_space_tag; 350 pba.pba_dmat = &bonito_bus_dma_tag; 351 pba.pba_pc = pc; 352 pba.pba_domain = pci_ndomains++; 353 pba.pba_bus = 0; 354 #ifdef notyet 355 pba.pba_ioex = bonito_get_resource_extent(pc, 1); 356 pba.pba_memex = bonito_get_resource_extent(pc, 0); 357 #endif 358 359 config_found(&sc->sc_dev, &pba, bonito_print); 360 } 361 362 bus_addr_t 363 bonito_pa_to_device(paddr_t pa) 364 { 365 return pa ^ loongson_dma_base; 366 } 367 368 paddr_t 369 bonito_device_to_pa(bus_addr_t addr) 370 { 371 return addr ^ loongson_dma_base; 372 } 373 374 int 375 bonito_print(void *aux, const char *pnp) 376 { 377 struct pcibus_attach_args *pba = aux; 378 379 if (pnp) 380 printf("%s at %s", pba->pba_busname, pnp); 381 printf(" bus %d", pba->pba_bus); 382 383 return UNCONF; 384 } 385 386 /* 387 * Bonito interrupt handling 388 */ 389 390 void * 391 bonito_intr_establish(int irq, int type, int level, int (*handler)(void *), 392 void *arg, const char *name) 393 { 394 struct intrhand **p, *q, *ih; 395 int s; 396 397 #ifdef DIAGNOSTIC 398 if (irq >= BONITO_NINTS || irq == BONITO_ISA_IRQ(2) || irq < 0) 399 panic("bonito_intr_establish: illegal irq %d", irq); 400 #endif 401 402 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 403 if (ih == NULL) 404 return NULL; 405 406 ih->ih_next = NULL; 407 ih->ih_fun = handler; 408 ih->ih_arg = arg; 409 ih->ih_level = level; 410 ih->ih_irq = irq; 411 evcount_attach(&ih->ih_count, name, &ih->ih_irq); 412 413 s = splhigh(); 414 415 /* 416 * Figure out where to put the handler. 417 * This is O(N^2), but we want to preserve the order, and N is 418 * generally small. 419 */ 420 for (p = &bonito_intrhand[irq]; (q = *p) != NULL; p = &q->ih_next) 421 ; 422 *p = ih; 423 424 bonito_intem |= 1UL << irq; 425 bonito_intr_makemasks(); 426 427 splx(s); /* causes hw mask update */ 428 429 return (ih); 430 } 431 432 void 433 bonito_intr_disestablish(void *vih) 434 { 435 struct intrhand *ih = (struct intrhand *)vih; 436 struct intrhand **p, *q; 437 int irq = ih->ih_irq; 438 int s; 439 440 #ifdef DIAGNOSTIC 441 if (irq >= BONITO_NINTS || irq == BONITO_ISA_IRQ(2) || irq < 0) 442 panic("bonito_intr_disestablish: illegal irq %d", irq); 443 #endif 444 445 s = splhigh(); 446 447 evcount_detach(&ih->ih_count); 448 449 for (p = &bonito_intrhand[irq]; (q = *p) != NULL; p = &q->ih_next) 450 if (q == ih) 451 break; 452 #ifdef DIAGNOSTIC 453 if (q == NULL) 454 panic("bonito_intr_disestablish: never registered"); 455 #endif 456 *p = ih->ih_next; 457 458 if (ih->ih_next == NULL && p == &bonito_intrhand[irq]) { 459 bonito_intem &= ~(1UL << irq); 460 bonito_intr_makemasks(); 461 /* 462 * No need to clear a bit in INTEN through INTCLR, 463 * splhigh() took care of disabling everything and 464 * splx() will not reenable this source after the 465 * mask update. 466 */ 467 } 468 469 splx(s); 470 471 free(ih, M_DEVBUF, sizeof *ih); 472 } 473 474 /* 475 * Update interrupt masks. This is for designs without legacy PIC. 476 */ 477 478 void 479 bonito_splx(int newipl) 480 { 481 struct cpu_info *ci = curcpu(); 482 483 /* Update masks to new ipl. Order highly important! */ 484 __asm__ (".set noreorder\n"); 485 ci->ci_ipl = newipl; 486 mips_sync(); 487 __asm__ (".set reorder\n"); 488 bonito_setintrmask(newipl); 489 /* If we still have softints pending trigger processing. */ 490 if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT) 491 setsoftintr0(); 492 } 493 494 void 495 bonito_setintrmask(int level) 496 { 497 uint64_t active; 498 uint32_t clear, set; 499 register_t sr; 500 501 active = bonito_intem & ~bonito_imask[level]; 502 /* be sure to mask high bits, there may be other interrupt sources */ 503 clear = BONITO_DIRECT_MASK(bonito_imask[level]); 504 set = BONITO_DIRECT_MASK(active); 505 506 sr = disableintr(); 507 508 if (clear != 0) { 509 REGVAL(BONITO_INTENCLR) = clear; 510 (void)REGVAL(BONITO_INTENCLR); 511 } 512 if (set != 0) { 513 REGVAL(BONITO_INTENSET) = set; 514 (void)REGVAL(BONITO_INTENSET); 515 } 516 517 setsr(sr); 518 } 519 520 /* 521 * Recompute interrupt masks. 522 */ 523 void 524 bonito_intr_makemasks() 525 { 526 int irq, level; 527 struct intrhand *q; 528 uint intrlevel[BONITO_NINTS]; 529 530 /* First, figure out which levels each IRQ uses. */ 531 for (irq = 0; irq < BONITO_NINTS; irq++) { 532 uint levels = 0; 533 for (q = bonito_intrhand[irq]; q != NULL; q = q->ih_next) 534 levels |= 1 << q->ih_level; 535 intrlevel[irq] = levels; 536 } 537 538 /* 539 * Then figure out which IRQs use each level. 540 * Note that we make sure never to overwrite imask[IPL_HIGH], in 541 * case an interrupt occurs during intr_disestablish() and causes 542 * an unfortunate splx() while we are here recomputing the masks. 543 */ 544 for (level = IPL_NONE; level < IPL_HIGH; level++) { 545 uint64_t irqs = 0; 546 for (irq = 0; irq < BONITO_NINTS; irq++) 547 if (intrlevel[irq] & (1 << level)) 548 irqs |= 1UL << irq; 549 bonito_imask[level] = irqs; 550 } 551 552 /* 553 * There are tty, network and disk drivers that use free() at interrupt 554 * time, so vm > (tty | net | bio). 555 * 556 * Enforce a hierarchy that gives slow devices a better chance at not 557 * dropping data. 558 */ 559 bonito_imask[IPL_NET] |= bonito_imask[IPL_BIO]; 560 bonito_imask[IPL_TTY] |= bonito_imask[IPL_NET]; 561 bonito_imask[IPL_VM] |= bonito_imask[IPL_TTY]; 562 bonito_imask[IPL_CLOCK] |= bonito_imask[IPL_VM]; 563 564 /* 565 * These are pseudo-levels. 566 */ 567 bonito_imask[IPL_NONE] = 0; 568 bonito_imask[IPL_HIGH] = -1UL; 569 } 570 571 /* 572 * Process native interrupts 573 */ 574 575 uint32_t 576 bonito_intr_2e(uint32_t hwpend, struct trapframe *frame) 577 { 578 uint64_t imr, isr, mask; 579 580 isr = REGVAL(BONITO_INTISR); 581 582 /* 583 * According to Linux code, Bonito64 - at least on Loongson 584 * systems - triggers an interrupt during DMA, which is to be 585 * ignored. Smells like a chip errata to me. 586 */ 587 while (ISSET(isr, BONITO_INTRMASK_MASTERERR)) { 588 delay(1); 589 isr = REGVAL(BONITO_INTISR); 590 } 591 592 isr &= BONITO_INTRMASK_GPIN; 593 imr = REGVAL(BONITO_INTEN); 594 isr &= imr; 595 #ifdef DEBUG 596 printf("pci interrupt: imr %04x isr %04x\n", imr, isr); 597 #endif 598 if (isr == 0) 599 return 0; /* not for us */ 600 601 /* 602 * Mask all pending interrupts. 603 */ 604 REGVAL(BONITO_INTENCLR) = isr; 605 (void)REGVAL(BONITO_INTENCLR); 606 607 /* 608 * If interrupts are spl-masked, mask them and wait for splx() 609 * to reenable them when necessary. 610 */ 611 if ((mask = isr & bonito_imask[frame->ipl]) != 0) { 612 isr &= ~mask; 613 imr &= ~mask; 614 } 615 616 /* 617 * Now process allowed interrupts. 618 */ 619 if (isr != 0) { 620 bonito_intr_dispatch(isr, 30, frame); 621 622 /* 623 * Reenable interrupts which have been serviced. 624 */ 625 REGVAL(BONITO_INTENSET) = imr; 626 (void)REGVAL(BONITO_INTENSET); 627 } 628 629 return hwpend; 630 } 631 632 uint32_t 633 bonito_intr_2f(uint32_t hwpend, struct trapframe *frame) 634 { 635 uint64_t imr, isr, mask; 636 637 isr = REGVAL(BONITO_INTISR) & LOONGSON_INTRMASK_LVL4; 638 imr = REGVAL(BONITO_INTEN); 639 isr &= imr; 640 #ifdef DEBUG 641 printf("pci interrupt: imr %04x isr %04x\n", imr, isr); 642 #endif 643 if (isr == 0) 644 return 0; /* not for us */ 645 646 /* 647 * Mask all pending interrupts. 648 */ 649 REGVAL(BONITO_INTENCLR) = isr; 650 (void)REGVAL(BONITO_INTENCLR); 651 652 /* 653 * If interrupts are spl-masked, mask them and wait for splx() 654 * to reenable them when necessary. 655 */ 656 if ((mask = isr & bonito_imask[frame->ipl]) != 0) { 657 isr &= ~mask; 658 imr &= ~mask; 659 } 660 661 /* 662 * Now process allowed interrupts. 663 */ 664 if (isr != 0) { 665 bonito_intr_dispatch(isr, 666 LOONGSON_INTR_DRAM_PARERR /* skip non-pci interrupts */, 667 frame); 668 669 /* 670 * Reenable interrupts which have been serviced. 671 */ 672 REGVAL(BONITO_INTENSET) = imr; 673 (void)REGVAL(BONITO_INTENSET); 674 } 675 676 return hwpend; 677 } 678 679 void 680 bonito_intr_dispatch(uint64_t isr, int startbit, struct trapframe *frame) 681 { 682 int lvl, bitno; 683 uint64_t tmpisr, mask; 684 struct intrhand *ih; 685 int rc; 686 687 /* Service higher level interrupts first */ 688 for (lvl = IPL_HIGH - 1; lvl != IPL_NONE; lvl--) { 689 tmpisr = isr & (bonito_imask[lvl] ^ bonito_imask[lvl - 1]); 690 if (tmpisr == 0) 691 continue; 692 for (bitno = startbit, mask = 1UL << bitno; mask != 0; 693 bitno--, mask >>= 1) { 694 if ((tmpisr & mask) == 0) 695 continue; 696 697 rc = 0; 698 for (ih = bonito_intrhand[bitno]; ih != NULL; 699 ih = ih->ih_next) { 700 splraise(ih->ih_level); 701 if ((*ih->ih_fun)(ih->ih_arg) != 0) { 702 rc = 1; 703 ih->ih_count.ec_count++; 704 } 705 __asm__ (".set noreorder\n"); 706 curcpu()->ci_ipl = frame->ipl; 707 mips_sync(); 708 __asm__ (".set reorder\n"); 709 } 710 if (rc == 0) { 711 printf("spurious interrupt %d\n", bitno); 712 #ifdef DEBUG 713 printf("ISR %08x IMR %08x ipl %d mask %08x\n", 714 REGVAL(BONITO_INTISR), REGVAL(BONITO_INTEN), 715 frame->ipl, bonito_imask[frame->ipl]); 716 #ifdef DDB 717 Debugger(); 718 #endif 719 #endif 720 } 721 722 if ((isr ^= mask) == 0) 723 return; 724 if ((tmpisr ^= mask) == 0) 725 break; 726 } 727 } 728 } 729 730 /* 731 * various PCI helpers 732 */ 733 734 void 735 bonito_attach_hook(struct device *parent, struct device *self, 736 struct pcibus_attach_args *pba) 737 { 738 pci_chipset_tag_t pc = pba->pba_pc; 739 struct bonito_softc *sc = pc->pc_conf_v; 740 const struct bonito_config *bc = sc->sc_bonito; 741 742 if (pba->pba_bus != 0) 743 return; 744 745 (*bc->bc_attach_hook)(pc); 746 } 747 748 /* 749 * PCI configuration space access routines 750 */ 751 752 int 753 bonito_bus_maxdevs(void *v, int busno) 754 { 755 struct bonito_softc *sc = v; 756 const struct bonito_config *bc = sc->sc_bonito; 757 758 return busno == 0 ? 32 - bc->bc_adbase : 32; 759 } 760 761 pcitag_t 762 bonito_make_tag(void *unused, int b, int d, int f) 763 { 764 return (b << 16) | (d << 11) | (f << 8); 765 } 766 767 void 768 bonito_decompose_tag(void *unused, pcitag_t tag, int *bp, int *dp, int *fp) 769 { 770 if (bp != NULL) 771 *bp = (tag >> 16) & 0xff; 772 if (dp != NULL) 773 *dp = (tag >> 11) & 0x1f; 774 if (fp != NULL) 775 *fp = (tag >> 8) & 0x7; 776 } 777 778 int 779 bonito_conf_addr(const struct bonito_config *bc, pcitag_t tag, int offset, 780 u_int32_t *cfgoff, u_int32_t *pcimap_cfg) 781 { 782 int b, d, f; 783 784 bonito_decompose_tag(NULL, tag, &b, &d, &f); 785 786 if (b == 0) { 787 d += bc->bc_adbase; 788 if (d > 31) 789 return 1; 790 *cfgoff = (1 << d) | (f << 8) | offset; 791 *pcimap_cfg = 0; 792 } else { 793 *cfgoff = tag | offset; 794 *pcimap_cfg = BONITO_PCIMAPCFG_TYPE1; 795 } 796 797 return 0; 798 } 799 800 /* PCI Configuration Space access hook structure */ 801 struct bonito_cfg_hook { 802 SLIST_ENTRY(bonito_cfg_hook) next; 803 int (*read)(void *, pci_chipset_tag_t, pcitag_t, int, pcireg_t *); 804 int (*write)(void *, pci_chipset_tag_t, pcitag_t, int, pcireg_t); 805 void *cookie; 806 }; 807 808 int 809 bonito_pci_hook(pci_chipset_tag_t pc, void *cookie, 810 int (*r)(void *, pci_chipset_tag_t, pcitag_t, int, pcireg_t *), 811 int (*w)(void *, pci_chipset_tag_t, pcitag_t, int, pcireg_t)) 812 { 813 struct bonito_softc *sc = pc->pc_conf_v; 814 struct bonito_cfg_hook *bch; 815 816 bch = malloc(sizeof *bch, M_DEVBUF, M_NOWAIT); 817 if (bch == NULL) 818 return ENOMEM; 819 820 bch->read = r; 821 bch->write = w; 822 bch->cookie = cookie; 823 SLIST_INSERT_HEAD(&sc->sc_hook, bch, next); 824 return 0; 825 } 826 827 int 828 bonito_conf_size(void *v, pcitag_t tag) 829 { 830 return PCI_CONFIG_SPACE_SIZE; 831 } 832 833 pcireg_t 834 bonito_conf_read(void *v, pcitag_t tag, int offset) 835 { 836 struct bonito_softc *sc = v; 837 struct bonito_cfg_hook *hook; 838 pcireg_t data; 839 840 SLIST_FOREACH(hook, &sc->sc_hook, next) { 841 if (hook->read != NULL && 842 (*hook->read)(hook->cookie, &sc->sc_pc, tag, offset, 843 &data) != 0) 844 return data; 845 } 846 847 return bonito_conf_read_internal(sc->sc_bonito, tag, offset); 848 } 849 850 pcireg_t 851 bonito_conf_read_internal(const struct bonito_config *bc, pcitag_t tag, 852 int offset) 853 { 854 pcireg_t data; 855 u_int32_t cfgoff, pcimap_cfg; 856 register_t sr; 857 uint64_t imr; 858 859 if (bonito_conf_addr(bc, tag, offset, &cfgoff, &pcimap_cfg)) 860 return (pcireg_t)-1; 861 862 sr = disableintr(); 863 imr = REGVAL(BONITO_INTEN); 864 REGVAL(BONITO_INTENCLR) = 0xffffffff; 865 (void)REGVAL(BONITO_INTENCLR); 866 867 /* clear aborts */ 868 REGVAL(BONITO_PCI_REG(PCI_COMMAND_STATUS_REG)) |= 869 PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT; 870 871 /* high 16 bits of address go into PciMapCfg register */ 872 REGVAL(BONITO_PCIMAP_CFG) = (cfgoff >> 16) | pcimap_cfg; 873 (void)REGVAL(BONITO_PCIMAP_CFG); 874 wbflush(); 875 876 /* low 16 bits of address are offset into config space */ 877 data = REGVAL(BONITO_PCICFG_BASE + (cfgoff & 0xfffc)); 878 879 /* check for error */ 880 if (REGVAL(BONITO_PCI_REG(PCI_COMMAND_STATUS_REG)) & 881 (PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT)) { 882 REGVAL(BONITO_PCI_REG(PCI_COMMAND_STATUS_REG)) |= 883 PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT; 884 data = (pcireg_t) -1; 885 } 886 887 REGVAL(BONITO_INTENSET) = imr; 888 (void)REGVAL(BONITO_INTENSET); 889 setsr(sr); 890 891 return data; 892 } 893 894 void 895 bonito_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data) 896 { 897 struct bonito_softc *sc = v; 898 u_int32_t cfgoff, pcimap_cfg; 899 struct bonito_cfg_hook *hook; 900 register_t sr; 901 uint64_t imr; 902 903 SLIST_FOREACH(hook, &sc->sc_hook, next) { 904 if (hook->write != NULL && 905 (*hook->write)(hook->cookie, &sc->sc_pc, tag, offset, 906 data) != 0) 907 return; 908 } 909 910 if (bonito_conf_addr(sc->sc_bonito, tag, offset, &cfgoff, &pcimap_cfg)) 911 panic("bonito_conf_write"); 912 913 sr = disableintr(); 914 imr = REGVAL(BONITO_INTEN); 915 REGVAL(BONITO_INTENCLR) = 0xffffffff; 916 (void)REGVAL(BONITO_INTENCLR); 917 918 /* clear aborts */ 919 REGVAL(BONITO_PCI_REG(PCI_COMMAND_STATUS_REG)) |= 920 PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT; 921 922 /* high 16 bits of address go into PciMapCfg register */ 923 REGVAL(BONITO_PCIMAP_CFG) = (cfgoff >> 16) | pcimap_cfg; 924 (void)REGVAL(BONITO_PCIMAP_CFG); 925 wbflush(); 926 927 /* low 16 bits of address are offset into config space */ 928 REGVAL(BONITO_PCICFG_BASE + (cfgoff & 0xfffc)) = data; 929 930 REGVAL(BONITO_INTENSET) = imr; 931 (void)REGVAL(BONITO_INTENSET); 932 setsr(sr); 933 } 934 935 /* 936 * PCI Interrupt handling 937 */ 938 939 int 940 bonito_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 941 { 942 struct bonito_softc *sc = pa->pa_pc->pc_intr_v; 943 const struct bonito_config *bc = sc->sc_bonito; 944 int bus, dev, fn, pin; 945 946 *ihp = (pci_intr_handle_t)-1; 947 948 if (pa->pa_intrpin == 0) /* no interrupt needed */ 949 return 1; 950 951 #ifdef DIAGNOSTIC 952 if (pa->pa_intrpin > 4) { 953 printf("%s: bad interrupt pin %d\n", __func__, pa->pa_intrpin); 954 return 1; 955 } 956 #endif 957 958 pci_decompose_tag(pa->pa_pc, pa->pa_tag, &bus, &dev, &fn); 959 if (pa->pa_bridgetag) { 960 pin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin, dev); 961 *ihp = pa->pa_bridgeih[pin - 1]; 962 } else { 963 if (bus == 0) 964 *ihp = (*bc->bc_intr_map)(dev, fn, pa->pa_intrpin); 965 966 if (*ihp == (pci_intr_handle_t)-1) 967 return 1; 968 } 969 970 return 0; 971 } 972 973 const char * 974 bonito_pci_intr_string(void *cookie, pci_intr_handle_t ih) 975 { 976 static char irqstr[1 + 12]; 977 978 if (BONITO_IRQ_IS_ISA(ih)) 979 snprintf(irqstr, sizeof irqstr, "isa irq %lu", 980 BONITO_IRQ_TO_ISA(ih)); 981 else 982 snprintf(irqstr, sizeof irqstr, "irq %lu", ih); 983 return irqstr; 984 } 985 986 void * 987 bonito_pci_intr_establish(void *cookie, pci_intr_handle_t ih, int level, 988 int (*cb)(void *), void *cbarg, char *name) 989 { 990 return bonito_intr_establish(ih, IST_LEVEL, level, cb, cbarg, name); 991 } 992 993 void 994 bonito_pci_intr_disestablish(void *cookie, void *ihp) 995 { 996 bonito_intr_disestablish(ihp); 997 } 998 999 /* 1000 * bus_space mapping routines. 1001 */ 1002 1003 /* 1004 * Legacy I/O access protection. 1005 * Since MI ISA code does not expect bus access to cause any failure when 1006 * accessing missing hardware, but only receive bogus data in return, we 1007 * force bus_space_map() to fail if there is no hardware there. 1008 */ 1009 1010 int 1011 bonito_io_map(bus_space_tag_t t, bus_addr_t offs, bus_size_t size, int flags, 1012 bus_space_handle_t *bshp) 1013 { 1014 const struct legacy_io_range *r; 1015 bus_addr_t rend; 1016 1017 if (offs < BONITO_PCIIO_LEGACY) { 1018 if ((r = sys_platform->legacy_io_ranges) == NULL) 1019 return ENXIO; 1020 1021 rend = offs + size - 1; 1022 for (; r->start != 0; r++) 1023 if (offs >= r->start && rend <= r->end) 1024 break; 1025 1026 if (r->end == 0) 1027 return ENXIO; 1028 } 1029 1030 *bshp = t->bus_base + offs; 1031 return 0; 1032 } 1033 1034 /* 1035 * PCI memory access. 1036 * Things are a bit complicated here, as we can either use one of the 64MB 1037 * windows in PCILO space (making sure ranges spanning multiple windows will 1038 * turn contiguous), or a direct access within the PCIHI space. 1039 * Note that, on 2F systems, only the PCIHI range for which CPU->PCI accesses 1040 * are enabled in the crossbar is usable. 1041 */ 1042 1043 int 1044 bonito_mem_map(bus_space_tag_t t, bus_addr_t offs, bus_size_t size, int flags, 1045 bus_space_handle_t *bshp) 1046 { 1047 uint32_t pcimap; 1048 bus_addr_t pcilo_w[3]; 1049 bus_addr_t ws, we, w; 1050 bus_addr_t end = offs + size - 1; 1051 int pcilo_window; 1052 1053 pcimap = REGVAL(BONITO_PCIMAP); 1054 1055 /* 1056 * Try a PCIHI mapping first. 1057 */ 1058 1059 if (loongson_ver >= 0x2f) { 1060 if (offs >= LS2F_PCIHI_BASE && end <= LS2F_PCIHI_TOP) { 1061 *bshp = t->bus_base + offs; 1062 return 0; 1063 } 1064 } else { 1065 /* 1066 * Only try HI space if we do not have memory setup there. 1067 */ 1068 if (physmem <= atop(BONITO_PCILO_BASE)) { 1069 /* PCI1.5 */ 1070 if (offs >= BONITO_PCIHI_BASE && 1071 end <= BONITO_PCIHI_TOP) { 1072 *bshp = t->bus_base + offs; 1073 return 0; 1074 } 1075 1076 /* PCI2 */ 1077 w = pcimap & BONITO_PCIMAP_PCIMAP_2 ? 0x80000000UL : 0; 1078 if (offs >= w && end < (w + 0x80000000UL)) { 1079 *bshp = t->bus_base + 0x80000000UL + (offs - w); 1080 return 0; 1081 } 1082 } 1083 } 1084 1085 /* 1086 * No luck, try a PCILO mapping. 1087 */ 1088 1089 /* 1090 * Decode PCIMAP, and figure out what PCILO mappings are 1091 * possible. 1092 */ 1093 1094 pcilo_w[0] = (pcimap & BONITO_PCIMAP_PCIMAP_LO0) >> 1095 BONITO_PCIMAP_PCIMAP_LO0_SHIFT; 1096 pcilo_w[1] = (pcimap & BONITO_PCIMAP_PCIMAP_LO1) >> 1097 BONITO_PCIMAP_PCIMAP_LO1_SHIFT; 1098 pcilo_w[2] = (pcimap & BONITO_PCIMAP_PCIMAP_LO2) >> 1099 BONITO_PCIMAP_PCIMAP_LO2_SHIFT; 1100 1101 /* 1102 * Check if the 64MB areas we want to span are all available as 1103 * contiguous PCILO mappings. 1104 */ 1105 1106 ws = offs >> 26; 1107 we = end >> 26; 1108 1109 pcilo_window = -1; 1110 if (ws == pcilo_w[0]) 1111 pcilo_window = 0; 1112 else if (ws == pcilo_w[1]) 1113 pcilo_window = 1; 1114 else if (ws == pcilo_w[2]) 1115 pcilo_window = 2; 1116 1117 if (pcilo_window >= 0) { 1118 /* contiguous area test */ 1119 for (w = ws + 1; w <= we; w++) { 1120 if (pcilo_window + (w - ws) > 2 || 1121 w != pcilo_w[pcilo_window + (w - ws)]) { 1122 pcilo_window = -1; 1123 break; 1124 } 1125 } 1126 } 1127 1128 if (pcilo_window >= 0) { 1129 *bshp = t->bus_base + BONITO_PCILO_BASE + 1130 BONITO_PCIMAP_WINBASE(pcilo_window) + 1131 BONITO_PCIMAP_WINOFFSET(offs); 1132 return 0; 1133 } 1134 1135 return EINVAL; 1136 } 1137 1138 /* 1139 * PCI resource handling 1140 */ 1141 1142 struct extent * 1143 bonito_get_resource_extent(pci_chipset_tag_t pc, int io) 1144 { 1145 struct bonito_softc *sc = pc->pc_conf_v; 1146 struct extent *ex; 1147 char *exname; 1148 size_t exnamesz; 1149 uint32_t reg; 1150 int errors; 1151 1152 exnamesz = 1 + 16 + 4; 1153 exname = (char *)malloc(exnamesz, M_DEVBUF, M_NOWAIT); 1154 if (exname == NULL) 1155 return NULL; 1156 snprintf(exname, exnamesz, "%s%s", sc->sc_dev.dv_xname, 1157 io ? "_io" : "_mem"); 1158 1159 ex = extent_create(exname, 0, 0xffffffff, M_DEVBUF, NULL, 0, 1160 EX_NOWAIT | EX_FILLED); 1161 if (ex == NULL) 1162 goto out; 1163 1164 errors = 0; 1165 if (io) { 1166 /* 1167 * Reserve the low 16KB of I/O space to the legacy hardware, 1168 * if any. 1169 */ 1170 if (extent_free(ex, BONITO_PCIIO_LEGACY, BONITO_PCIIO_SIZE, 1171 EX_NOWAIT) != 0) 1172 errors++; 1173 } else { 1174 reg = REGVAL(BONITO_PCIMAP); 1175 if (extent_free(ex, 1176 BONITO_PCIMAP_WINBASE((reg & BONITO_PCIMAP_PCIMAP_LO0) >> 1177 BONITO_PCIMAP_PCIMAP_LO0_SHIFT), 1178 BONITO_PCIMAP_WINSIZE, EX_NOWAIT) != 0) 1179 errors++; 1180 if (extent_free(ex, 1181 BONITO_PCIMAP_WINBASE((reg & BONITO_PCIMAP_PCIMAP_LO1) >> 1182 BONITO_PCIMAP_PCIMAP_LO1_SHIFT), 1183 BONITO_PCIMAP_WINSIZE, EX_NOWAIT) != 0) 1184 errors++; 1185 if (extent_free(ex, 1186 BONITO_PCIMAP_WINBASE((reg & BONITO_PCIMAP_PCIMAP_LO2) >> 1187 BONITO_PCIMAP_PCIMAP_LO2_SHIFT), 1188 BONITO_PCIMAP_WINSIZE, EX_NOWAIT) != 0) 1189 errors++; 1190 1191 if (sc->sc_compatible) { 1192 /* XXX make PCIMAP_HI available if PCIMAP_2 set */ 1193 } 1194 } 1195 1196 if (errors != 0) { 1197 extent_destroy(ex); 1198 ex = NULL; 1199 } 1200 1201 #ifdef BONITO_DEBUG 1202 extent_print(ex); 1203 #endif 1204 1205 out: 1206 free(exname, M_DEVBUF, exnamesz); 1207 1208 return ex; 1209 } 1210 1211 /* 1212 * Functions used during early system configuration (before bonito attaches). 1213 */ 1214 1215 pcitag_t bonito_make_tag_early(int, int, int); 1216 pcireg_t bonito_conf_read_early(pcitag_t, int); 1217 1218 pcitag_t 1219 bonito_make_tag_early(int b, int d, int f) 1220 { 1221 return bonito_make_tag(NULL, b, d, f); 1222 } 1223 1224 pcireg_t 1225 bonito_conf_read_early(pcitag_t tag, int reg) 1226 { 1227 return bonito_conf_read_internal(sys_platform->bonito_config, tag, reg); 1228 } 1229 1230 void 1231 bonito_early_setup() 1232 { 1233 pci_make_tag_early = bonito_make_tag_early; 1234 pci_conf_read_early = bonito_conf_read_early; 1235 1236 early_mem_t = &bonito_pci_mem_space_tag; 1237 early_io_t = &bonito_pci_io_space_tag; 1238 } 1239