xref: /openbsd-src/sys/arch/i386/pci/piix.c (revision b2ea75c1b17e1a9a339660e7ed45cd24946b230e)
1 /*	$OpenBSD: piix.c,v 1.5 2001/01/25 00:07:40 mickey Exp $	*/
2 /*	$NetBSD: piix.c,v 1.1 1999/11/17 01:21:20 thorpej Exp $	*/
3 
4 /*-
5  * Copyright (c) 1999 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to The NetBSD Foundation
9  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10  * NASA Ames Research Center.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  * 3. All advertising materials mentioning features or use of this software
21  *    must display the following acknowledgement:
22  *	This product includes software developed by the NetBSD
23  *	Foundation, Inc. and its contributors.
24  * 4. Neither the name of The NetBSD Foundation nor the names of its
25  *    contributors may be used to endorse or promote products derived
26  *    from this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 /*
42  * Copyright (c) 1999, by UCHIYAMA Yasushi
43  * All rights reserved.
44  *
45  * Redistribution and use in source and binary forms, with or without
46  * modification, are permitted provided that the following conditions
47  * are met:
48  * 1. Redistributions of source code must retain the above copyright
49  *    notice, this list of conditions and the following disclaimer.
50  * 2. The name of the developer may NOT be used to endorse or promote products
51  *    derived from this software without specific prior written permission.
52  *
53  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
54  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
55  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
56  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
57  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
58  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
59  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
63  * SUCH DAMAGE.
64  */
65 
66 /*
67  * Support for the Intel PIIX PCI-ISA bridge interrupt controller.
68  */
69 
70 #include <sys/param.h>
71 #include <sys/systm.h>
72 #include <sys/device.h>
73 #include <sys/malloc.h>
74 
75 #include <machine/intr.h>
76 #include <machine/bus.h>
77 
78 #include <dev/pci/pcivar.h>
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcidevs.h>
81 
82 #include <i386/pci/pcibiosvar.h>
83 #include <i386/pci/piixreg.h>
84 #include <i386/pci/piixvar.h>
85 
86 #ifdef PIIX_DEBUG
87 #define	DPRINTF(arg) printf arg
88 #else
89 #define	DPRINTF(arg)
90 #endif
91 
92 int	piix_getclink __P((pciintr_icu_handle_t, int, int *));
93 int	piix_get_intr __P((pciintr_icu_handle_t, int, int *));
94 int	piix_set_intr __P((pciintr_icu_handle_t, int, int));
95 #ifdef PIIX_DEBUG
96 void	piix_pir_dump __P((struct piix_handle *));
97 #endif
98 
99 const struct pciintr_icu piix_pci_icu = {
100 	piix_getclink,
101 	piix_get_intr,
102 	piix_set_intr,
103 	piix_get_trigger,
104 	piix_set_trigger,
105 };
106 
107 int
108 piix_init(pc, iot, tag, ptagp, phandp)
109 	pci_chipset_tag_t pc;
110 	bus_space_tag_t iot;
111 	pcitag_t tag;
112 	pciintr_icu_tag_t *ptagp;
113 	pciintr_icu_handle_t *phandp;
114 {
115 	struct piix_handle *ph;
116 
117 	ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT);
118 	if (ph == NULL)
119 		return (1);
120 
121 	ph->ph_iot = iot;
122 	ph->ph_pc = pc;
123 	ph->ph_tag = tag;
124 
125 	if (bus_space_map(iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0,
126 	    &ph->ph_elcr_ioh) != 0) {
127 		free(ph, M_DEVBUF);
128 		return (1);
129 	}
130 
131 #ifdef PIIX_DEBUG
132 	piix_pir_dump(ph);
133 #endif
134 	*ptagp = &piix_pci_icu;
135 	*phandp = ph;
136 	return (0);
137 }
138 
139 int
140 piix_getclink(v, link, clinkp)
141 	pciintr_icu_handle_t v;
142 	int link, *clinkp;
143 {
144 	DPRINTF(("PIIX link value 0x%x: ", link));
145 
146 	/* Pattern 1: simple. */
147 	if (PIIX_LEGAL_LINK(link - 1)) {
148 		*clinkp = link - 1;
149 		DPRINTF(("PIRQ %d (simple)\n", *clinkp));
150 		return (0);
151 	}
152 
153 	/* Pattern 2: configuration register offset */
154 	if (link >= 0x60 && link <= 0x63) {
155 		*clinkp = link - 0x60;
156 		DPRINTF(("PIRQ %d (register offset)\n", *clinkp));
157 		return (0);
158 	}
159 
160 	DPRINTF(("bogus IRQ selection source\n"));
161 	return (1);
162 }
163 
164 int
165 piix_get_intr(v, clink, irqp)
166 	pciintr_icu_handle_t v;
167 	int clink, *irqp;
168 {
169 	struct piix_handle *ph = v;
170 	int shift;
171 	pcireg_t reg;
172 
173 	if (PIIX_LEGAL_LINK(clink) == 0)
174 		return (1);
175 
176 	reg = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ);
177 	shift = clink << 3;
178 	if ((reg >> shift) & PIIX_CFG_PIRQ_NONE)
179 		*irqp = I386_PCI_INTERRUPT_LINE_NO_CONNECTION;
180 	else
181 		*irqp = PIIX_PIRQ(reg, clink);
182 
183 	return (0);
184 }
185 
186 int
187 piix_set_intr(v, clink, irq)
188 	pciintr_icu_handle_t v;
189 	int clink, irq;
190 {
191 	struct piix_handle *ph = v;
192 	int shift;
193 	pcireg_t reg;
194 
195 	if (PIIX_LEGAL_LINK(clink) == 0 || PIIX_LEGAL_IRQ(irq) == 0)
196 		return (1);
197 
198 	reg = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ);
199 	shift = clink << 3;
200 	reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift);
201 	reg |= irq << shift;
202 	pci_conf_write(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ, reg);
203 
204 	return (0);
205 }
206 
207 int
208 piix_get_trigger(v, irq, triggerp)
209 	pciintr_icu_handle_t v;
210 	int irq, *triggerp;
211 {
212 	struct piix_handle *ph = v;
213 	int off, bit;
214 	u_int8_t elcr;
215 
216 	if (PIIX_LEGAL_IRQ(irq) == 0)
217 		return (1);
218 
219 	off = (irq > 7) ? 1 : 0;
220 	bit = irq & 7;
221 
222 	elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off);
223 	if (elcr & (1 << bit))
224 		*triggerp = IST_LEVEL;
225 	else
226 		*triggerp = IST_EDGE;
227 
228 	return (0);
229 }
230 
231 int
232 piix_set_trigger(v, irq, trigger)
233 	pciintr_icu_handle_t v;
234 	int irq, trigger;
235 {
236 	struct piix_handle *ph = v;
237 	int off, bit;
238 	u_int8_t elcr;
239 
240 	if (PIIX_LEGAL_IRQ(irq) == 0)
241 		return (1);
242 
243 	off = (irq > 7) ? 1 : 0;
244 	bit = irq & 7;
245 
246 	elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off);
247 	if (trigger == IST_LEVEL)
248 		elcr |= (1 << bit);
249 	else
250 		elcr &= ~(1 << bit);
251 	bus_space_write_1(ph->ph_iot, ph->ph_elcr_ioh, off, elcr);
252 
253 	return (0);
254 }
255 
256 #ifdef PIIX_DEBUG
257 void
258 piix_pir_dump(ph)
259 	struct piix_handle *ph;
260 {
261 	int i, irq;
262 	pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ);
263 	u_int8_t elcr[2];
264 
265 	elcr[0] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 0);
266 	elcr[1] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 1);
267 
268 	for (i = 0; i < 4; i++) {
269 		irq = PIIX_PIRQ(irqs, i);
270 		if (irq & PIIX_CFG_PIRQ_NONE)
271 			printf("PIIX PIRQ %d: irq none (0x%x)\n", i, irq);
272 		else
273 			printf("PIIX PIRQ %d: irq %d\n", i, irq);
274 	}
275 	printf("PIIX irq:");
276 	for (i = 0; i < 16; i++)
277 		printf(" %2d", i);
278 	printf("\n");
279 	printf(" trigger:");
280 	for (i = 0; i < 16; i++)
281 		printf("  %c", (elcr[(i & 8) ? 1 : 0] & (1 << (i & 7))) ?
282 		       'L' : 'E');
283 	printf("\n");
284 }
285 #endif /* PIIX_DEBUG */
286