1 /* $OpenBSD: pci_machdep.c,v 1.81 2015/09/01 06:01:24 deraadt Exp $ */ 2 /* $NetBSD: pci_machdep.c,v 1.28 1997/06/06 23:29:17 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1997 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * Copyright (c) 1994 Charles Hannum. All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Charles Hannum. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Machine-specific functions for PCI autoconfiguration. 66 * 67 * On PCs, there are two methods of generating PCI configuration cycles. 68 * We try to detect the appropriate mechanism for this machine and set 69 * up a few function pointers to access the correct method directly. 70 * 71 * The configuration method can be hard-coded in the config file by 72 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 73 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 74 */ 75 76 #include <sys/types.h> 77 #include <sys/param.h> 78 #include <sys/time.h> 79 #include <sys/systm.h> 80 #include <sys/errno.h> 81 #include <sys/device.h> 82 #include <sys/extent.h> 83 #include <sys/malloc.h> 84 85 #include <uvm/uvm_extern.h> 86 87 #include <machine/bus.h> 88 #include <machine/pio.h> 89 #include <machine/i8259.h> 90 #include <machine/biosvar.h> 91 92 #include "bios.h" 93 #if NBIOS > 0 94 extern bios_pciinfo_t *bios_pciinfo; 95 #endif 96 97 #include <dev/isa/isavar.h> 98 #include <dev/pci/pcivar.h> 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/pci/ppbreg.h> 102 103 #include "ioapic.h" 104 105 #include <machine/i82093var.h> 106 #include <machine/i82489reg.h> 107 #include <machine/i82489var.h> 108 #if NIOAPIC > 0 109 #include <machine/mpbiosvar.h> 110 #endif 111 112 #include "pcibios.h" 113 #if NPCIBIOS > 0 114 #include <i386/pci/pcibiosvar.h> 115 #endif 116 117 int pci_mode = -1; 118 119 /* 120 * Memory Mapped Configuration space access. 121 * 122 * Since mapping the whole configuration space will cost us up to 123 * 256MB of kernel virtual memory, we use seperate mappings per bus. 124 * The mappings are created on-demand, such that we only use kernel 125 * virtual memory for busses that are actually present. 126 */ 127 bus_addr_t pci_mcfg_addr; 128 int pci_mcfg_min_bus, pci_mcfg_max_bus; 129 bus_space_tag_t pci_mcfgt = I386_BUS_SPACE_MEM; 130 bus_space_handle_t pci_mcfgh[256]; 131 void pci_mcfg_map_bus(int); 132 133 struct mutex pci_conf_lock = MUTEX_INITIALIZER(IPL_HIGH); 134 135 #define PCI_CONF_LOCK() \ 136 do { \ 137 mtx_enter(&pci_conf_lock); \ 138 } while (0) 139 140 #define PCI_CONF_UNLOCK() \ 141 do { \ 142 mtx_leave(&pci_conf_lock); \ 143 } while (0) 144 145 #define PCI_MODE1_ENABLE 0x80000000UL 146 #define PCI_MODE1_ADDRESS_REG 0x0cf8 147 #define PCI_MODE1_DATA_REG 0x0cfc 148 149 #define PCI_MODE2_ENABLE_REG 0x0cf8 150 #define PCI_MODE2_FORWARD_REG 0x0cfa 151 152 #define _m1tag(b, d, f) \ 153 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 154 #define _qe(bus, dev, fcn, vend, prod) \ 155 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 156 struct { 157 u_int32_t tag; 158 pcireg_t id; 159 } pcim1_quirk_tbl[] = { 160 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 161 /* XXX Triflex2 not tested */ 162 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 163 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 164 /* Triton needed for Connectix Virtual PC */ 165 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 166 /* Connectix Virtual PC 5 has a 440BX */ 167 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 168 {0, 0xffffffff} /* patchable */ 169 }; 170 #undef _m1tag 171 #undef _qe 172 173 /* 174 * PCI doesn't have any special needs; just use the generic versions 175 * of these functions. 176 */ 177 struct bus_dma_tag pci_bus_dma_tag = { 178 NULL, /* _cookie */ 179 _bus_dmamap_create, 180 _bus_dmamap_destroy, 181 _bus_dmamap_load, 182 _bus_dmamap_load_mbuf, 183 _bus_dmamap_load_uio, 184 _bus_dmamap_load_raw, 185 _bus_dmamap_unload, 186 _bus_dmamap_sync, 187 _bus_dmamem_alloc, 188 _bus_dmamem_alloc_range, 189 _bus_dmamem_free, 190 _bus_dmamem_map, 191 _bus_dmamem_unmap, 192 _bus_dmamem_mmap, 193 }; 194 195 void 196 pci_attach_hook(struct device *parent, struct device *self, 197 struct pcibus_attach_args *pba) 198 { 199 pci_chipset_tag_t pc = pba->pba_pc; 200 pcitag_t tag; 201 pcireg_t id, class; 202 203 #if NBIOS > 0 204 if (pba->pba_bus == 0) 205 printf(": configuration mode %d (%s)", 206 pci_mode, (bios_pciinfo?"bios":"no bios")); 207 #else 208 if (pba->pba_bus == 0) 209 printf(": configuration mode %d", pci_mode); 210 #endif 211 212 if (pba->pba_bus != 0) 213 return; 214 215 /* 216 * Machines that use the non-standard method of generating PCI 217 * configuration cycles are way too old to support MSI. 218 */ 219 if (pci_mode == 2) 220 return; 221 222 /* 223 * In order to decide whether the system supports MSI we look 224 * at the host bridge, which should be device 0 function 0 on 225 * bus 0. It is better to not enable MSI on systems that 226 * support it than the other way around, so be conservative 227 * here. So we don't enable MSI if we don't find a host 228 * bridge there. We also deliberately don't enable MSI on 229 * chipsets from low-end manifacturers like VIA and SiS. 230 */ 231 tag = pci_make_tag(pc, 0, 0, 0); 232 id = pci_conf_read(pc, tag, PCI_ID_REG); 233 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 234 235 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 236 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_HOST) 237 return; 238 239 switch (PCI_VENDOR(id)) { 240 case PCI_VENDOR_INTEL: 241 /* 242 * For Intel platforms, MSI support was introduced 243 * with the new Pentium 4 processor interrupt delivery 244 * mechanism, so we blacklist all PCI chipsets that 245 * support Pentium III and earlier CPUs. 246 */ 247 switch (PCI_PRODUCT(id)) { 248 case PCI_PRODUCT_INTEL_PCMC: /* 82434LX/NX */ 249 case PCI_PRODUCT_INTEL_82437FX: 250 case PCI_PRODUCT_INTEL_82437MX: 251 case PCI_PRODUCT_INTEL_82437VX: 252 case PCI_PRODUCT_INTEL_82439HX: 253 case PCI_PRODUCT_INTEL_82439TX: 254 case PCI_PRODUCT_INTEL_82440BX: 255 case PCI_PRODUCT_INTEL_82440BX_AGP: 256 case PCI_PRODUCT_INTEL_82440MX_HB: 257 case PCI_PRODUCT_INTEL_82441FX: 258 case PCI_PRODUCT_INTEL_82443BX: 259 case PCI_PRODUCT_INTEL_82443BX_AGP: 260 case PCI_PRODUCT_INTEL_82443BX_NOAGP: 261 case PCI_PRODUCT_INTEL_82443GX: 262 case PCI_PRODUCT_INTEL_82443LX: 263 case PCI_PRODUCT_INTEL_82443LX_AGP: 264 case PCI_PRODUCT_INTEL_82810_HB: 265 case PCI_PRODUCT_INTEL_82810E_HB: 266 case PCI_PRODUCT_INTEL_82815_HB: 267 case PCI_PRODUCT_INTEL_82820_HB: 268 case PCI_PRODUCT_INTEL_82830M_HB: 269 case PCI_PRODUCT_INTEL_82840_HB: 270 break; 271 default: 272 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 273 break; 274 } 275 break; 276 case PCI_VENDOR_NVIDIA: 277 /* 278 * Since NVIDIA chipsets are completely undocumented, 279 * we have to make a guess here. We assume that all 280 * chipsets that support PCIe include support for MSI, 281 * since support for MSI is mandated by the PCIe 282 * standard. 283 */ 284 switch (PCI_PRODUCT(id)) { 285 case PCI_PRODUCT_NVIDIA_NFORCE_PCHB: 286 case PCI_PRODUCT_NVIDIA_NFORCE2_PCHB: 287 break; 288 default: 289 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 290 break; 291 } 292 break; 293 case PCI_VENDOR_AMD: 294 /* 295 * The AMD-750 and AMD-760 chipsets don't support MSI. 296 */ 297 switch (PCI_PRODUCT(id)) { 298 case PCI_PRODUCT_AMD_SC751_SC: 299 case PCI_PRODUCT_AMD_761_PCHB: 300 case PCI_PRODUCT_AMD_762_PCHB: 301 break; 302 default: 303 pba->pba_flags |= PCI_FLAGS_MSI_ENABLED; 304 break; 305 } 306 break; 307 } 308 309 /* 310 * Don't enable MSI on a HyperTransport bus. In order to 311 * determine that bus 0 is a HyperTransport bus, we look at 312 * device 24 function 0, which is the HyperTransport 313 * host/primary interface integrated on most 64-bit AMD CPUs. 314 * If that device has a HyperTransport capability, bus 0 must 315 * be a HyperTransport bus and we disable MSI. 316 */ 317 tag = pci_make_tag(pc, 0, 24, 0); 318 if (pci_get_capability(pc, tag, PCI_CAP_HT, NULL, NULL)) 319 pba->pba_flags &= ~PCI_FLAGS_MSI_ENABLED; 320 } 321 322 int 323 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 324 { 325 326 /* 327 * Bus number is irrelevant. If Configuration Mechanism 2 is in 328 * use, can only have devices 0-15 on any bus. If Configuration 329 * Mechanism 1 is in use, can have devices 0-31 (i.e. the `normal' 330 * range). 331 */ 332 if (pci_mode == 2) 333 return (16); 334 else 335 return (32); 336 } 337 338 pcitag_t 339 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 340 { 341 pcitag_t tag; 342 343 switch (pci_mode) { 344 case 1: 345 if (bus >= 256 || device >= 32 || function >= 8) 346 panic("pci_make_tag: bad request"); 347 348 tag.mode1 = PCI_MODE1_ENABLE | 349 (bus << 16) | (device << 11) | (function << 8); 350 break; 351 case 2: 352 if (bus >= 256 || device >= 16 || function >= 8) 353 panic("pci_make_tag: bad request"); 354 355 tag.mode2.port = 0xc000 | (device << 8); 356 tag.mode2.enable = 0xf0 | (function << 1); 357 tag.mode2.forward = bus; 358 break; 359 default: 360 panic("pci_make_tag: mode not configured"); 361 } 362 363 return tag; 364 } 365 366 void 367 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 368 { 369 switch (pci_mode) { 370 case 1: 371 if (bp != NULL) 372 *bp = (tag.mode1 >> 16) & 0xff; 373 if (dp != NULL) 374 *dp = (tag.mode1 >> 11) & 0x1f; 375 if (fp != NULL) 376 *fp = (tag.mode1 >> 8) & 0x7; 377 break; 378 case 2: 379 if (bp != NULL) 380 *bp = tag.mode2.forward & 0xff; 381 if (dp != NULL) 382 *dp = (tag.mode2.port >> 8) & 0xf; 383 if (fp != NULL) 384 *fp = (tag.mode2.enable >> 1) & 0x7; 385 break; 386 default: 387 panic("pci_decompose_tag: mode not configured"); 388 } 389 } 390 391 int 392 pci_conf_size(pci_chipset_tag_t pc, pcitag_t tag) 393 { 394 int bus; 395 396 if (pci_mcfg_addr) { 397 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 398 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) 399 return PCIE_CONFIG_SPACE_SIZE; 400 } 401 402 return PCI_CONFIG_SPACE_SIZE; 403 } 404 405 void 406 pci_mcfg_map_bus(int bus) 407 { 408 if (pci_mcfgh[bus]) 409 return; 410 411 if (bus_space_map(pci_mcfgt, pci_mcfg_addr + (bus << 20), 1 << 20, 412 0, &pci_mcfgh[bus])) 413 panic("pci_conf_read: cannot map mcfg space"); 414 } 415 416 pcireg_t 417 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 418 { 419 pcireg_t data; 420 int bus; 421 422 KASSERT((reg & 0x3) == 0); 423 424 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 425 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 426 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 427 pci_mcfg_map_bus(bus); 428 data = bus_space_read_4(pci_mcfgt, pci_mcfgh[bus], 429 (tag.mode1 & 0x000ff00) << 4 | reg); 430 return data; 431 } 432 } 433 434 PCI_CONF_LOCK(); 435 switch (pci_mode) { 436 case 1: 437 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 438 data = inl(PCI_MODE1_DATA_REG); 439 outl(PCI_MODE1_ADDRESS_REG, 0); 440 break; 441 case 2: 442 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 443 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 444 data = inl(tag.mode2.port | reg); 445 outb(PCI_MODE2_ENABLE_REG, 0); 446 break; 447 default: 448 panic("pci_conf_read: mode not configured"); 449 } 450 PCI_CONF_UNLOCK(); 451 452 return data; 453 } 454 455 void 456 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 457 { 458 int bus; 459 460 KASSERT((reg & 0x3) == 0); 461 462 if (pci_mcfg_addr && reg >= PCI_CONFIG_SPACE_SIZE) { 463 pci_decompose_tag(pc, tag, &bus, NULL, NULL); 464 if (bus >= pci_mcfg_min_bus && bus <= pci_mcfg_max_bus) { 465 pci_mcfg_map_bus(bus); 466 bus_space_write_4(pci_mcfgt, pci_mcfgh[bus], 467 (tag.mode1 & 0x000ff00) << 4 | reg, data); 468 return; 469 } 470 } 471 472 PCI_CONF_LOCK(); 473 switch (pci_mode) { 474 case 1: 475 outl(PCI_MODE1_ADDRESS_REG, tag.mode1 | reg); 476 outl(PCI_MODE1_DATA_REG, data); 477 outl(PCI_MODE1_ADDRESS_REG, 0); 478 break; 479 case 2: 480 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 481 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 482 outl(tag.mode2.port | reg, data); 483 outb(PCI_MODE2_ENABLE_REG, 0); 484 break; 485 default: 486 panic("pci_conf_write: mode not configured"); 487 } 488 PCI_CONF_UNLOCK(); 489 } 490 491 int 492 pci_mode_detect(void) 493 { 494 495 #ifdef PCI_CONF_MODE 496 #if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 497 return (pci_mode = PCI_CONF_MODE); 498 #else 499 #error Invalid PCI configuration mode. 500 #endif 501 #else 502 u_int32_t sav, val; 503 int i; 504 pcireg_t idreg; 505 506 if (pci_mode != -1) 507 return (pci_mode); 508 509 #if NBIOS > 0 510 /* 511 * If we have PCI info passed from the BIOS, use the mode given there 512 * for all of this code. If not, pass on through to the previous tests 513 * to try and divine the correct mode. 514 */ 515 if (bios_pciinfo != NULL) { 516 if (bios_pciinfo->pci_chars & 0x2) 517 return (pci_mode = 2); 518 519 if (bios_pciinfo->pci_chars & 0x1) 520 return (pci_mode = 1); 521 522 /* We should never get here, but if we do, fall through... */ 523 } 524 #endif 525 526 /* 527 * We try to divine which configuration mode the host bridge wants. 528 * 529 * This should really be done using the PCI BIOS. If we get here, the 530 * PCI BIOS does not exist, or the boot blocks did not provide the 531 * information. 532 */ 533 534 sav = inl(PCI_MODE1_ADDRESS_REG); 535 536 pci_mode = 1; /* assume this for now */ 537 /* 538 * catch some known buggy implementations of mode 1 539 */ 540 for (i = 0; i < sizeof(pcim1_quirk_tbl) / sizeof(pcim1_quirk_tbl[0]); 541 i++) { 542 pcitag_t t; 543 544 if (!pcim1_quirk_tbl[i].tag) 545 break; 546 t.mode1 = pcim1_quirk_tbl[i].tag; 547 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 548 if (idreg == pcim1_quirk_tbl[i].id) { 549 #ifdef DEBUG 550 printf("known mode 1 PCI chipset (%08x)\n", 551 idreg); 552 #endif 553 return (pci_mode); 554 } 555 } 556 557 /* 558 * Strong check for standard compliant mode 1: 559 * 1. bit 31 ("enable") can be set 560 * 2. byte/word access does not affect register 561 */ 562 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 563 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 564 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 565 val = inl(PCI_MODE1_ADDRESS_REG); 566 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 567 #ifdef DEBUG 568 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 569 val); 570 #endif 571 goto not1; 572 } 573 outl(PCI_MODE1_ADDRESS_REG, 0); 574 val = inl(PCI_MODE1_ADDRESS_REG); 575 if ((val & 0x80fffffc) != 0) 576 goto not1; 577 return (pci_mode); 578 not1: 579 outl(PCI_MODE1_ADDRESS_REG, sav); 580 581 /* 582 * This mode 2 check is quite weak (and known to give false 583 * positives on some Compaq machines). 584 * However, this doesn't matter, because this is the 585 * last test, and simply no PCI devices will be found if 586 * this happens. 587 */ 588 outb(PCI_MODE2_ENABLE_REG, 0); 589 outb(PCI_MODE2_FORWARD_REG, 0); 590 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 591 inb(PCI_MODE2_FORWARD_REG) != 0) 592 goto not2; 593 return (pci_mode = 2); 594 not2: 595 return (pci_mode = 0); 596 #endif 597 } 598 599 int 600 pci_intr_map_msi(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 601 { 602 pci_chipset_tag_t pc = pa->pa_pc; 603 pcitag_t tag = pa->pa_tag; 604 605 if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 || mp_busses == NULL || 606 pci_get_capability(pc, tag, PCI_CAP_MSI, NULL, NULL) == 0) 607 return 1; 608 609 ihp->tag = tag; 610 ihp->line = APIC_INT_VIA_MSG; 611 ihp->pin = 0; 612 return 0; 613 } 614 615 int 616 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 617 { 618 int pin = pa->pa_rawintrpin; 619 int line = pa->pa_intrline; 620 #if NIOAPIC > 0 621 struct mp_intr_map *mip; 622 int bus, dev, func; 623 #endif 624 625 if (pin == 0) { 626 /* No IRQ used. */ 627 goto bad; 628 } 629 630 if (pin > PCI_INTERRUPT_PIN_MAX) { 631 printf("pci_intr_map: bad interrupt pin %d\n", pin); 632 goto bad; 633 } 634 635 ihp->tag = pa->pa_tag; 636 ihp->line = line; 637 ihp->pin = pin; 638 639 #if NIOAPIC > 0 640 pci_decompose_tag (pa->pa_pc, pa->pa_tag, &bus, &dev, &func); 641 642 if (!(ihp->line & PCI_INT_VIA_ISA) && mp_busses != NULL) { 643 int mpspec_pin = (dev << 2) | (pin - 1); 644 645 if (bus < mp_nbusses) { 646 for (mip = mp_busses[bus].mb_intrs; 647 mip != NULL; mip = mip->next) { 648 if (&mp_busses[bus] == mp_isa_bus || 649 &mp_busses[bus] == mp_eisa_bus) 650 continue; 651 if (mip->bus_pin == mpspec_pin) { 652 ihp->line = mip->ioapic_ih | line; 653 return 0; 654 } 655 } 656 } 657 658 if (pa->pa_bridgetag) { 659 int swizpin = PPB_INTERRUPT_SWIZZLE(pin, dev); 660 if (pa->pa_bridgeih[swizpin - 1].line != -1) { 661 ihp->line = pa->pa_bridgeih[swizpin - 1].line; 662 ihp->line |= line; 663 return 0; 664 } 665 } 666 /* 667 * No explicit PCI mapping found. This is not fatal, 668 * we'll try the ISA (or possibly EISA) mappings next. 669 */ 670 } 671 #endif 672 673 #if NPCIBIOS > 0 674 pci_intr_header_fixup(pa->pa_pc, pa->pa_tag, ihp); 675 line = ihp->line & APIC_INT_LINE_MASK; 676 #endif 677 678 /* 679 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 680 * `unknown' or `no connection' on a PC. We assume that a device with 681 * `no connection' either doesn't have an interrupt (in which case the 682 * pin number should be 0, and would have been noticed above), or 683 * wasn't configured by the BIOS (in which case we punt, since there's 684 * no real way we can know how the interrupt lines are mapped in the 685 * hardware). 686 * 687 * XXX 688 * Since IRQ 0 is only used by the clock, and we can't actually be sure 689 * that the BIOS did its job, we also recognize that as meaning that 690 * the BIOS has not configured the device. 691 */ 692 if (line == 0 || line == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 693 goto bad; 694 695 if (line >= ICU_LEN) { 696 printf("pci_intr_map: bad interrupt line %d\n", line); 697 goto bad; 698 } 699 if (line == 2) { 700 printf("pci_intr_map: changed line 2 to line 9\n"); 701 line = 9; 702 } 703 704 #if NIOAPIC > 0 705 if (!(ihp->line & PCI_INT_VIA_ISA) && mp_busses != NULL) { 706 if (mip == NULL && mp_isa_bus) { 707 for (mip = mp_isa_bus->mb_intrs; mip != NULL; 708 mip = mip->next) { 709 if (mip->bus_pin == line) { 710 ihp->line = mip->ioapic_ih | line; 711 return 0; 712 } 713 } 714 } 715 if (mip == NULL && mp_eisa_bus) { 716 for (mip = mp_eisa_bus->mb_intrs; mip != NULL; 717 mip = mip->next) { 718 if (mip->bus_pin == line) { 719 ihp->line = mip->ioapic_ih | line; 720 return 0; 721 } 722 } 723 } 724 if (mip == NULL) { 725 printf("pci_intr_map: " 726 "bus %d dev %d func %d pin %d; line %d\n", 727 bus, dev, func, pin, line); 728 printf("pci_intr_map: no MP mapping found\n"); 729 } 730 } 731 #endif 732 733 return 0; 734 735 bad: 736 ihp->line = -1; 737 return 1; 738 } 739 740 const char * 741 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 742 { 743 static char irqstr[64]; 744 int line = ih.line & APIC_INT_LINE_MASK; 745 746 if (ih.line & APIC_INT_VIA_MSG) 747 return ("msi"); 748 749 #if NIOAPIC > 0 750 if (ih.line & APIC_INT_VIA_APIC) { 751 snprintf(irqstr, sizeof irqstr, "apic %d int %d", 752 APIC_IRQ_APIC(ih.line), APIC_IRQ_PIN(ih.line)); 753 return (irqstr); 754 } 755 #endif 756 757 if (line == 0 || line >= ICU_LEN || line == 2) 758 panic("pci_intr_string: bogus handle 0x%x", line); 759 760 snprintf(irqstr, sizeof irqstr, "irq %d", line); 761 return (irqstr); 762 } 763 764 #include "acpiprt.h" 765 #if NACPIPRT > 0 766 void acpiprt_route_interrupt(int bus, int dev, int pin); 767 #endif 768 769 extern struct intrhand *apic_intrhand[256]; 770 extern int apic_maxlevel[256]; 771 772 void * 773 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 774 int (*func)(void *), void *arg, const char *what) 775 { 776 void *ret; 777 int bus, dev; 778 int l = ih.line & APIC_INT_LINE_MASK; 779 pcitag_t tag = ih.tag; 780 int irq = ih.line; 781 782 if (ih.line & APIC_INT_VIA_MSG) { 783 struct intrhand *ih; 784 pcireg_t reg, addr; 785 int off, vec; 786 int flags; 787 788 flags = level & IPL_MPSAFE; 789 level &= ~IPL_MPSAFE; 790 791 KASSERT(level <= IPL_TTY || flags & IPL_MPSAFE); 792 793 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0) 794 panic("%s: no msi capability", __func__); 795 796 vec = idt_vec_alloc(level, level + 15); 797 if (vec == 0) 798 return (NULL); 799 800 ih = malloc(sizeof(*ih), M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 801 if (ih == NULL) 802 panic("%s: can't malloc handler info", __func__); 803 804 ih->ih_fun = func; 805 ih->ih_arg = arg; 806 ih->ih_next = NULL; 807 ih->ih_level = level; 808 ih->ih_flags = flags; 809 ih->ih_irq = irq; 810 ih->ih_pin = tag.mode1; 811 ih->ih_vec = vec; 812 evcount_attach(&ih->ih_count, what, &ih->ih_vec); 813 814 apic_maxlevel[vec] = level; 815 apic_intrhand[vec] = ih; 816 idt_vec_set(vec, apichandler[vec & 0xf]); 817 818 addr = 0xfee00000UL | (cpu_info_primary.ci_apicid << 12); 819 820 if (reg & PCI_MSI_MC_C64) { 821 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr); 822 pci_conf_write(pc, tag, off + PCI_MSI_MAU32, 0); 823 pci_conf_write(pc, tag, off + PCI_MSI_MD64, vec); 824 } else { 825 pci_conf_write(pc, tag, off + PCI_MSI_MA, addr); 826 pci_conf_write(pc, tag, off + PCI_MSI_MD32, vec); 827 } 828 pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE); 829 return (ih); 830 } 831 832 pci_decompose_tag(pc, ih.tag, &bus, &dev, NULL); 833 #if NACPIPRT > 0 834 acpiprt_route_interrupt(bus, dev, ih.pin); 835 #endif 836 837 #if NIOAPIC > 0 838 if (l != -1 && ih.line & APIC_INT_VIA_APIC) 839 return (apic_intr_establish(ih.line, IST_LEVEL, level, func, 840 arg, what)); 841 #endif 842 if (l == 0 || l >= ICU_LEN || l == 2) 843 panic("pci_intr_establish: bogus handle 0x%x", l); 844 845 ret = isa_intr_establish(NULL, l, IST_LEVEL, level, func, arg, what); 846 #if NPCIBIOS > 0 847 if (ret) 848 pci_intr_route_link(pc, &ih); 849 #endif 850 return (ret); 851 } 852 853 void 854 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 855 { 856 struct intrhand *ih = cookie; 857 858 if (ih->ih_irq & APIC_INT_VIA_MSG) { 859 pcitag_t tag = { .mode1 = ih->ih_pin }; 860 pcireg_t reg; 861 int off; 862 863 if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®)) 864 pci_conf_write(pc, tag, off, reg &= ~PCI_MSI_MC_MSIE); 865 866 apic_maxlevel[ih->ih_vec] = 0; 867 apic_intrhand[ih->ih_vec] = NULL; 868 idt_vec_free(ih->ih_vec); 869 870 evcount_detach(&ih->ih_count); 871 free(ih, M_DEVBUF, sizeof *ih); 872 return; 873 } 874 875 /* XXX oh, unroute the pci int link? */ 876 isa_intr_disestablish(NULL, cookie); 877 } 878 879 struct extent *pciio_ex; 880 struct extent *pcimem_ex; 881 struct extent *pcibus_ex; 882 883 void 884 pci_init_extents(void) 885 { 886 bios_memmap_t *bmp; 887 u_int64_t size; 888 889 if (pciio_ex == NULL) { 890 /* 891 * We only have 64K of addressable I/O space. 892 * However, since BARs may contain garbage, we cover 893 * the full 32-bit address space defined by PCI of 894 * which we only make the first 64K available. 895 */ 896 pciio_ex = extent_create("pciio", 0, 0xffffffff, M_DEVBUF, 897 NULL, 0, EX_NOWAIT | EX_FILLED); 898 if (pciio_ex == NULL) 899 return; 900 extent_free(pciio_ex, 0, 0x10000, M_NOWAIT); 901 } 902 903 if (pcimem_ex == NULL) { 904 pcimem_ex = extent_create("pcimem", 0, 0xffffffff, M_DEVBUF, 905 NULL, 0, EX_NOWAIT); 906 if (pcimem_ex == NULL) 907 return; 908 909 for (bmp = bios_memmap; bmp->type != BIOS_MAP_END; bmp++) { 910 /* 911 * Ignore address space beyond 4G. 912 */ 913 if (bmp->addr >= 0x100000000ULL) 914 continue; 915 size = bmp->size; 916 if (bmp->addr + size >= 0x100000000ULL) 917 size = 0x100000000ULL - bmp->addr; 918 919 /* Ignore zero-sized regions. */ 920 if (size == 0) 921 continue; 922 923 if (extent_alloc_region(pcimem_ex, bmp->addr, size, 924 EX_NOWAIT)) 925 printf("memory map conflict 0x%llx/0x%llx\n", 926 bmp->addr, bmp->size); 927 } 928 929 /* Take out the video buffer area and BIOS areas. */ 930 extent_alloc_region(pcimem_ex, IOM_BEGIN, IOM_SIZE, 931 EX_CONFLICTOK | EX_NOWAIT); 932 } 933 934 if (pcibus_ex == NULL) { 935 pcibus_ex = extent_create("pcibus", 0, 0xff, M_DEVBUF, 936 NULL, 0, EX_NOWAIT); 937 } 938 } 939 940 #include "acpi.h" 941 #if NACPI > 0 942 void acpi_pci_match(struct device *, struct pci_attach_args *); 943 pcireg_t acpi_pci_min_powerstate(pci_chipset_tag_t, pcitag_t); 944 void acpi_pci_set_powerstate(pci_chipset_tag_t, pcitag_t, int, int); 945 #endif 946 947 void 948 pci_dev_postattach(struct device *dev, struct pci_attach_args *pa) 949 { 950 #if NACPI > 0 951 acpi_pci_match(dev, pa); 952 #endif 953 } 954 955 pcireg_t 956 pci_min_powerstate(pci_chipset_tag_t pc, pcitag_t tag) 957 { 958 #if NACPI > 0 959 return acpi_pci_min_powerstate(pc, tag); 960 #else 961 return pci_get_powerstate(pc, tag); 962 #endif 963 } 964 965 void 966 pci_set_powerstate_md(pci_chipset_tag_t pc, pcitag_t tag, int state, int pre) 967 { 968 #if NACPI > 0 969 acpi_pci_set_powerstate(pc, tag, state, pre); 970 #endif 971 } 972