1 /* $OpenBSD: pci_intr_fixup.c,v 1.61 2008/06/26 05:42:11 ray Exp $ */ 2 /* $NetBSD: pci_intr_fixup.c,v 1.10 2000/08/10 21:18:27 soda Exp $ */ 3 4 /* 5 * Copyright (c) 2001 Michael Shalayeff 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 21 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /*- 30 * Copyright (c) 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 35 * NASA Ames Research Center. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 47 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 48 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 49 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 50 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 51 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 52 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 53 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 54 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 55 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 56 * POSSIBILITY OF SUCH DAMAGE. 57 */ 58 /* 59 * Copyright (c) 1999, by UCHIYAMA Yasushi 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions 64 * are met: 65 * 1. Redistributions of source code must retain the above copyright 66 * notice, this list of conditions and the following disclaimer. 67 * 2. The name of the developer may NOT be used to endorse or promote products 68 * derived from this software without specific prior written permission. 69 * 70 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 71 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 73 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 74 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 75 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 76 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 77 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 78 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 79 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 80 * SUCH DAMAGE. 81 */ 82 83 /* 84 * PCI Interrupt Router support. 85 */ 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/kernel.h> 90 #include <sys/malloc.h> 91 #include <sys/queue.h> 92 #include <sys/device.h> 93 94 #include <machine/bus.h> 95 #include <machine/intr.h> 96 #include <machine/i8259.h> 97 #include <machine/i82093var.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <i386/pci/pcibiosvar.h> 104 105 struct pciintr_link_map { 106 int link, clink, irq, fixup_stage; 107 u_int16_t bitmap; 108 SIMPLEQ_ENTRY(pciintr_link_map) list; 109 }; 110 111 pciintr_icu_tag_t pciintr_icu_tag = NULL; 112 pciintr_icu_handle_t pciintr_icu_handle; 113 114 #ifdef PCIBIOS_IRQS_HINT 115 int pcibios_irqs_hint = PCIBIOS_IRQS_HINT; 116 #endif 117 118 struct pciintr_link_map *pciintr_link_lookup(int); 119 struct pcibios_intr_routing *pciintr_pir_lookup(int, int); 120 int pciintr_bitmap_count_irq(int, int *); 121 122 SIMPLEQ_HEAD(, pciintr_link_map) pciintr_link_map_list; 123 124 const struct pciintr_icu_table { 125 pci_vendor_id_t piit_vendor; 126 pci_product_id_t piit_product; 127 int (*piit_init)(pci_chipset_tag_t, 128 bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *, 129 pciintr_icu_handle_t *); 130 } pciintr_icu_table[] = { 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_LPC, 132 piix_init }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_LPC, 134 piix_init }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371MX, 136 piix_init }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_ISA, 138 piix_init }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371FB_ISA, 140 piix_init }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371SB_ISA, 142 piix_init }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ISA, 144 piix_init }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 146 piix_init }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC, 148 piix_init }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 150 piix_init }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 152 piix_init }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC, 154 piix_init }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC, 156 piix_init }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC, 158 piix_init }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DBM_LPC, 160 piix_init }, 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LPC, 162 piix_init }, 163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 164 piix_init }, 165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC, 166 piix_init }, 167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC, 168 piix_init }, 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_LPC, 170 piix_init }, 171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC, 172 piix_init }, 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GH_LPC, 174 piix_init }, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC, 176 piix_init }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IB_LPC, 178 piix_init }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IH_LPC, 180 piix_init }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IO_LPC, 182 piix_init }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801IR_LPC, 184 piix_init }, 185 186 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558, 187 opti82c558_init }, 188 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C700, 189 opti82c700_init }, 190 191 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_OSB4, 192 osb4_init }, 193 { PCI_VENDOR_RCC, PCI_PRODUCT_RCC_CSB5, 194 osb4_init }, 195 196 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_ISA, 197 via82c586_init, }, 198 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C596A, 199 via82c586_init, }, 200 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C686A_ISA, 201 via82c586_init }, 202 203 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8231_ISA, 204 via8231_init }, 205 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233_ISA, 206 via8231_init }, 207 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233A_ISA, 208 via8231_init }, 209 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8235_ISA, 210 via8231_init }, 211 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237_ISA, 212 via8231_init }, 213 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237A_ISA, 214 via8231_init }, 215 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237S_ISA, 216 via8231_init }, 217 218 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503, 219 sis85c503_init }, 220 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_962, 221 sis85c503_init }, 222 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_963, 223 sis85c503_init }, 224 225 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC756_PMC, 226 amd756_init }, 227 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_766_PMC, 228 amd756_init }, 229 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_PMC, 230 amd756_init }, 231 232 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1533, 233 ali1543_init }, 234 235 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1543, 236 ali1543_init }, 237 238 { 0, 0, 239 NULL }, 240 }; 241 242 const struct pciintr_icu_table *pciintr_icu_lookup(pcireg_t); 243 244 const struct pciintr_icu_table * 245 pciintr_icu_lookup(id) 246 pcireg_t id; 247 { 248 const struct pciintr_icu_table *piit; 249 250 for (piit = pciintr_icu_table; piit->piit_init != NULL; piit++) 251 if (PCI_VENDOR(id) == piit->piit_vendor && 252 PCI_PRODUCT(id) == piit->piit_product) 253 return (piit); 254 255 return (NULL); 256 } 257 258 struct pciintr_link_map * 259 pciintr_link_lookup(int link) 260 { 261 struct pciintr_link_map *l; 262 263 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 264 l = SIMPLEQ_NEXT(l, list)) 265 if (l->link == link) 266 return (l); 267 268 return (NULL); 269 } 270 271 static __inline struct pciintr_link_map * 272 pciintr_link_alloc(pci_chipset_tag_t pc, struct pcibios_intr_routing *pir, int pin) 273 { 274 int link = pir->linkmap[pin].link, clink, irq; 275 struct pciintr_link_map *l, *lstart; 276 277 if (pciintr_icu_tag != NULL) { 278 /* 279 * Get the canonical link value for this entry. 280 */ 281 if (pciintr_icu_getclink(pciintr_icu_tag, pciintr_icu_handle, 282 link, &clink) != 0) { 283 /* 284 * ICU doesn't understand the link value. 285 * Just ignore this PIR entry. 286 */ 287 PCIBIOS_PRINTV(("pciintr_link_alloc: bus %d device %d: " 288 "ignoring link 0x%02x\n", pir->bus, 289 PIR_DEVFUNC_DEVICE(pir->device), link)); 290 return (NULL); 291 } 292 293 /* 294 * Check the link value by asking the ICU for the 295 * canonical link value. 296 * Also, determine if this PIRQ is mapped to an IRQ. 297 */ 298 if (pciintr_icu_get_intr(pciintr_icu_tag, pciintr_icu_handle, 299 clink, &irq) != 0) { 300 /* 301 * ICU doesn't understand the canonical link value. 302 * Just ignore this PIR entry. 303 */ 304 PCIBIOS_PRINTV(("pciintr_link_alloc: " 305 "bus %d device %d link 0x%02x: " 306 "ignoring PIRQ 0x%02x\n", pir->bus, 307 PIR_DEVFUNC_DEVICE(pir->device), link, clink)); 308 return (NULL); 309 } 310 } 311 312 if ((l = malloc(sizeof(*l), M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) 313 return (NULL); 314 315 l->link = link; 316 l->bitmap = pir->linkmap[pin].bitmap; 317 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 318 l->clink = clink; 319 l->irq = irq; /* maybe I386_PCI_INTERRUPT_LINE_NO_CONNECTION */ 320 } else { 321 l->clink = link; 322 l->irq = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 323 } 324 325 lstart = SIMPLEQ_FIRST(&pciintr_link_map_list); 326 if (lstart == NULL || lstart->link < l->link) 327 SIMPLEQ_INSERT_TAIL(&pciintr_link_map_list, l, list); 328 else 329 SIMPLEQ_INSERT_HEAD(&pciintr_link_map_list, l, list); 330 331 return (l); 332 } 333 334 struct pcibios_intr_routing * 335 pciintr_pir_lookup(int bus, int device) 336 { 337 struct pcibios_intr_routing *pir; 338 int entry; 339 340 if (pcibios_pir_table == NULL) 341 return (NULL); 342 343 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 344 pir = &pcibios_pir_table[entry]; 345 if (pir->bus == bus && 346 PIR_DEVFUNC_DEVICE(pir->device) == device) 347 return (pir); 348 } 349 350 return (NULL); 351 } 352 353 int 354 pciintr_bitmap_count_irq(int irq_bitmap, int *irqp) 355 { 356 int i, bit, count = 0, irq = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 357 358 if (irq_bitmap != 0) 359 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) 360 if (irq_bitmap & bit) { 361 irq = i; 362 count++; 363 } 364 365 *irqp = irq; 366 return (count); 367 } 368 369 static __inline int 370 pciintr_link_init(pci_chipset_tag_t pc) 371 { 372 int entry, pin, link; 373 struct pcibios_intr_routing *pir; 374 struct pciintr_link_map *l; 375 376 if (pcibios_pir_table == NULL) { 377 /* No PIR table; can't do anything. */ 378 printf("pciintr_link_init: no PIR table\n"); 379 return (1); 380 } 381 382 SIMPLEQ_INIT(&pciintr_link_map_list); 383 384 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 385 pir = &pcibios_pir_table[entry]; 386 for (pin = 0; pin < PCI_INTERRUPT_PIN_MAX; pin++) { 387 if ((link = pir->linkmap[pin].link) == 0) 388 /* No connection for this pin. */ 389 continue; 390 391 /* 392 * Multiple devices may be wired to the same 393 * interrupt; check to see if we've seen this 394 * one already. If not, allocate a new link 395 * map entry and stuff it in the map. 396 */ 397 if ((l = pciintr_link_lookup(link)) == NULL) 398 pciintr_link_alloc(pc, pir, pin); 399 else if (pir->linkmap[pin].bitmap != l->bitmap) { 400 /* 401 * violates PCI IRQ Routing Table Specification 402 */ 403 PCIBIOS_PRINTV(("pciintr_link_init: " 404 "bus %d device %d link 0x%02x: " 405 "bad irq bitmap 0x%04x, " 406 "should be 0x%04x\n", pir->bus, 407 PIR_DEVFUNC_DEVICE(pir->device), link, 408 pir->linkmap[pin].bitmap, l->bitmap)); 409 /* safer value. */ 410 l->bitmap &= pir->linkmap[pin].bitmap; 411 /* XXX - or, should ignore this entry? */ 412 } 413 } 414 } 415 416 return (0); 417 } 418 419 /* 420 * No compatible PCI ICU found. 421 * Hopes the BIOS already setup the ICU. 422 */ 423 static __inline int 424 pciintr_guess_irq(void) 425 { 426 struct pciintr_link_map *l; 427 int irq, guessed = 0; 428 429 /* 430 * Stage 1: If only one IRQ is available for the link, use it. 431 */ 432 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 433 l = SIMPLEQ_NEXT(l, list)) { 434 if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 435 continue; 436 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 437 l->irq = irq; 438 l->fixup_stage = 1; 439 if (pcibios_flags & PCIBIOS_INTRDEBUG) 440 printf("pciintr_guess_irq (stage 1): " 441 "guessing PIRQ 0x%02x to be IRQ %d\n", 442 l->clink, l->irq); 443 guessed = 1; 444 } 445 } 446 447 return (guessed ? 0 : -1); 448 } 449 450 static __inline int 451 pciintr_link_fixup(void) 452 { 453 struct pciintr_link_map *l; 454 u_int16_t pciirq = 0; 455 int irq; 456 457 /* 458 * First stage: Attempt to connect PIRQs which aren't 459 * yet connected. 460 */ 461 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 462 l = SIMPLEQ_NEXT(l, list)) { 463 if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 464 /* 465 * Interrupt is already connected. Don't do 466 * anything to it. 467 * In this case, l->fixup_stage == 0. 468 */ 469 pciirq |= 1 << l->irq; 470 if (pcibios_flags & PCIBIOS_INTRDEBUG) 471 printf("pciintr_link_fixup: PIRQ 0x%02x is " 472 "already connected to IRQ %d\n", 473 l->clink, l->irq); 474 continue; 475 } 476 /* 477 * Interrupt isn't connected. Attempt to assign it to an IRQ. 478 */ 479 if (pcibios_flags & PCIBIOS_INTRDEBUG) 480 printf("pciintr_link_fixup: PIRQ 0x%02x not connected", 481 l->clink); 482 483 /* 484 * Just do the easy case now; we'll defer the harder ones 485 * to Stage 2. 486 */ 487 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 488 l->irq = irq; 489 l->fixup_stage = 1; 490 pciirq |= 1 << irq; 491 if (pcibios_flags & PCIBIOS_INTRDEBUG) 492 printf(", assigning IRQ %d", l->irq); 493 } 494 if (pcibios_flags & PCIBIOS_INTRDEBUG) 495 printf("\n"); 496 } 497 498 /* 499 * Stage 2: Attempt to connect PIRQs which we didn't 500 * connect in Stage 1. 501 */ 502 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 503 l = SIMPLEQ_NEXT(l, list)) 504 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION && 505 (irq = ffs(l->bitmap & pciirq)) > 0) { 506 /* 507 * This IRQ is a valid PCI IRQ already 508 * connected to another PIRQ, and also an 509 * IRQ our PIRQ can use; connect it up! 510 */ 511 l->fixup_stage = 2; 512 l->irq = irq - 1; 513 if (pcibios_flags & PCIBIOS_INTRDEBUG) 514 printf("pciintr_link_fixup (stage 2): " 515 "assigning IRQ %d to PIRQ 0x%02x\n", 516 l->irq, l->clink); 517 } 518 519 #ifdef PCIBIOS_IRQS_HINT 520 /* 521 * Stage 3: The worst case. I need configuration hint that 522 * user supplied a mask for the PCI irqs 523 */ 524 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 525 l = SIMPLEQ_NEXT(l, list)) { 526 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION && 527 (irq = ffs(l->bitmap & pcibios_irqs_hint)) > 0) { 528 l->fixup_stage = 3; 529 l->irq = irq - 1; 530 if (pcibios_flags & PCIBIOS_INTRDEBUG) 531 printf("pciintr_link_fixup (stage 3): " 532 "assigning IRQ %d to PIRQ 0x%02x\n", 533 l->irq, l->clink); 534 } 535 } 536 #endif /* PCIBIOS_IRQS_HINT */ 537 538 if (pcibios_flags & PCIBIOS_INTRDEBUG) 539 printf("pciintr_link_fixup: piirq 0x%04x\n", pciirq); 540 541 return (0); 542 } 543 544 int 545 pci_intr_route_link(pci_chipset_tag_t pc, pci_intr_handle_t *ihp) 546 { 547 struct pciintr_link_map *l; 548 pcireg_t intr; 549 int irq, rv = 1; 550 char *p = NULL; 551 552 if (pcibios_flags & PCIBIOS_INTR_FIXUP) 553 return 1; 554 555 irq = ihp->line & APIC_INT_LINE_MASK; 556 if (irq != 0 && irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 557 pcibios_pir_header.exclusive_irq |= 1 << irq; 558 559 l = ihp->link; 560 if (!l || pciintr_icu_tag == NULL) 561 return (1); 562 563 if (l->fixup_stage == 0) { 564 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 565 /* Appropriate interrupt was not found. */ 566 if (pcibios_flags & PCIBIOS_INTRDEBUG) 567 printf("pci_intr_route_link: PIRQ 0x%02x: " 568 "no IRQ, try " 569 "\"option PCIBIOS_IRQS_HINT=0x%04x\"\n", 570 l->clink, 571 /* suggest irq 9/10/11, if possible */ 572 (l->bitmap & 0x0e00) ? (l->bitmap & 0x0e00) 573 : l->bitmap); 574 } else 575 p = " preserved BIOS setting"; 576 } else { 577 578 if (pciintr_icu_set_intr(pciintr_icu_tag, pciintr_icu_handle, 579 l->clink, l->irq) != 0 || 580 pciintr_icu_set_trigger(pciintr_icu_tag, pciintr_icu_handle, 581 l->irq, IST_LEVEL) != 0) { 582 p = " failed"; 583 rv = 0; 584 } else 585 p = ""; 586 } 587 if (p && pcibios_flags & PCIBIOS_INTRDEBUG) 588 printf("pci_intr_route_link: route PIRQ 0x%02x -> IRQ %d%s\n", 589 l->clink, l->irq, p); 590 591 if (!rv) 592 return (0); 593 594 /* 595 * IRQs 14 and 15 are reserved for PCI IDE interrupts; don't muck 596 * with them. 597 */ 598 if (irq == 14 || irq == 15) 599 return (1); 600 601 intr = pci_conf_read(pc, ihp->tag, PCI_INTERRUPT_REG); 602 if (irq != PCI_INTERRUPT_LINE(intr)) { 603 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 604 intr |= irq << PCI_INTERRUPT_LINE_SHIFT; 605 pci_conf_write(pc, ihp->tag, PCI_INTERRUPT_REG, intr); 606 } 607 608 return (1); 609 } 610 611 int 612 pci_intr_post_fixup(void) 613 { 614 struct pciintr_link_map *l; 615 int i, pciirq; 616 617 if (pcibios_flags & PCIBIOS_INTR_FIXUP) 618 return 1; 619 620 if (!pciintr_icu_handle) 621 return 0; 622 623 pciirq = pcibios_pir_header.exclusive_irq; 624 if (pcibios_flags & PCIBIOS_INTRDEBUG) 625 printf("pci_intr_post_fixup: PCI IRQs:"); 626 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); 627 l != NULL; l = SIMPLEQ_NEXT(l, list)) 628 if (l->fixup_stage == 0 && l->irq != 0 && 629 l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 630 if (pcibios_flags & PCIBIOS_INTRDEBUG) 631 printf(" %d", l->irq); 632 pciirq |= (1 << l->irq); 633 } 634 635 if (pcibios_flags & PCIBIOS_INTRDEBUG) 636 printf("; ISA IRQs:"); 637 for (i = 0; i < 16; i++) 638 if (!(pciirq & (1 << i))) { 639 if (pcibios_flags & PCIBIOS_INTRDEBUG) 640 printf(" %d", i); 641 pciintr_icu_set_trigger(pciintr_icu_tag, 642 pciintr_icu_handle, i, IST_EDGE); 643 } 644 645 if (pcibios_flags & PCIBIOS_INTRDEBUG) 646 printf("\n"); 647 648 return (0); 649 } 650 651 int 652 pci_intr_header_fixup(pci_chipset_tag_t pc, pcitag_t tag, 653 pci_intr_handle_t *ihp) 654 { 655 struct pcibios_intr_routing *pir; 656 struct pciintr_link_map *l; 657 int irq, link, bus, device, function; 658 char *p = NULL; 659 660 if (pcibios_flags & PCIBIOS_INTR_FIXUP) 661 return 1; 662 663 irq = ihp->line & APIC_INT_LINE_MASK; 664 ihp->link = NULL; 665 ihp->tag = tag; 666 pci_decompose_tag(pc, tag, &bus, &device, &function); 667 668 if ((pir = pciintr_pir_lookup(bus, device)) == NULL || 669 (link = pir->linkmap[ihp->pin - 1].link) == 0) { 670 PCIBIOS_PRINTV(("Interrupt not connected; no need to change.")); 671 return 1; 672 } 673 674 if ((l = pciintr_link_lookup(link)) == NULL) { 675 /* 676 * No link map entry. 677 * Probably pciintr_icu_getclink() or pciintr_icu_get_intr() 678 * has failed. 679 */ 680 if (pcibios_flags & PCIBIOS_INTRDEBUG) 681 printf("pci_intr_header_fixup: no entry for link " 682 "0x%02x (%d:%d:%d:%c)\n", 683 link, bus, device, function, '@' + ihp->pin); 684 return 1; 685 } 686 687 ihp->link = l; 688 if (irq == 14 || irq == 15) { 689 p = " WARNING: ignored"; 690 ihp->link = NULL; 691 } else if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 692 693 /* Appropriate interrupt was not found. */ 694 if (pciintr_icu_tag == NULL && irq != 0 && 695 irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 696 /* 697 * Do not print warning, 698 * if no compatible PCI ICU found, 699 * but the irq is already assigned by BIOS. 700 */ 701 p = ""; 702 else 703 p = " WARNING: missing"; 704 } else if (irq == 0 || irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 705 706 p = " fixed up"; 707 ihp->line = irq = l->irq; 708 709 } else if (pcibios_flags & PCIBIOS_FIXUP_FORCE) { 710 /* routed by BIOS, but inconsistent */ 711 /* believe PCI IRQ Routing table */ 712 p = " WARNING: overriding"; 713 ihp->line = irq = l->irq; 714 } else { 715 /* believe PCI Interrupt Configuration Register (default) */ 716 p = " WARNING: preserving"; 717 ihp->line = (l->irq = irq) | (l->clink & PCI_INT_VIA_ISA); 718 } 719 720 if (pcibios_flags & PCIBIOS_INTRDEBUG) { 721 pcireg_t id = pci_conf_read(pc, tag, PCI_ID_REG); 722 723 printf("\n%d:%d:%d %04x:%04x pin %c clink 0x%02x irq %d " 724 "stage %d %s irq %d\n", bus, device, function, 725 PCI_VENDOR(id), PCI_PRODUCT(id), '@' + ihp->pin, l->clink, 726 ((l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION)? 727 -1 : l->irq), l->fixup_stage, p, irq); 728 } 729 730 return (1); 731 } 732 733 int 734 pci_intr_fixup(struct pcibios_softc *sc, pci_chipset_tag_t pc, 735 bus_space_tag_t iot) 736 { 737 struct pcibios_pir_header *pirh = &pcibios_pir_header; 738 const struct pciintr_icu_table *piit = NULL; 739 pcitag_t icutag; 740 741 /* 742 * Attempt to initialize our PCI interrupt router. If 743 * the PIR Table is present in ROM, use the location 744 * specified by the PIR Table, and use the compat ID, 745 * if present. Otherwise, we have to look for the router 746 * ourselves (the PCI-ISA bridge). 747 * 748 * A number of buggy BIOS implementations leave the router 749 * entry as 000:00:0, which is typically not the correct 750 * device/function. If the router device address is set to 751 * this value, and the compatible router entry is undefined 752 * (zero is the correct value to indicate undefined), then we 753 * work on the basis it is most likely an error, and search 754 * the entire device-space of bus 0 (but obviously starting 755 * with 000:00:0, in case that really is the right one). 756 */ 757 if (pirh->signature != 0 && (pirh->router_bus != 0 || 758 pirh->router_devfunc != 0 || pirh->compat_router != 0)) { 759 760 icutag = pci_make_tag(pc, pirh->router_bus, 761 PIR_DEVFUNC_DEVICE(pirh->router_devfunc), 762 PIR_DEVFUNC_FUNCTION(pirh->router_devfunc)); 763 if (pirh->compat_router == 0 || 764 (piit = pciintr_icu_lookup(pirh->compat_router)) == NULL) { 765 /* 766 * No compat ID, or don't know the compat ID? Read 767 * it from the configuration header. 768 */ 769 pirh->compat_router = pci_conf_read(pc, icutag, 770 PCI_ID_REG); 771 } 772 if (piit == NULL) 773 piit = pciintr_icu_lookup(pirh->compat_router); 774 } else { 775 int device, maxdevs = pci_bus_maxdevs(pc, 0); 776 777 /* 778 * Search configuration space for a known interrupt 779 * router. 780 */ 781 for (device = 0; device < maxdevs; device++) { 782 const struct pci_quirkdata *qd; 783 int function, nfuncs; 784 pcireg_t icuid; 785 pcireg_t bhlcr; 786 787 icutag = pci_make_tag(pc, 0, device, 0); 788 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 789 790 /* Invalid vendor ID value? */ 791 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 792 continue; 793 /* XXX Not invalid, but we've done this ~forever. */ 794 if (PCI_VENDOR(icuid) == 0) 795 continue; 796 797 qd = pci_lookup_quirkdata(PCI_VENDOR(icuid), 798 PCI_PRODUCT(icuid)); 799 800 bhlcr = pci_conf_read(pc, icutag, PCI_BHLC_REG); 801 if (PCI_HDRTYPE_MULTIFN(bhlcr) || (qd != NULL && 802 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 803 nfuncs = 8; 804 else 805 nfuncs = 1; 806 807 for (function = 0; function < nfuncs; function++) { 808 icutag = pci_make_tag(pc, 0, device, function); 809 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 810 811 /* Invalid vendor ID value? */ 812 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 813 continue; 814 /* Not invalid, but we've done this ~forever. */ 815 if (PCI_VENDOR(icuid) == 0) 816 continue; 817 818 if ((piit = pciintr_icu_lookup(icuid))) { 819 pirh->compat_router = icuid; 820 pirh->router_bus = 0; 821 pirh->router_devfunc = 822 PIR_DEVFUNC_COMPOSE(device, 0); 823 break; 824 } 825 } 826 827 if (piit != NULL) 828 break; 829 } 830 } 831 832 if (piit == NULL) { 833 printf("%s: no compatible PCI ICU found", sc->sc_dev.dv_xname); 834 if (pirh->signature != 0 && pirh->compat_router != 0) 835 printf(": ICU vendor 0x%04x product 0x%04x", 836 PCI_VENDOR(pirh->compat_router), 837 PCI_PRODUCT(pirh->compat_router)); 838 printf("\n"); 839 if (!(pcibios_flags & PCIBIOS_INTR_GUESS)) { 840 if (pciintr_link_init(pc)) 841 return (-1); /* non-fatal */ 842 if (pciintr_guess_irq()) 843 return (-1); /* non-fatal */ 844 } 845 return (0); 846 } else { 847 char devinfo[256]; 848 849 printf("%s: PCI Interrupt Router at %03d:%02d:%01d", 850 sc->sc_dev.dv_xname, pirh->router_bus, 851 PIR_DEVFUNC_DEVICE(pirh->router_devfunc), 852 PIR_DEVFUNC_FUNCTION(pirh->router_devfunc)); 853 if (pirh->compat_router != 0) { 854 pci_devinfo(pirh->compat_router, 0, 0, devinfo, 855 sizeof devinfo); 856 printf(" (%s)", devinfo); 857 } 858 printf("\n"); 859 } 860 861 /* 862 * Initialize the PCI ICU. 863 */ 864 if ((*piit->piit_init)(pc, iot, icutag, &pciintr_icu_tag, 865 &pciintr_icu_handle) != 0) 866 return (-1); /* non-fatal */ 867 868 /* 869 * Initialize the PCI interrupt link map. 870 */ 871 if (pciintr_link_init(pc)) 872 return (-1); /* non-fatal */ 873 874 /* 875 * Fix up the link->IRQ mappings. 876 */ 877 if (pciintr_link_fixup() != 0) 878 return (-1); /* non-fatal */ 879 880 return (0); 881 } 882