1 /* $OpenBSD: pci_intr_fixup.c,v 1.28 2003/07/30 05:26:33 mickey Exp $ */ 2 /* $NetBSD: pci_intr_fixup.c,v 1.10 2000/08/10 21:18:27 soda Exp $ */ 3 4 /* 5 * Copyright (c) 2001 Michael Shalayeff 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 21 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /*- 30 * Copyright (c) 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 35 * NASA Ames Research Center. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by the NetBSD 48 * Foundation, Inc. and its contributors. 49 * 4. Neither the name of The NetBSD Foundation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 55 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 56 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 57 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 58 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 59 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 60 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 61 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 62 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 63 * POSSIBILITY OF SUCH DAMAGE. 64 */ 65 /* 66 * Copyright (c) 1999, by UCHIYAMA Yasushi 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. The name of the developer may NOT be used to endorse or promote products 75 * derived from this software without specific prior written permission. 76 * 77 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 78 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 79 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 80 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 81 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 82 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 83 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 84 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 85 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 86 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 87 * SUCH DAMAGE. 88 */ 89 90 /* 91 * PCI Interrupt Router support. 92 */ 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/kernel.h> 97 #include <sys/malloc.h> 98 #include <sys/queue.h> 99 #include <sys/device.h> 100 101 #include <machine/bus.h> 102 #include <machine/intr.h> 103 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcivar.h> 106 #include <dev/pci/pcidevs.h> 107 108 #include <i386/isa/icu.h> 109 #include <i386/pci/pcibiosvar.h> 110 111 struct pciintr_link_map { 112 int link, clink, irq, fixup_stage; 113 u_int16_t bitmap; 114 SIMPLEQ_ENTRY(pciintr_link_map) list; 115 }; 116 117 pciintr_icu_tag_t pciintr_icu_tag = NULL; 118 pciintr_icu_handle_t pciintr_icu_handle; 119 120 #ifdef PCIBIOS_IRQS_HINT 121 int pcibios_irqs_hint = PCIBIOS_IRQS_HINT; 122 #endif 123 124 struct pciintr_link_map *pciintr_link_lookup(int); 125 struct pcibios_intr_routing *pciintr_pir_lookup(int, int); 126 int pciintr_bitmap_count_irq(int, int *); 127 128 SIMPLEQ_HEAD(, pciintr_link_map) pciintr_link_map_list; 129 130 const struct pciintr_icu_table { 131 pci_vendor_id_t piit_vendor; 132 pci_product_id_t piit_product; 133 int (*piit_init)(pci_chipset_tag_t, 134 bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *, 135 pciintr_icu_handle_t *); 136 } pciintr_icu_table[] = { 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371MX, 138 piix_init }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_ISA, 140 piix_init }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371FB_ISA, 142 piix_init }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371SB_ISA, 144 piix_init }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC, 146 piix_init }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC, 148 piix_init }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC, 150 piix_init }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC, 152 piix_init }, 153 154 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558, 155 opti82c558_init }, 156 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C700, 157 opti82c700_init }, 158 159 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C596A, 160 via82c586_init, }, 161 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_ISA, 162 via82c586_init, }, 163 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C686A_ISA, 164 via82c586_init }, 165 166 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8231_ISA, 167 via8231_init }, 168 169 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503, 170 sis85c503_init }, 171 172 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC756_PMC, 173 amd756_init }, 174 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_766_ISA, 175 amd756_init }, 176 177 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1543, 178 ali1543_init }, 179 180 { 0, 0, 181 NULL }, 182 }; 183 184 const struct pciintr_icu_table *pciintr_icu_lookup(pcireg_t); 185 186 const struct pciintr_icu_table * 187 pciintr_icu_lookup(id) 188 pcireg_t id; 189 { 190 const struct pciintr_icu_table *piit; 191 192 for (piit = pciintr_icu_table; piit->piit_init != NULL; piit++) 193 if (PCI_VENDOR(id) == piit->piit_vendor && 194 PCI_PRODUCT(id) == piit->piit_product) 195 return (piit); 196 197 return (NULL); 198 } 199 200 struct pciintr_link_map * 201 pciintr_link_lookup(link) 202 int link; 203 { 204 struct pciintr_link_map *l; 205 206 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 207 l = SIMPLEQ_NEXT(l, list)) 208 if (l->link == link) 209 return (l); 210 211 return (NULL); 212 } 213 214 static __inline struct pciintr_link_map * 215 pciintr_link_alloc(pci_chipset_tag_t pc, struct pcibios_intr_routing *pir, int pin) 216 { 217 int link = pir->linkmap[pin].link, clink, irq; 218 struct pciintr_link_map *l, *lstart; 219 220 if (pciintr_icu_tag != NULL) { 221 /* 222 * Get the canonical link value for this entry. 223 */ 224 if (pciintr_icu_getclink(pciintr_icu_tag, pciintr_icu_handle, 225 link, &clink) != 0) { 226 /* 227 * ICU doesn't understand the link value. 228 * Just ignore this PIR entry. 229 */ 230 PCIBIOS_PRINTV(("pciintr_link_alloc: bus %d device %d: " 231 "ignoring link 0x%02x\n", pir->bus, 232 PIR_DEVFUNC_DEVICE(pir->device), link)); 233 return (NULL); 234 } 235 236 /* 237 * Check the link value by asking the ICU for the 238 * canonical link value. 239 * Also, determine if this PIRQ is mapped to an IRQ. 240 */ 241 if (pciintr_icu_get_intr(pciintr_icu_tag, pciintr_icu_handle, 242 clink, &irq) != 0) { 243 /* 244 * ICU doesn't understand the canonical link value. 245 * Just ignore this PIR entry. 246 */ 247 PCIBIOS_PRINTV(("pciintr_link_alloc: " 248 "bus %d device %d link 0x%02x: " 249 "ignoring PIRQ 0x%02x\n", pir->bus, 250 PIR_DEVFUNC_DEVICE(pir->device), link, clink)); 251 return (NULL); 252 } 253 } 254 255 if ((l = malloc(sizeof(*l), M_DEVBUF, M_NOWAIT)) == NULL) 256 return (NULL); 257 258 memset(l, 0, sizeof(*l)); 259 260 l->link = link; 261 l->bitmap = pir->linkmap[pin].bitmap; 262 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */ 263 l->clink = clink; 264 l->irq = irq; /* maybe I386_PCI_INTERRUPT_LINE_NO_CONNECTION */ 265 } else { 266 l->clink = link; 267 l->irq = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 268 } 269 270 lstart = SIMPLEQ_FIRST(&pciintr_link_map_list); 271 if (lstart == NULL || lstart->link < l->link) 272 SIMPLEQ_INSERT_TAIL(&pciintr_link_map_list, l, list); 273 else 274 SIMPLEQ_INSERT_HEAD(&pciintr_link_map_list, l, list); 275 276 return (l); 277 } 278 279 struct pcibios_intr_routing * 280 pciintr_pir_lookup(bus, device) 281 int bus, device; 282 { 283 struct pcibios_intr_routing *pir; 284 int entry; 285 286 if (pcibios_pir_table == NULL) 287 return (NULL); 288 289 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 290 pir = &pcibios_pir_table[entry]; 291 if (pir->bus == bus && 292 PIR_DEVFUNC_DEVICE(pir->device) == device) 293 return (pir); 294 } 295 296 return (NULL); 297 } 298 299 int 300 pciintr_bitmap_count_irq(irq_bitmap, irqp) 301 int irq_bitmap, *irqp; 302 { 303 int i, bit, count = 0, irq = I386_PCI_INTERRUPT_LINE_NO_CONNECTION; 304 305 if (irq_bitmap != 0) 306 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) 307 if (irq_bitmap & bit) { 308 irq = i; 309 count++; 310 } 311 312 *irqp = irq; 313 return (count); 314 } 315 316 static __inline int 317 pciintr_link_init(pci_chipset_tag_t pc) 318 { 319 int entry, pin, link; 320 struct pcibios_intr_routing *pir; 321 struct pciintr_link_map *l; 322 323 if (pcibios_pir_table == NULL) { 324 /* No PIR table; can't do anything. */ 325 printf("pciintr_link_init: no PIR table\n"); 326 return (1); 327 } 328 329 SIMPLEQ_INIT(&pciintr_link_map_list); 330 331 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) { 332 pir = &pcibios_pir_table[entry]; 333 for (pin = 0; pin < PCI_INTERRUPT_PIN_MAX; pin++) { 334 if ((link = pir->linkmap[pin].link) == 0) 335 /* No connection for this pin. */ 336 continue; 337 338 /* 339 * Multiple devices may be wired to the same 340 * interrupt; check to see if we've seen this 341 * one already. If not, allocate a new link 342 * map entry and stuff it in the map. 343 */ 344 if ((l = pciintr_link_lookup(link)) == NULL) 345 pciintr_link_alloc(pc, pir, pin); 346 else if (pir->linkmap[pin].bitmap != l->bitmap) { 347 /* 348 * violates PCI IRQ Routing Table Specification 349 */ 350 PCIBIOS_PRINTV(("pciintr_link_init: " 351 "bus %d device %d link 0x%02x: " 352 "bad irq bitmap 0x%04x, " 353 "should be 0x%04x\n", pir->bus, 354 PIR_DEVFUNC_DEVICE(pir->device), link, 355 pir->linkmap[pin].bitmap, l->bitmap)); 356 /* safer value. */ 357 l->bitmap &= pir->linkmap[pin].bitmap; 358 /* XXX - or, should ignore this entry? */ 359 } 360 } 361 } 362 363 return (0); 364 } 365 366 /* 367 * No compatible PCI ICU found. 368 * Hopes the BIOS already setup the ICU. 369 */ 370 static __inline int 371 pciintr_guess_irq(void) 372 { 373 struct pciintr_link_map *l; 374 int irq, guessed = 0; 375 376 /* 377 * Stage 1: If only one IRQ is available for the link, use it. 378 */ 379 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 380 l = SIMPLEQ_NEXT(l, list)) { 381 if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 382 continue; 383 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 384 l->irq = irq; 385 l->fixup_stage = 1; 386 if (pcibios_flags & PCIBIOS_INTRDEBUG) 387 printf("pciintr_guess_irq (stage 1): " 388 "guessing PIRQ 0x%02x to be IRQ %d\n", 389 l->clink, l->irq); 390 guessed = 1; 391 } 392 } 393 394 return (guessed ? 0 : -1); 395 } 396 397 static __inline int 398 pciintr_link_fixup(void) 399 { 400 struct pciintr_link_map *l; 401 u_int16_t pciirq = 0; 402 int irq; 403 404 /* 405 * First stage: Attempt to connect PIRQs which aren't 406 * yet connected. 407 */ 408 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 409 l = SIMPLEQ_NEXT(l, list)) { 410 if (l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 411 /* 412 * Interrupt is already connected. Don't do 413 * anything to it. 414 * In this case, l->fixup_stage == 0. 415 */ 416 pciirq |= 1 << l->irq; 417 if (pcibios_flags & PCIBIOS_INTRDEBUG) 418 printf("pciintr_link_fixup: PIRQ 0x%02x is " 419 "already connected to IRQ %d\n", 420 l->clink, l->irq); 421 continue; 422 } 423 /* 424 * Interrupt isn't connected. Attempt to assign it to an IRQ. 425 */ 426 if (pcibios_flags & PCIBIOS_INTRDEBUG) 427 printf("pciintr_link_fixup: PIRQ 0x%02x not connected", 428 l->clink); 429 430 /* 431 * Just do the easy case now; we'll defer the harder ones 432 * to Stage 2. 433 */ 434 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) { 435 l->irq = irq; 436 l->fixup_stage = 1; 437 pciirq |= 1 << irq; 438 if (pcibios_flags & PCIBIOS_INTRDEBUG) 439 printf(", assigning IRQ %d", l->irq); 440 } 441 if (pcibios_flags & PCIBIOS_INTRDEBUG) 442 printf("\n"); 443 } 444 445 /* 446 * Stage 2: Attempt to connect PIRQs which we didn't 447 * connect in Stage 1. 448 */ 449 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 450 l = SIMPLEQ_NEXT(l, list)) 451 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION && 452 (irq = ffs(l->bitmap & pciirq)) > 0) { 453 /* 454 * This IRQ is a valid PCI IRQ already 455 * connected to another PIRQ, and also an 456 * IRQ our PIRQ can use; connect it up! 457 */ 458 l->fixup_stage = 2; 459 l->irq = irq - 1; 460 if (pcibios_flags & PCIBIOS_INTRDEBUG) 461 printf("pciintr_link_fixup (stage 2): " 462 "assigning IRQ %d to PIRQ 0x%02x\n", 463 l->irq, l->clink); 464 } 465 466 #ifdef PCIBIOS_IRQS_HINT 467 /* 468 * Stage 3: The worst case. I need configuration hint that 469 * user supplied a mask for the PCI irqs 470 */ 471 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); l != NULL; 472 l = SIMPLEQ_NEXT(l, list)) { 473 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION && 474 (irq = ffs(l->bitmap & pcibios_irqs_hint)) > 0) { 475 l->fixup_stage = 3; 476 l->irq = irq - 1; 477 if (pcibios_flags & PCIBIOS_INTRDEBUG) 478 printf("pciintr_link_fixup (stage 3): " 479 "assigning IRQ %d to PIRQ 0x%02x\n", 480 l->irq, l->clink); 481 } 482 } 483 #endif /* PCIBIOS_IRQS_HINT */ 484 485 if (pcibios_flags & PCIBIOS_INTRDEBUG) 486 printf("pciintr_link_fixup: piirq 0x%04x\n", pciirq); 487 488 return (0); 489 } 490 491 int 492 pci_intr_route_link(pc, ihp) 493 pci_chipset_tag_t pc; 494 pci_intr_handle_t *ihp; 495 { 496 struct pciintr_link_map *l; 497 pcireg_t intr; 498 int rv = 1; 499 char *p = NULL; 500 501 if (pcibios_flags & PCIBIOS_INTR_FIXUP) 502 return 1; 503 504 if (ihp->line != 0 && 505 ihp->line != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 506 pcibios_pir_header.exclusive_irq |= (1 << ihp->line); 507 508 l = ihp->link; 509 if (!l || pciintr_icu_tag == NULL) 510 return (1); 511 512 if (l->fixup_stage == 0) { 513 if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 514 /* Appropriate interrupt was not found. */ 515 if (pcibios_flags & PCIBIOS_INTRDEBUG) 516 printf("pci_intr_route_link: PIRQ 0x%02x: " 517 "no IRQ, try " 518 "\"option PCIBIOS_IRQS_HINT=0x%04x\"\n", 519 l->clink, 520 /* suggest irq 9/10/11, if possible */ 521 (l->bitmap & 0x0e00) ? (l->bitmap & 0x0e00) 522 : l->bitmap); 523 } else 524 p = " preserved BIOS setting"; 525 } else { 526 527 if (pciintr_icu_set_intr(pciintr_icu_tag, pciintr_icu_handle, 528 l->clink, l->irq) != 0 || 529 pciintr_icu_set_trigger(pciintr_icu_tag, pciintr_icu_handle, 530 l->irq, IST_LEVEL) != 0) { 531 p = " failed"; 532 rv = 0; 533 } else 534 p = ""; 535 } 536 if (p && pcibios_flags & PCIBIOS_INTRDEBUG) 537 printf("pci_intr_route_link: route PIRQ 0x%02x -> IRQ %d%s\n", 538 l->clink, l->irq, p); 539 540 if (!rv) 541 return (0); 542 543 /* 544 * IRQs 14 and 15 are reserved for PCI IDE interrupts; don't muck 545 * with them. 546 */ 547 if (ihp->line == 14 || ihp->line == 15) 548 return (1); 549 550 intr = pci_conf_read(pc, ihp->tag, PCI_INTERRUPT_REG); 551 if (ihp->line != PCI_INTERRUPT_LINE(intr)) { 552 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 553 intr |= (ihp->line << PCI_INTERRUPT_LINE_SHIFT); 554 pci_conf_write(pc, ihp->tag, PCI_INTERRUPT_REG, intr); 555 } 556 557 return (1); 558 } 559 560 int 561 pci_intr_post_fixup() 562 { 563 struct pciintr_link_map *l; 564 int i, pciirq; 565 566 if (pcibios_flags & PCIBIOS_INTR_FIXUP) 567 return 1; 568 569 if (!pciintr_icu_handle) 570 return 0; 571 572 pciirq = pcibios_pir_header.exclusive_irq; 573 if (pcibios_flags & PCIBIOS_INTRDEBUG) 574 printf("pci_intr_post_fixup: PCI IRQs:"); 575 for (l = SIMPLEQ_FIRST(&pciintr_link_map_list); 576 l != NULL; l = SIMPLEQ_NEXT(l, list)) 577 if (l->fixup_stage == 0 && l->irq != 0 && 578 l->irq != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 579 if (pcibios_flags & PCIBIOS_INTRDEBUG) 580 printf(" %d", l->irq); 581 pciirq |= (1 << l->irq); 582 } 583 584 if (pcibios_flags & PCIBIOS_INTRDEBUG) 585 printf("; ISA IRQs:"); 586 for (i = 0; i < 16; i++) 587 if (!(pciirq & (1 << i))) { 588 if (pcibios_flags & PCIBIOS_INTRDEBUG) 589 printf(" %d", i); 590 pciintr_icu_set_trigger(pciintr_icu_tag, 591 pciintr_icu_handle, i, IST_EDGE); 592 } 593 594 if (pcibios_flags & PCIBIOS_INTRDEBUG) 595 printf("\n"); 596 597 return (0); 598 } 599 600 int 601 pci_intr_header_fixup(pc, tag, ihp) 602 pci_chipset_tag_t pc; 603 pcitag_t tag; 604 pci_intr_handle_t *ihp; 605 { 606 struct pcibios_intr_routing *pir; 607 struct pciintr_link_map *l; 608 int irq, link, bus, device, function; 609 char *p = NULL; 610 611 if (pcibios_flags & PCIBIOS_INTR_FIXUP) 612 return 1; 613 614 irq = ihp->line; 615 ihp->link = NULL; 616 ihp->tag = tag; 617 pci_decompose_tag(pc, tag, &bus, &device, &function); 618 619 if ((pir = pciintr_pir_lookup(bus, device)) == NULL || 620 (link = pir->linkmap[ihp->pin - 1].link) == 0) { 621 PCIBIOS_PRINTV(("Interrupt not connected; no need to change.")); 622 return 1; 623 } 624 625 if ((l = pciintr_link_lookup(link)) == NULL) { 626 /* 627 * No link map entry. 628 * Probably pciintr_icu_getclink() or pciintr_icu_get_intr() 629 * was failed. 630 */ 631 if (pcibios_flags & PCIBIOS_INTRDEBUG) 632 printf("pci_intr_header_fixup: no entry for link " 633 "0x%02x (%d:%d:%d:%c)\n", 634 link, bus, device, function, '@' + ihp->pin); 635 return 1; 636 } 637 638 ihp->link = l; 639 if (irq == 14 || irq == 15) 640 p = " WARNING: ignored"; 641 else if (l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 642 643 /* Appropriate interrupt was not found. */ 644 if (pciintr_icu_tag == NULL && ihp->line != 0 && 645 ihp->line != I386_PCI_INTERRUPT_LINE_NO_CONNECTION) 646 /* 647 * Do not print warning, 648 * if no compatible PCI ICU found, 649 * but the irq is already assigned by BIOS. 650 */ 651 p = ""; 652 else 653 p = " WARNING: missing"; 654 } else if (irq == 0 || irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION) { 655 656 p = " fixed up"; 657 ihp->line = l->irq; 658 659 } else { 660 /* routed by BIOS, but inconsistent */ 661 #ifdef PCIBIOS_INTR_FIXUP_FORCE 662 /* believe PCI IRQ Routing table */ 663 p = " WARNING: overriding"; 664 ihp->line = l->irq; 665 #else 666 /* believe PCI Interrupt Configuration Register (default) */ 667 p = " WARNING: preserving"; 668 #endif 669 } 670 671 if (pcibios_flags & PCIBIOS_INTRDEBUG) { 672 register pcireg_t id = pci_conf_read(pc, tag, PCI_ID_REG); 673 674 printf("%d:%d:%d %04x:%04x pin %c clink 0x%02x irq %d stage %d" 675 "%s irq %d\n", bus, device, function, 676 PCI_VENDOR(id), PCI_PRODUCT(id), '@' + ihp->pin, l->clink, 677 ((l->irq == I386_PCI_INTERRUPT_LINE_NO_CONNECTION)? 678 -1 : l->irq), l->fixup_stage, p, irq); 679 } 680 681 return (1); 682 } 683 684 int 685 pci_intr_fixup(sc, pc, iot) 686 struct pcibios_softc *sc; 687 pci_chipset_tag_t pc; 688 bus_space_tag_t iot; 689 { 690 struct pcibios_pir_header *pirh = &pcibios_pir_header; 691 const struct pciintr_icu_table *piit = NULL; 692 pcitag_t icutag; 693 694 /* 695 * Attempt to initialize our PCI interrupt router. If 696 * the PIR Table is present in ROM, use the location 697 * specified by the PIR Table, and use the compat ID, 698 * if present. Otherwise, we have to look for the router 699 * ourselves (the PCI-ISA bridge). 700 * 701 * A number of buggy BIOS implementations leave the router 702 * entry as 000:00:0, which is typically not the correct 703 * device/function. If the router device address is set to 704 * this value, and the compatible router entry is undefined 705 * (zero is the correct value to indicate undefined), then we 706 * work on the basis it is most likely an error, and search 707 * the entire device-space of bus 0 (but obviously starting 708 * with 000:00:0, in case that really is the right one). 709 */ 710 if (pirh->signature != 0 && (pirh->router_bus != 0 || 711 pirh->router_devfunc != 0 || pirh->compat_router != 0)) { 712 713 icutag = pci_make_tag(pc, pirh->router_bus, 714 PIR_DEVFUNC_DEVICE(pirh->router_devfunc), 715 PIR_DEVFUNC_FUNCTION(pirh->router_devfunc)); 716 if (pirh->compat_router == 0 || 717 (piit = pciintr_icu_lookup(pirh->compat_router)) == NULL) { 718 /* 719 * No compat ID, or don't know the compat ID? Read 720 * it from the configuration header. 721 */ 722 pirh->compat_router = pci_conf_read(pc, icutag, 723 PCI_ID_REG); 724 } 725 if (piit == NULL) 726 piit = pciintr_icu_lookup(pirh->compat_router); 727 } else { 728 int device, maxdevs = pci_bus_maxdevs(pc, 0); 729 730 /* 731 * Search configuration space for a known interrupt 732 * router. 733 */ 734 for (device = 0; device < maxdevs; device++) { 735 const struct pci_quirkdata *qd; 736 int function, nfuncs; 737 pcireg_t icuid; 738 pcireg_t bhlcr; 739 740 icutag = pci_make_tag(pc, 0, device, 0); 741 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 742 743 /* Invalid vendor ID value? */ 744 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 745 continue; 746 /* XXX Not invalid, but we've done this ~forever. */ 747 if (PCI_VENDOR(icuid) == 0) 748 continue; 749 750 qd = pci_lookup_quirkdata(PCI_VENDOR(icuid), 751 PCI_PRODUCT(icuid)); 752 753 bhlcr = pci_conf_read(pc, icutag, PCI_BHLC_REG); 754 if (PCI_HDRTYPE_MULTIFN(bhlcr) || (qd != NULL && 755 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 756 nfuncs = 8; 757 else 758 nfuncs = 1; 759 760 for (function = 0; function < nfuncs; function++) { 761 icutag = pci_make_tag(pc, 0, device, function); 762 icuid = pci_conf_read(pc, icutag, PCI_ID_REG); 763 764 /* Invalid vendor ID value? */ 765 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID) 766 continue; 767 /* Not invalid, but we've done this ~forever. */ 768 if (PCI_VENDOR(icuid) == 0) 769 continue; 770 771 if ((piit = pciintr_icu_lookup(icuid))) { 772 pirh->compat_router = icuid; 773 pirh->router_bus = 0; 774 pirh->router_devfunc = 775 PIR_DEVFUNC_COMPOSE(device, 0); 776 break; 777 } 778 } 779 780 if (piit != NULL) 781 break; 782 } 783 } 784 785 if (piit == NULL) { 786 printf("%s: no compatible PCI ICU found", sc->sc_dev.dv_xname); 787 if (pirh->signature != 0 && pirh->compat_router != 0) 788 printf(": ICU vendor 0x%04x product 0x%04x", 789 PCI_VENDOR(pirh->compat_router), 790 PCI_PRODUCT(pirh->compat_router)); 791 printf("\n"); 792 if (!(pcibios_flags & PCIBIOS_INTR_GUESS)) { 793 if (pciintr_link_init(pc)) 794 return (-1); /* non-fatal */ 795 if (pciintr_guess_irq()) 796 return (-1); /* non-fatal */ 797 return (0); /* success! */ 798 } else 799 return (-1); /* non-fatal */ 800 } else { 801 char devinfo[256]; 802 803 printf("%s: PCI Interrupt Router at %03d:%02d:%01d", 804 sc->sc_dev.dv_xname, pirh->router_bus, 805 PIR_DEVFUNC_DEVICE(pirh->router_devfunc), 806 PIR_DEVFUNC_FUNCTION(pirh->router_devfunc)); 807 if (pirh->compat_router != 0) { 808 pci_devinfo(pirh->compat_router, 0, 0, devinfo, 809 sizeof devinfo); 810 printf(" (%s)", devinfo); 811 } 812 printf("\n"); 813 } 814 815 /* 816 * Initialize the PCI ICU. 817 */ 818 if ((*piit->piit_init)(pc, iot, icutag, &pciintr_icu_tag, 819 &pciintr_icu_handle) != 0) 820 return (-1); /* non-fatal */ 821 822 /* 823 * Initialize the PCI interrupt link map. 824 */ 825 if (pciintr_link_init(pc)) 826 return (-1); /* non-fatal */ 827 828 /* 829 * Fix up the link->IRQ mappings. 830 */ 831 if (pciintr_link_fixup() != 0) 832 return (-1); /* non-fatal */ 833 834 return (0); 835 } 836