1 /* $OpenBSD: specialreg.h,v 1.57 2016/09/03 13:35:03 mlarkin Exp $ */ 2 /* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */ 3 4 /*- 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 33 */ 34 35 /* 36 * Bits in 386 special registers: 37 */ 38 #define CR0_PE 0x00000001 /* Protected mode Enable */ 39 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 40 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 41 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 42 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 43 #define CR0_PG 0x80000000 /* PaGing enable */ 44 45 /* 46 * Bits in 486 special registers: 47 */ 48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 50 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 51 #define CR0_NW 0x20000000 /* Not Write-through */ 52 #define CR0_CD 0x40000000 /* Cache Disable */ 53 54 /* 55 * Cyrix 486 DLC special registers, accessable as IO ports. 56 */ 57 #define CCR0 0xc0 /* configuration control register 0 */ 58 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 59 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 60 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 61 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 62 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 63 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 64 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 65 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 66 67 #define CCR1 0xc1 /* configuration control register 1 */ 68 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 69 /* the remaining 7 bits of this register are reserved */ 70 71 /* 72 * bits in the pentiums %cr4 register: 73 */ 74 75 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 76 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 77 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */ 78 #define CR4_DE 0x00000008 /* debugging extension */ 79 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 80 #define CR4_PAE 0x00000020 /* physical address extension enable */ 81 #define CR4_MCE 0x00000040 /* machine check enable */ 82 #define CR4_PGE 0x00000080 /* page global enable */ 83 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 84 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 85 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 86 #define CR4_UMIP 0x00000800 /* user mode instruction prevention */ 87 #define CR4_VMXE 0x00002000 /* enable virtual machine operation */ 88 #define CR4_SMXE 0x00004000 /* enable safe mode operation */ 89 #define CR4_FSGSBASE 0x00010000 /* enable {RD,WR}{FS,GS}BASE ops */ 90 #define CR4_PCIDE 0x00020000 /* enable process-context IDs */ 91 #define CR4_OSXSAVE 0x00040000 /* enable XSAVE and extended states */ 92 #define CR4_SMEP 0x00100000 /* supervisor mode exec protection */ 93 #define CR4_SMAP 0x00200000 /* supervisor mode access prevention */ 94 95 /* 96 * CPUID "features" bits (CPUID function 0x1): 97 * EDX bits, then ECX bits 98 */ 99 100 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 101 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 102 #define CPUID_DE 0x00000004 /* has debugging extension */ 103 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 104 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 105 #define CPUID_MSR 0x00000020 /* has model specific registers */ 106 #define CPUID_PAE 0x00000040 /* has phys address extension */ 107 #define CPUID_MCE 0x00000080 /* has machine check exception */ 108 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 109 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 110 #define CPUID_SYS1 0x00000400 /* has SYSCALL/SYSRET inst. (Cyrix) */ 111 #define CPUID_SEP 0x00000800 /* has SYSCALL/SYSRET inst. (AMD/Intel) */ 112 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 113 #define CPUID_PGE 0x00002000 /* has page global extension */ 114 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 115 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 116 #define CPUID_PAT 0x00010000 /* has page attribute table */ 117 #define CPUID_PSE36 0x00020000 /* has 36bit page size extension */ 118 #define CPUID_PSN 0x00040000 /* has processor serial number */ 119 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ 120 #define CPUID_B20 0x00100000 /* reserved */ 121 #define CPUID_DS 0x00200000 /* Debug Store */ 122 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 123 #define CPUID_MMX 0x00800000 /* has MMX instructions */ 124 #define CPUID_FXSR 0x01000000 /* has FXRSTOR instruction */ 125 #define CPUID_SSE 0x02000000 /* has streaming SIMD extensions */ 126 #define CPUID_SSE2 0x04000000 /* has streaming SIMD extensions #2 */ 127 #define CPUID_SS 0x08000000 /* self-snoop */ 128 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 129 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 130 #define CPUID_B30 0x40000000 /* reserved */ 131 #define CPUID_PBE 0x80000000 /* Pending Break Enabled restarts clock */ 132 133 #define CPUIDECX_SSE3 0x00000001 /* streaming SIMD extensions #3 */ 134 #define CPUIDECX_PCLMUL 0x00000002 /* Carryless Multiplication */ 135 #define CPUIDECX_DTES64 0x00000004 /* 64bit debug store */ 136 #define CPUIDECX_MWAIT 0x00000008 /* Monitor/Mwait */ 137 #define CPUIDECX_DSCPL 0x00000010 /* CPL Qualified Debug Store */ 138 #define CPUIDECX_VMX 0x00000020 /* Virtual Machine Extensions */ 139 #define CPUIDECX_SMX 0x00000040 /* Safer Mode Extensions */ 140 #define CPUIDECX_EST 0x00000080 /* enhanced SpeedStep */ 141 #define CPUIDECX_TM2 0x00000100 /* thermal monitor 2 */ 142 #define CPUIDECX_SSSE3 0x00000200 /* Supplemental Streaming SIMD Ext. 3 */ 143 #define CPUIDECX_CNXTID 0x00000400 /* Context ID */ 144 #define CPUIDECX_SDBG 0x00000800 /* Silicon debug capability */ 145 #define CPUIDECX_FMA3 0x00001000 /* Fused Multiply Add */ 146 #define CPUIDECX_CX16 0x00002000 /* has CMPXCHG16B instruction */ 147 #define CPUIDECX_XTPR 0x00004000 /* xTPR Update Control */ 148 #define CPUIDECX_PDCM 0x00008000 /* Perfmon and Debug Capability */ 149 #define CPUIDECX_PCID 0x00020000 /* Process-context ID Capability */ 150 #define CPUIDECX_DCA 0x00040000 /* Direct Cache Access */ 151 #define CPUIDECX_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 152 #define CPUIDECX_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 153 #define CPUIDECX_X2APIC 0x00200000 /* Extended xAPIC Support */ 154 #define CPUIDECX_MOVBE 0x00400000 /* MOVBE Instruction */ 155 #define CPUIDECX_POPCNT 0x00800000 /* POPCNT Instruction */ 156 #define CPUIDECX_DEADLINE 0x01000000 /* APIC one-shot via deadline */ 157 #define CPUIDECX_AES 0x02000000 /* AES Instruction */ 158 #define CPUIDECX_XSAVE 0x04000000 /* XSAVE/XSTOR States */ 159 #define CPUIDECX_OSXSAVE 0x08000000 /* OSXSAVE */ 160 #define CPUIDECX_AVX 0x10000000 /* Advanced Vector Extensions */ 161 #define CPUIDECX_F16C 0x20000000 /* 16bit fp conversion */ 162 #define CPUIDECX_RDRAND 0x40000000 /* RDRAND instruction */ 163 #define CPUIDECX_HV 0x80000000 /* Running on hypervisor */ 164 165 /* 166 * "Structured Extended Feature Flags Parameters" (CPUID function 0x7, leaf 0) 167 * EBX bits 168 */ 169 #define SEFF0EBX_FSGSBASE 0x00000001 /* {RD,WR}[FG]SBASE instructions */ 170 #define SEFF0EBX_SGX 0x00000004 /* Software Guard Extensions */ 171 #define SEFF0EBX_BMI1 0x00000008 /* advanced bit manipulation */ 172 #define SEFF0EBX_HLE 0x00000010 /* Hardware Lock Elision */ 173 #define SEFF0EBX_AVX2 0x00000020 /* Advanced Vector Extensions 2 */ 174 #define SEFF0EBX_SMEP 0x00000080 /* Supervisor mode exec protection */ 175 #define SEFF0EBX_BMI2 0x00000100 /* advanced bit manipulation */ 176 #define SEFF0EBX_ERMS 0x00000200 /* Enhanced REP MOVSB/STOSB */ 177 #define SEFF0EBX_INVPCID 0x00000400 /* INVPCID instruction */ 178 #define SEFF0EBX_RTM 0x00000800 /* Restricted Transactional Memory */ 179 #define SEFF0EBX_PQM 0x00001000 /* Quality of Service Monitoring */ 180 #define SEFF0EBX_MPX 0x00004000 /* Memory Protection Extensions */ 181 #define SEFF0EBX_AVX512F 0x00010000 /* AVX-512 foundation inst */ 182 #define SEFF0EBX_AVX512DQ 0x00020000 /* AVX-512 double/quadword */ 183 #define SEFF0EBX_RDSEED 0x00040000 /* RDSEED instruction */ 184 #define SEFF0EBX_ADX 0x00080000 /* ADCX/ADOX instructions */ 185 #define SEFF0EBX_SMAP 0x00100000 /* Supervisor mode access prevent */ 186 #define SEFF0EBX_AVX512IFMA 0x00200000 /* AVX-512 integer mult-add */ 187 #define SEFF0EBX_PCOMMIT 0x00400000 /* Persistent commit inst */ 188 #define SEFF0EBX_CLFLUSHOPT 0x00800000 /* cache line flush */ 189 #define SEFF0EBX_CLWB 0x01000000 /* cache line write back */ 190 #define SEFF0EBX_PT 0x02000000 /* Processor Trace */ 191 #define SEFF0EBX_AVX512PF 0x04000000 /* AVX-512 prefetch */ 192 #define SEFF0EBX_AVX512ER 0x08000000 /* AVX-512 exp/reciprocal */ 193 #define SEFF0EBX_AVX512CD 0x10000000 /* AVX-512 conflict detection */ 194 #define SEFF0EBX_SHA 0x20000000 /* SHA Extensions */ 195 #define SEFF0EBX_AVX512BW 0x40000000 /* AVX-512 byte/word inst */ 196 #define SEFF0EBX_AVX512VL 0x80000000 /* AVX-512 vector len inst */ 197 /* SEFF ECX bits */ 198 #define SEFF0ECX_PREFETCHWT1 0x00000001 /* PREFETCHWT1 instruction */ 199 #define SEFF0ECX_AVX512VBMI 0x00000002 /* AVX-512 vector bit inst */ 200 #define SEFF0ECX_UMIP 0x00000004 /* UMIP support */ 201 #define SEFF0ECX_PKU 0x00000008 /* Page prot keys for user mode */ 202 203 /* 204 * Thermal and Power Management (CPUID function 0x6) EAX bits 205 */ 206 #define TPM_SENSOR 0x00000001 /* Digital temp sensor */ 207 #define TPM_ARAT 0x00000004 /* APIC Timer Always Running */ 208 209 /* 210 * "Architectural Performance Monitoring" bits (CPUID function 0x0a): 211 * EAX bits 212 */ 213 214 #define CPUIDEAX_VERID 0x000000ff 215 #define CPUIDEAX_NUM_GC(cpuid) (((cpuid) >> 8) & 0x000000ff) 216 #define CPUIDEAX_BIT_GC(cpuid) (((cpuid) >> 16) & 0x000000ff) 217 #define CPUIDEAX_LEN_EBX(cpuid) (((cpuid) >> 24) & 0x000000ff) 218 219 #define CPUIDEBX_EVT_CORE (1 << 0) /* Core cycle */ 220 #define CPUIDEBX_EVT_INST (1 << 1) /* Instruction retired */ 221 #define CPUIDEBX_EVT_REFR (1 << 2) /* Reference cycles */ 222 #define CPUIDEBX_EVT_CACHE_REF (1 << 3) /* Last-level cache ref. */ 223 #define CPUIDEBX_EVT_CACHE_MIS (1 << 4) /* Last-level cache miss. */ 224 #define CPUIDEBX_EVT_BRANCH_INST (1 << 5) /* Branch instruction ret. */ 225 #define CPUIDEBX_EVT_BRANCH_MISP (1 << 6) /* Branch mispredict ret. */ 226 227 #define CPUIDEDX_NUM_FC(cpuid) (((cpuid) >> 0) & 0x0000001f) 228 #define CPUIDEDX_BIT_FC(cpuid) (((cpuid) >> 5) & 0x000000ff) 229 230 /* 231 * CPUID "extended features" bits (CPUID function 0x80000001): 232 * EDX bits, then ECX bits 233 */ 234 235 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 236 #define CPUID_NXE 0x00100000 /* No-Execute Extension */ 237 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 238 #define CPUID_FFXSR 0x02000000 /* fast FP/MMX save/restore */ 239 #define CPUID_PAGE1GB 0x04000000 /* 1-GByte pages */ 240 #define CPUID_LONG 0x20000000 /* long mode */ 241 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 242 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 243 244 #define CPUIDECX_LAHF 0x00000001 /* LAHF and SAHF instructions */ 245 #define CPUIDECX_CMPLEG 0x00000002 /* Core MP legacy mode */ 246 #define CPUIDECX_SVM 0x00000004 /* Secure Virtual Machine */ 247 #define CPUIDECX_EAPICSP 0x00000008 /* Extended APIC space */ 248 #define CPUIDECX_AMCR8 0x00000010 /* LOCK MOV CR0 means MOV CR8 */ 249 #define CPUIDECX_ABM 0x00000020 /* LZCNT instruction */ 250 #define CPUIDECX_SSE4A 0x00000040 /* SSE4-A instruction set */ 251 #define CPUIDECX_MASSE 0x00000080 /* Misaligned SSE mode */ 252 #define CPUIDECX_3DNOWP 0x00000100 /* 3DNowPrefetch */ 253 #define CPUIDECX_OSVW 0x00000200 /* OS visible workaround */ 254 #define CPUIDECX_IBS 0x00000400 /* Instruction based sampling */ 255 #define CPUIDECX_XOP 0x00000800 /* Extended operating support */ 256 #define CPUIDECX_SKINIT 0x00001000 /* SKINIT and STGI are supported */ 257 #define CPUIDECX_WDT 0x00002000 /* Watchdog timer */ 258 /* Reserved 0x00004000 */ 259 #define CPUIDECX_LWP 0x00008000 /* Lightweight profiling support */ 260 #define CPUIDECX_FMA4 0x00010000 /* 4-operand FMA instructions */ 261 /* Reserved 0x00020000 */ 262 /* Reserved 0x00040000 */ 263 #define CPUIDECX_NODEID 0x00080000 /* Support for MSRC001C */ 264 /* Reserved 0x00100000 */ 265 #define CPUIDECX_TBM 0x00200000 /* Trailing bit manipulation instruction */ 266 #define CPUIDECX_TOPEXT 0x00400000 /* Topology extensions support */ 267 268 /* 269 * "Advanced Power Management Information" bits (CPUID function 0x80000007): 270 * EDX bits. 271 */ 272 273 #define CPUIDEDX_ITSC (1 << 8) /* Invariant TSC */ 274 275 #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15) 276 #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15) 277 #define CPUID2STEPPING(cpuid) ((cpuid) & 15) 278 279 #define CPUID(code, eax, ebx, ecx, edx) \ 280 __asm volatile("cpuid" \ 281 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 282 : "a" (code)); 283 #define CPUID_LEAF(code, leaf, eax, ebx, ecx, edx) \ 284 __asm volatile("cpuid" \ 285 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 286 : "a" (code), "c" (leaf)); 287 288 289 /* 290 * Model-specific registers for the i386 family 291 */ 292 #define MSR_P5_MC_ADDR 0x000 293 #define MSR_P5_MC_TYPE 0x001 294 #define MSR_TSC 0x010 295 #define P5MSR_CTRSEL 0x011 /* P5 only (trap on P6) */ 296 #define P5MSR_CTR0 0x012 /* P5 only (trap on P6) */ 297 #define P5MSR_CTR1 0x013 /* P5 only (trap on P6) */ 298 #define MSR_APICBASE 0x01b 299 #define MSR_EBL_CR_POWERON 0x02a 300 #define MSR_EBC_FREQUENCY_ID 0x02c /* Pentium 4 only */ 301 #define MSR_TEST_CTL 0x033 302 #define MSR_BIOS_UPDT_TRIG 0x079 303 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 304 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 305 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 306 #define MSR_BIOS_SIGN 0x08b 307 #define P6MSR_CTR0 0x0c1 308 #define P6MSR_CTR1 0x0c2 309 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 310 /* 311 * for Core i Series and newer Xeons, see 312 * http://www.intel.com/content/dam/www/public/us/en/ 313 * documents/white-papers/cpu-monitoring-dts-peci-paper.pdf 314 */ 315 #define MSR_TEMPERATURE_TARGET 0x1a2 /* Core i Series, Newer Xeons */ 316 #define MSR_TEMPERATURE_TARGET_TJMAX(r) (((r) >> 16) & 0xff) 317 /* 318 * not documented anywhere, see intelcore_update_sensor() 319 * only available Core Duo and Core Solo Processors 320 */ 321 #define MSR_TEMPERATURE_TARGET_UNDOCUMENTED 0x0ee 322 #define MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED 0x40000000 323 #define MSR_MTRRcap 0x0fe 324 #define MTRRcap_FIXED 0x100 /* bit 8 - fixed MTRRs supported */ 325 #define MTRRcap_WC 0x400 /* bit 10 - WC type supported */ 326 #define MTRRcap_SMRR 0x800 /* bit 11 - SMM range reg supported */ 327 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 328 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 329 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 330 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 331 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 332 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 333 #define MSR_SYSENTER_CS 0x174 334 #define MSR_SYSENTER_ESP 0x175 335 #define MSR_SYSENTER_EIP 0x176 336 #define MSR_MCG_CAP 0x179 337 #define MSR_MCG_STATUS 0x17a 338 #define MSR_MCG_CTL 0x17b 339 #define P6MSR_CTRSEL0 0x186 340 #define P6MSR_CTRSEL1 0x187 341 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 342 #define MSR_PERF_CTL 0x199 /* Pentium M */ 343 #define PERF_CTL_TURBO 0x100000000ULL /* bit 32 - turbo mode */ 344 #define MSR_THERM_CONTROL 0x19a 345 #define MSR_THERM_INTERRUPT 0x19b 346 #define MSR_THERM_STATUS 0x19c 347 #define MSR_THERM_STATUS_VALID_BIT 0x80000000 348 #define MSR_THERM_STATUS_TEMP(msr) ((msr >> 16) & 0x7f) 349 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 350 #define MSR_MISC_ENABLE 0x1a0 351 #define MSR_DEBUGCTLMSR 0x1d9 352 #define MSR_LASTBRANCHFROMIP 0x1db 353 #define MSR_LASTBRANCHTOIP 0x1dc 354 #define MSR_LASTINTFROMIP 0x1dd 355 #define MSR_LASTINTTOIP 0x1de 356 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 357 #define MSR_MTRRvarBase 0x200 358 #define MSR_MTRRfix64K_00000 0x250 359 #define MSR_MTRRfix16K_80000 0x258 360 #define MSR_MTRRfix4K_C0000 0x268 361 #define MSR_CR_PAT 0x277 362 #define MSR_MTRRdefType 0x2ff 363 #define MTRRdefType_FIXED_ENABLE 0x400 /* bit 10 - fixed MTRR enabled */ 364 #define MTRRdefType_ENABLE 0x800 /* bit 11 - MTRRs enabled */ 365 #define MSR_PERF_FIXED_CTR1 0x30a /* CPU_CLK_Unhalted.Core */ 366 #define MSR_PERF_FIXED_CTR2 0x30b /* CPU_CLK.Unhalted.Ref */ 367 #define MSR_PERF_FIXED_CTR_CTRL 0x38d 368 #define MSR_PERF_FIXED_CTR_FC_DIS 0x0 /* disable counter */ 369 #define MSR_PERF_FIXED_CTR_FC_1 0x1 /* count ring 1 */ 370 #define MSR_PERF_FIXED_CTR_FC_123 0x2 /* count rings 1,2,3 */ 371 #define MSR_PERF_FIXED_CTR_FC_ANY 0x3 /* count everything */ 372 #define MSR_PERF_FIXED_CTR_FC_MASK 0x3 373 #define MSR_PERF_FIXED_CTR_FC(_i, _v) ((_v) << (4 * (_i))) 374 #define MSR_PERF_FIXED_CTR_ANYTHR(_i) (0x4 << (4 * (_i))) 375 #define MSR_PERF_FIXED_CTR_INT(_i) (0x8 << (4 * (_i))) 376 #define MSR_PERF_GLOBAL_CTRL 0x38f 377 #define MSR_PERF_GLOBAL_CTR1_EN (1ULL << 33) 378 #define MSR_PERF_GLOBAL_CTR2_EN (1ULL << 34) 379 #define MSR_MC0_CTL 0x400 380 #define MSR_MC0_STATUS 0x401 381 #define MSR_MC0_ADDR 0x402 382 #define MSR_MC0_MISC 0x403 383 #define MSR_MC1_CTL 0x404 384 #define MSR_MC1_STATUS 0x405 385 #define MSR_MC1_ADDR 0x406 386 #define MSR_MC1_MISC 0x407 387 #define MSR_MC2_CTL 0x408 388 #define MSR_MC2_STATUS 0x409 389 #define MSR_MC2_ADDR 0x40a 390 #define MSR_MC2_MISC 0x40b 391 #define MSR_MC4_CTL 0x40c 392 #define MSR_MC4_STATUS 0x40d 393 #define MSR_MC4_ADDR 0x40e 394 #define MSR_MC4_MISC 0x40f 395 #define MSR_MC3_CTL 0x410 396 #define MSR_MC3_STATUS 0x411 397 #define MSR_MC3_ADDR 0x412 398 #define MSR_MC3_MISC 0x413 399 400 /* VIA MSRs */ 401 #define MSR_CENT_TMTEMPERATURE 0x1423 /* Thermal monitor temperature */ 402 #define MSR_C7M_TMTEMPERATURE 0x1169 403 404 /* AMD MSRs */ 405 #define MSR_K6_EPMR 0xc0000086 406 #define MSR_K7_EVNTSEL0 0xc0010000 407 #define MSR_K7_EVNTSEL1 0xc0010001 408 #define MSR_K7_EVNTSEL2 0xc0010002 409 #define MSR_K7_EVNTSEL3 0xc0010003 410 #define MSR_K7_PERFCTR0 0xc0010004 411 #define MSR_K7_PERFCTR1 0xc0010005 412 #define MSR_K7_PERFCTR2 0xc0010006 413 #define MSR_K7_PERFCTR3 0xc0010007 414 415 /* 416 * AMD K8 (Opteron) MSRs. 417 */ 418 #define MSR_SYSCFG 0xc0000010 419 420 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 421 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 422 #define EFER_LME 0x00000100 /* Long Mode Active */ 423 #define EFER_LMA 0x00000400 /* Long Mode Enabled */ 424 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 425 426 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 427 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 428 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 429 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 430 431 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 432 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 433 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 434 #define MSR_INT_PEN_MSG 0xc0010055 /* Interrupt pending message */ 435 436 #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */ 437 #define DE_CFG_721 0x00000001 /* errata 721 */ 438 439 #define IPM_C1E_CMP_HLT 0x10000000 440 #define IPM_SMI_CMP_HLT 0x08000000 441 442 /* 443 * These require a 'passcode' for access. See cpufunc.h. 444 */ 445 #define MSR_HWCR 0xc0010015 446 #define HWCR_FFDIS 0x00000040 447 448 #define MSR_NB_CFG 0xc001001f 449 #define NB_CFG_DISIOREQLOCK 0x0000000000000004ULL 450 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 451 452 #define MSR_LS_CFG 0xc0011020 453 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 454 455 #define MSR_IC_CFG 0xc0011021 456 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 457 458 #define MSR_DC_CFG 0xc0011022 459 #define DC_CFG_DIS_CNV_WC_SSO 0x00000004 460 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 461 462 #define MSR_BU_CFG 0xc0011023 463 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 464 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 465 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 466 467 /* 468 * Constants related to MTRRs 469 */ 470 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 471 #define MTRR_N16K 16 472 #define MTRR_N4K 64 473 474 /* 475 * the following four 3-byte registers control the non-cacheable regions. 476 * These registers must be written as three separate bytes. 477 * 478 * NCRx+0: A31-A24 of starting address 479 * NCRx+1: A23-A16 of starting address 480 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 481 * 482 * The non-cacheable region's starting address must be aligned to the 483 * size indicated by the NCR_SIZE_xx field. 484 */ 485 #define NCR1 0xc4 486 #define NCR2 0xc7 487 #define NCR3 0xca 488 #define NCR4 0xcd 489 490 #define NCR_SIZE_0K 0 491 #define NCR_SIZE_4K 1 492 #define NCR_SIZE_8K 2 493 #define NCR_SIZE_16K 3 494 #define NCR_SIZE_32K 4 495 #define NCR_SIZE_64K 5 496 #define NCR_SIZE_128K 6 497 #define NCR_SIZE_256K 7 498 #define NCR_SIZE_512K 8 499 #define NCR_SIZE_1M 9 500 #define NCR_SIZE_2M 10 501 #define NCR_SIZE_4M 11 502 #define NCR_SIZE_8M 12 503 #define NCR_SIZE_16M 13 504 #define NCR_SIZE_32M 14 505 #define NCR_SIZE_4G 15 506 507 /* 508 * Performance monitor events. 509 * 510 * Note that 586-class and 686-class CPUs have different performance 511 * monitors available, and they are accessed differently: 512 * 513 * 686-class: `rdpmc' instruction 514 * 586-class: `rdmsr' instruction, CESR MSR 515 * 516 * The descriptions of these events are too lenghy to include here. 517 * See Appendix A of "Intel Architecture Software Developer's 518 * Manual, Volume 3: System Programming" for more information. 519 */ 520 521 /* 522 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 523 * is CTR1. 524 */ 525 526 #define PMC5_CESR_EVENT 0x003f 527 #define PMC5_CESR_OS 0x0040 528 #define PMC5_CESR_USR 0x0080 529 #define PMC5_CESR_E 0x0100 530 #define PMC5_CESR_P 0x0200 531 532 /* 533 * 686-class Event Selector MSR format. 534 */ 535 536 #define PMC6_EVTSEL_EVENT 0x000000ff 537 #define PMC6_EVTSEL_UNIT 0x0000ff00 538 #define PMC6_EVTSEL_UNIT_SHIFT 8 539 #define PMC6_EVTSEL_USR (1 << 16) 540 #define PMC6_EVTSEL_OS (1 << 17) 541 #define PMC6_EVTSEL_E (1 << 18) 542 #define PMC6_EVTSEL_PC (1 << 19) 543 #define PMC6_EVTSEL_INT (1 << 20) 544 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 545 #define PMC6_EVTSEL_INV (1 << 23) 546 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 547 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 548 549 /* Data Cache Unit */ 550 #define PMC6_DATA_MEM_REFS 0x43 551 #define PMC6_DCU_LINES_IN 0x45 552 #define PMC6_DCU_M_LINES_IN 0x46 553 #define PMC6_DCU_M_LINES_OUT 0x47 554 #define PMC6_DCU_MISS_OUTSTANDING 0x48 555 556 /* Instruction Fetch Unit */ 557 #define PMC6_IFU_IFETCH 0x80 558 #define PMC6_IFU_IFETCH_MISS 0x81 559 #define PMC6_ITLB_MISS 0x85 560 #define PMC6_IFU_MEM_STALL 0x86 561 #define PMC6_ILD_STALL 0x87 562 563 /* L2 Cache */ 564 #define PMC6_L2_IFETCH 0x28 565 #define PMC6_L2_LD 0x29 566 #define PMC6_L2_ST 0x2a 567 #define PMC6_L2_LINES_IN 0x24 568 #define PMC6_L2_LINES_OUT 0x26 569 #define PMC6_L2_M_LINES_INM 0x25 570 #define PMC6_L2_M_LINES_OUTM 0x27 571 #define PMC6_L2_RQSTS 0x2e 572 #define PMC6_L2_ADS 0x21 573 #define PMC6_L2_DBUS_BUSY 0x22 574 #define PMC6_L2_DBUS_BUSY_RD 0x23 575 576 /* External Bus Logic */ 577 #define PMC6_BUS_DRDY_CLOCKS 0x62 578 #define PMC6_BUS_LOCK_CLOCKS 0x63 579 #define PMC6_BUS_REQ_OUTSTANDING 0x60 580 #define PMC6_BUS_TRAN_BRD 0x65 581 #define PMC6_BUS_TRAN_RFO 0x66 582 #define PMC6_BUS_TRANS_WB 0x67 583 #define PMC6_BUS_TRAN_IFETCH 0x68 584 #define PMC6_BUS_TRAN_INVAL 0x69 585 #define PMC6_BUS_TRAN_PWR 0x6a 586 #define PMC6_BUS_TRANS_P 0x6b 587 #define PMC6_BUS_TRANS_IO 0x6c 588 #define PMC6_BUS_TRAN_DEF 0x6d 589 #define PMC6_BUS_TRAN_BURST 0x6e 590 #define PMC6_BUS_TRAN_ANY 0x70 591 #define PMC6_BUS_TRAN_MEM 0x6f 592 #define PMC6_BUS_DATA_RCV 0x64 593 #define PMC6_BUS_BNR_DRV 0x61 594 #define PMC6_BUS_HIT_DRV 0x7a 595 #define PMC6_BUS_HITM_DRDV 0x7b 596 #define PMC6_BUS_SNOOP_STALL 0x7e 597 598 /* Floating Point Unit */ 599 #define PMC6_FLOPS 0xc1 600 #define PMC6_FP_COMP_OPS_EXE 0x10 601 #define PMC6_FP_ASSIST 0x11 602 #define PMC6_MUL 0x12 603 #define PMC6_DIV 0x12 604 #define PMC6_CYCLES_DIV_BUSY 0x14 605 606 /* Memory Ordering */ 607 #define PMC6_LD_BLOCKS 0x03 608 #define PMC6_SB_DRAINS 0x04 609 #define PMC6_MISALIGN_MEM_REF 0x05 610 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 611 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 612 613 /* Instruction Decoding and Retirement */ 614 #define PMC6_INST_RETIRED 0xc0 615 #define PMC6_UOPS_RETIRED 0xc2 616 #define PMC6_INST_DECODED 0xd0 617 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 618 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 619 620 /* Interrupts */ 621 #define PMC6_HW_INT_RX 0xc8 622 #define PMC6_CYCLES_INT_MASKED 0xc6 623 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 624 625 /* Branches */ 626 #define PMC6_BR_INST_RETIRED 0xc4 627 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 628 #define PMC6_BR_TAKEN_RETIRED 0xc9 629 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 630 #define PMC6_BR_INST_DECODED 0xe0 631 #define PMC6_BTB_MISSES 0xe2 632 #define PMC6_BR_BOGUS 0xe4 633 #define PMC6_BACLEARS 0xe6 634 635 /* Stalls */ 636 #define PMC6_RESOURCE_STALLS 0xa2 637 #define PMC6_PARTIAL_RAT_STALLS 0xd2 638 639 /* Segment Register Loads */ 640 #define PMC6_SEGMENT_REG_LOADS 0x06 641 642 /* Clocks */ 643 #define PMC6_CPU_CLK_UNHALTED 0x79 644 645 /* MMX Unit */ 646 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 647 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 648 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 649 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 650 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 651 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 652 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 653 654 /* Segment Register Renaming */ 655 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 656 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 657 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 658 659 /* VIA C3 crypto featureset: for i386_has_xcrypt */ 660 #define C3_HAS_AES 1 /* cpu has AES */ 661 #define C3_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 662 #define C3_HAS_MM 4 /* cpu has RSA instructions */ 663 #define C3_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 664 665 /* Centaur Extended Feature flags */ 666 #define C3_CPUID_HAS_RNG 0x000004 667 #define C3_CPUID_DO_RNG 0x000008 668 #define C3_CPUID_HAS_ACE 0x000040 669 #define C3_CPUID_DO_ACE 0x000080 670 #define C3_CPUID_HAS_ACE2 0x000100 671 #define C3_CPUID_DO_ACE2 0x000200 672 #define C3_CPUID_HAS_PHE 0x000400 673 #define C3_CPUID_DO_PHE 0x000800 674 #define C3_CPUID_HAS_PMM 0x001000 675 #define C3_CPUID_DO_PMM 0x002000 676 677 /* VIA C3 xcrypt-* instruction context control options */ 678 #define C3_CRYPT_CWLO_ROUND_M 0x0000000f 679 #define C3_CRYPT_CWLO_ALG_M 0x00000070 680 #define C3_CRYPT_CWLO_ALG_AES 0x00000000 681 #define C3_CRYPT_CWLO_KEYGEN_M 0x00000080 682 #define C3_CRYPT_CWLO_KEYGEN_HW 0x00000000 683 #define C3_CRYPT_CWLO_KEYGEN_SW 0x00000080 684 #define C3_CRYPT_CWLO_NORMAL 0x00000000 685 #define C3_CRYPT_CWLO_INTERMEDIATE 0x00000100 686 #define C3_CRYPT_CWLO_ENCRYPT 0x00000000 687 #define C3_CRYPT_CWLO_DECRYPT 0x00000200 688 #define C3_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 689 #define C3_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 690 #define C3_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 691