xref: /openbsd-src/sys/arch/i386/include/intr.h (revision b2ea75c1b17e1a9a339660e7ed45cd24946b230e)
1 /*	$OpenBSD: intr.h,v 1.7 2001/06/24 17:05:36 miod Exp $	*/
2 /*	$NetBSD: intr.h,v 1.5 1996/05/13 06:11:28 mycroft Exp $	*/
3 
4 /*
5  * Copyright (c) 1996 Charles M. Hannum.  All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *	This product includes software developed by Charles M. Hannum.
18  * 4. The name of the author may not be used to endorse or promote products
19  *    derived from this software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #ifndef _I386_INTR_H_
34 #define _I386_INTR_H_
35 
36 /* Interrupt priority `levels'; not mutually exclusive. */
37 #define	IPL_NONE	0	/* nothing */
38 #define	IPL_BIO		1	/* block I/O */
39 #define	IPL_NET		2	/* network */
40 #define	IPL_TTY		3	/* terminal */
41 #define	IPL_IMP		4	/* memory allocation */
42 #define	IPL_AUDIO	5	/* audio */
43 #define	IPL_CLOCK	6	/* clock */
44 #define	IPL_HIGH	7	/* everything */
45 
46 #ifndef _LOCORE
47 int imask[IPL_HIGH+1];
48 #endif
49 
50 /* Interrupt sharing types. */
51 #define	IST_NONE	0	/* none */
52 #define	IST_PULSE	1	/* pulsed */
53 #define	IST_EDGE	2	/* edge-triggered */
54 #define	IST_LEVEL	3	/* level-triggered */
55 
56 /* Soft interrupt masks. */
57 #define	SIR_CLOCK	31
58 #define	SIR_CLOCKMASK	((1 << SIR_CLOCK))
59 #define	SIR_NET		30
60 #define	SIR_NETMASK	((1 << SIR_NET) | SIR_CLOCKMASK)
61 #define	SIR_TTY		29
62 #define	SIR_TTYMASK	((1 << SIR_TTY) | SIR_CLOCKMASK)
63 #define	SIR_ALLMASK	(SIR_CLOCKMASK | SIR_NETMASK | SIR_TTYMASK)
64 
65 #ifndef _LOCORE
66 
67 volatile int cpl, ipending, astpending;
68 
69 extern void Xspllower __P((void));
70 
71 static __inline int splraise __P((int));
72 static __inline int spllower __P((int));
73 static __inline void splx __P((int));
74 static __inline void softintr __P((int));
75 
76 /*
77  * Add a mask to cpl, and return the old value of cpl.
78  */
79 static __inline int
80 splraise(ncpl)
81 	register int ncpl;
82 {
83 	register int ocpl = cpl;
84 
85 	cpl = ocpl | ncpl;
86 	return (ocpl);
87 }
88 
89 /*
90  * Restore a value to cpl (unmasking interrupts).  If any unmasked
91  * interrupts are pending, call Xspllower() to process them.
92  */
93 static __inline void
94 splx(ncpl)
95 	register int ncpl;
96 {
97 
98 	cpl = ncpl;
99 	if (ipending & ~ncpl)
100 		Xspllower();
101 }
102 
103 /*
104  * Same as splx(), but we return the old value of spl, for the
105  * benefit of some splsoftclock() callers.
106  */
107 static __inline int
108 spllower(ncpl)
109 	register int ncpl;
110 {
111 	register int ocpl = cpl;
112 
113 	cpl = ncpl;
114 	if (ipending & ~ncpl)
115 		Xspllower();
116 	return (ocpl);
117 }
118 
119 /*
120  * Hardware interrupt masks
121  */
122 #define	splbio()	splraise(imask[IPL_BIO])
123 #define	splnet()	splraise(imask[IPL_NET])
124 #define	spltty()	splraise(imask[IPL_TTY])
125 #define	splaudio()	splraise(imask[IPL_AUDIO])
126 #define	splclock()	splraise(imask[IPL_CLOCK])
127 #define	splstatclock()	splhigh()
128 
129 /*
130  * Software interrupt masks
131  *
132  * NOTE: spllowersoftclock() is used by hardclock() to lower the priority from
133  * clock to softclock before it calls softclock().
134  */
135 #define	spllowersoftclock()	spllower(SIR_CLOCKMASK)
136 #define	splsoftclock()		splraise(SIR_CLOCKMASK)
137 #define	splsoftnet()		splraise(SIR_NETMASK)
138 #define	splsofttty()		splraise(SIR_TTYMASK)
139 
140 /*
141  * Miscellaneous
142  */
143 #define	splimp()	splraise(imask[IPL_IMP])
144 #define	splvm()		splraise(imask[IPL_IMP])
145 #define	splhigh()	splraise(imask[IPL_HIGH])
146 #define	spl0()		spllower(0)
147 
148 /*
149  * Software interrupt registration
150  *
151  * We hand-code this to ensure that it's atomic.
152  */
153 static __inline void
154 softintr(mask)
155 	register int mask;
156 {
157 
158 	__asm __volatile("orl %0,_ipending" : : "ir" (mask));
159 }
160 
161 #define	setsoftast()	(astpending = 1)
162 #define	setsoftclock()	softintr(1 << SIR_CLOCK)
163 #define	setsoftnet()	softintr(1 << SIR_NET)
164 #define	setsofttty()	softintr(1 << SIR_TTY)
165 
166 #endif /* !_LOCORE */
167 
168 #endif /* !_I386_INTR_H_ */
169