1 /* $OpenBSD: pdc.h,v 1.15 2000/12/06 17:18:57 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 1990 mt Xinu, Inc. All rights reserved. 5 * Copyright (c) 1990,1991,1992,1994 University of Utah. All rights reserved. 6 * 7 * Permission to use, copy, modify and distribute this software is hereby 8 * granted provided that (1) source code retains these copyright, permission, 9 * and disclaimer notices, and (2) redistributions including binaries 10 * reproduce the notices in supporting documentation, and (3) all advertising 11 * materials mentioning features or use of this software display the following 12 * acknowledgement: ``This product includes software developed by the 13 * Computer Systems Laboratory at the University of Utah.'' 14 * 15 * Copyright (c) 1990 mt Xinu, Inc. 16 * This file may be freely distributed in any form as long as 17 * this copyright notice is included. 18 * MTXINU, THE UNIVERSITY OF UTAH, AND CSL PROVIDE THIS SOFTWARE ``AS 19 * IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, 20 * WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND 21 * FITNESS FOR A PARTICULAR PURPOSE. 22 * 23 * CSL requests users of this software to return to csl-dist@cs.utah.edu any 24 * improvements that they make and grant CSL redistribution rights. 25 * 26 * Utah $Hdr: pdc.h 1.12 94/12/14$ 27 */ 28 29 #ifndef _MACHINE_PDC_H_ 30 #define _MACHINE_PDC_H_ 31 32 /* 33 * Definitions for interaction with "Processor Dependent Code", 34 * which is a set of ROM routines used to provide information to the OS. 35 * Also includes definitions for the layout of "Page Zero" memory when 36 * boot code is invoked. 37 * 38 * Glossary: 39 * PDC: Processor Dependent Code (ROM or copy of ROM). 40 * IODC: I/O Dependent Code (module-type dependent code). 41 * IPL: Boot program (loaded into memory from boot device). 42 * HPA: Hard Physical Address (hardwired address). 43 * SPA: Soft Physical Address (reconfigurable address). 44 * 45 * 46 * 47 * 48 * Definitions for talking to IODC (I/O Dependent Code). 49 * 50 * The PDC is used to load I/O Dependent Code from a particular module. 51 * I/O Dependent Code is module-type dependent software which provides 52 * a uniform way to identify, initialize, and access a module (and in 53 * some cases, their devices). 54 */ 55 56 /* 57 * Our Initial Memory Module is laid out as follows. 58 * 59 * 0x000 +--------------------+ 60 * | Page Zero (iomod.h)| 61 * 0x800 +--------------------+ 62 * | | 63 * | | 64 * | PDC | 65 * | | 66 * | | 67 * MEM_FREE +--------------------+ 68 * | | 69 * | Console IODC | 70 * | | 71 * MEM_FREE+16k +--------------------+ 72 * | | 73 * | Boot Device IODC | 74 * | | 75 * IPL_START +--------------------+ 76 * | | 77 * | IPL Code or Kernel | 78 * | | 79 * +--------------------+ 80 * 81 * Restrictions: 82 * MEM_FREE (pagezero.mem_free) can be no greater than 32K. 83 * The PDC may use up to MEM_FREE + 32K (for Console & Boot IODC). 84 * IPL_START must be less than or equal to 64K. 85 * 86 * The IPL (boot) Code is immediately relocated to RELOC (check 87 * "../stand/Makefile") to make way for the Kernel. 88 */ 89 90 #define IODC_MAXSIZE (16 * 1024) /* maximum size of IODC */ 91 #define IODC_MINIOSIZ 64 /* minimum buffer size for IODC call */ 92 #define IODC_MAXIOSIZ (64 * 1024) /* maximum buffer size for IODC call */ 93 94 #define PDC_ALIGNMENT __attribute__ ((__aligned__(64))) 95 96 /* 97 * The PDC Entry Points and their arguments... 98 */ 99 100 #define PDC_POW_FAIL 1 /* prepare for power failure */ 101 #define PDC_POW_FAIL_DFLT 0 102 103 #define PDC_CHASSIS 2 /* update chassis display (see below) */ 104 #define PDC_CHASSIS_DISP 0 /* update display */ 105 #define PDC_CHASSIS_WARN 1 /* return warnings */ 106 #define PDC_CHASSIS_ALL 2 /* update display & return warnings */ 107 108 #define PDC_PIM 3 /* access Processor Internal Memory */ 109 #define PDC_PIM_HPMC 0 /* read High Pri Mach Chk data */ 110 #define PDC_PIM_SIZE 1 /* return size */ 111 #define PDC_PIM_LPMC 2 /* read Low Pri Mach Chk data */ 112 #define PDC_PIM_SBD 3 /* read soft boot data */ 113 #define PDC_PIM_TOC 4 /* read TOC data (used to use HPMC) */ 114 115 #define PDC_MODEL 4 /* processor model number info */ 116 #define PDC_MODEL_INFO 0 /* processor model number info */ 117 #define PDC_MODEL_BOOTID 1 /* set BOOT_ID of processor */ 118 #define PDC_MODEL_COMP 2 /* return component version numbers */ 119 #define PDC_MODEL_MODEL 3 /* return system model information */ 120 #define PDC_MODEL_ENSPEC 4 /* enable product-specific instrs */ 121 #define PDC_MODEL_DISPEC 5 /* disable product-specific instrs */ 122 #define PDC_MODEL_CPUID 6 /* return CPU versions */ 123 #define PDC_MODEL_CPBALITIES 7 /* return capabilites */ 124 #define PDC_MODEL_GETBOOTSTOPTS 8 /* return boot test options */ 125 #define PDC_MODEL_SETBOOTSTOPTS 9 /* set boot test options */ 126 127 #define PDC_CACHE 5 /* return cache and TLB params */ 128 #define PDC_CACHE_DFLT 0 /* return parameters */ 129 #define PDC_CACHE_SETCS 1 /* set coherence state */ 130 #define PDC_CACHE_GETSPIDB 2 /* get space-id bits */ 131 132 #define PDC_HPA 6 /* return HPA of processor */ 133 #define PDC_HPA_DFLT 0 134 #define PDC_HPA_MODULES 1 135 136 #define PDC_COPROC 7 /* return co-processor configuration */ 137 #define PDC_COPROC_DFLT 0 138 139 #define PDC_IODC 8 /* talk to IODC */ 140 #define PDC_IODC_READ 0 /* read IODC entry point */ 141 #define IODC_DATA 0 /* get first 16 bytes from mod IODC */ 142 #define IODC_INIT 3 /* initialize (see options below) */ 143 #define IODC_INIT_FIRST 2 /* find first device on module */ 144 #define IODC_INIT_NEXT 3 /* find subsequent devices on module */ 145 #define IODC_INIT_ALL 4 /* initialize module and device */ 146 #define IODC_INIT_DEV 5 /* initialize device */ 147 #define IODC_INIT_MOD 6 /* initialize module */ 148 #define IODC_INIT_MSG 9 /* return error message(s) */ 149 #define IODC_INIT_STR 20 /* find device w/ spec in string */ 150 #define IODC_IO 4 /* perform I/O (see options below) */ 151 #define IODC_IO_READ 0 /* read from boot device */ 152 #define IODC_IO_WRITE 1 /* write to boot device */ 153 #define IODC_IO_CONSIN 2 /* read from console */ 154 #define IODC_IO_CONSOUT 3 /* write to conosle */ 155 #define IODC_IO_CLOSE 4 /* close device */ 156 #define IODC_IO_MSG 9 /* return error message(s) */ 157 #define IODC_SPA 5 /* get extended SPA information */ 158 #define IODC_SPA_DFLT 0 /* return SPA information */ 159 #define IODC_TEST 8 /* perform self tests */ 160 #define IODC_TEST_INFO 0 /* return test information */ 161 #define IODC_TEST_STEP 1 /* execute a particular test */ 162 #define IODC_TEST_TEST 2 /* describe a test section */ 163 #define IODC_TEST_MSG 9 /* return error message(s) */ 164 #define PDC_IODC_NINIT 2 /* non-destructive init */ 165 #define PDC_IODC_DINIT 3 /* destructive init */ 166 #define PDC_IODC_MEMERR 4 /* check for memory errors */ 167 #define PDC_IODC_IMEMMASTER 5 /* interlieved memory master ID */ 168 169 #define PDC_TOD 9 /* access time-of-day clock */ 170 #define PDC_TOD_READ 0 /* read TOD clock */ 171 #define PDC_TOD_WRITE 1 /* write TOD clock */ 172 #define PDC_TOD_ITIMER 2 /* calibrate Interval Timer (CR16) */ 173 174 #define PDC_STABLE 10 /* access Stable Storage (SS) */ 175 #define PDC_STABLE_READ 0 /* read SS */ 176 #define PDC_STABLE_WRITE 1 /* write SS */ 177 #define PDC_STABLE_SIZE 2 /* return size of SS */ 178 #define PDC_STABLE_VRFY 3 /* verify contents of SS */ 179 #define PDC_STABLE_INIT 4 /* initialize SS */ 180 181 #define PDC_NVM 11 /* access Non-Volatile Memory (NVM) */ 182 #define PDC_NVM_READ 0 /* read NVM */ 183 #define PDC_NVM_WRITE 1 /* write NVM */ 184 #define PDC_NVM_SIZE 2 /* return size of NVM */ 185 #define PDC_NVM_VRFY 3 /* verify contents of NVM */ 186 #define PDC_NVM_INIT 4 /* initialize NVM */ 187 188 #define PDC_ADD_VALID 12 /* check address for validity */ 189 #define PDC_ADD_VALID_DFLT 0 190 191 #define PDC_BUS_BAD 13 /* verify Error Detection Circuitry (EDC) */ 192 #define PDC_BUS_BAD_DLFT 0 193 194 #define PDC_DEBUG 14 /* return address of PDC debugger */ 195 #define PDC_DEBUG_DFLT 0 196 197 #define PDC_INSTR 15 /* return instr that invokes PDCE_CHECK */ 198 #define PDC_INSTR_DFLT 0 199 200 #define PDC_PROC 16 /* stop currently executing processor */ 201 #define PDC_PROC_DFLT 0 202 203 #define PDC_CONF 17 /* (de)configure a module */ 204 #define PDC_CONF_DECONF 0 /* deconfigure module */ 205 #define PDC_CONF_RECONF 1 /* reconfigure module */ 206 #define PDC_CONF_INFO 2 /* get config informaion */ 207 208 #define PDC_BLOCK_TLB 18 /* Manage Block TLB entries (BTLB) */ 209 #define PDC_BTLB_DEFAULT 0 /* Return BTLB configuration info */ 210 #define PDC_BTLB_INSERT 1 /* Insert a BTLB entry */ 211 #define PDC_BTLB_PURGE 2 /* Purge a BTLB entry */ 212 #define PDC_BTLB_PURGE_ALL 3 /* Purge all BTLB entries */ 213 214 #define PDC_TLB 19 /* Manage Hardware TLB handling */ 215 #define PDC_TLB_INFO 0 /* Return HW-TLB configuration info */ 216 #define PDC_TLB_CONFIG 1 /* Set HW-TLB pdir base and size */ 217 218 #define PDC_TLB_CURRPDE 1 /* cr28 points to current pde on miss */ 219 #define PDC_TLB_RESERVD 3 /* reserved */ 220 #define PDC_TLB_NEXTPDE 5 /* cr28 points to next pde on miss */ 221 #define PDC_TLB_WORD3 7 /* cr28 is word 3 of 16 byte pde */ 222 223 #define PDC_PSW 21 /* manage default values of configurable psw bits */ 224 #define PDC_PSW_GETMASK 0 /* get mask */ 225 #define PDC_PSW_DEFAULTS 1 /* get default bits values */ 226 #define PDC_PSW_SETDEFAULTS 2 /* set default bits values */ 227 228 #define PDC_SOFT_POWER 23 /* support for soft power switch */ 229 #define PDC_SOFT_POWER_INFO 0 /* get info about soft power switch */ 230 #define PDC_SOFT_POWER_ENABLE 1 /* enable/disable soft power switch */ 231 232 #define PDC_PAT_IO 71 /* online services for IO modules */ 233 #define PDC_PAT_IO_GET_PCI_RTSZ 15 234 #define PDC_PAT_IO_GET_PCI_RT 16 235 236 #define PDC_MEMMAP 128 /* hp700: return page information */ 237 #define PDC_MEMMAP_HPA 0 /* map module # to HPA */ 238 239 #define PDC_EEPROM 129 /* Hversion dependent */ 240 #define PDC_EEPROM_READ_WORD 0 241 #define PDC_EEPROM_WRITE_WORD 1 242 #define PDC_EEPROM_READ_BYTE 2 243 #define PDC_EEPROM_WRITE_BYTE 3 244 245 #define PDC_LAN_STATION_ID 138 /* Hversion dependent mechanism for */ 246 #define PDC_LAN_STATION_ID_READ 0 /* getting the lan station address */ 247 248 #define PDC_PCI_INDEX 147 /* PCI rt access */ 249 #define PDC_PCI_GET_INT_TBL_SZ 13 250 #define PDC_PCI_GET_INT_TBL 14 251 252 #define PDC_ERR_OK 0 /* operation complete */ 253 #define PDC_ERR_WARNING 3 /* OK, but warning */ 254 #define PDC_ERR_NOPROC -1 /* no such procedure */ 255 #define PDC_ERR_NOPT -2 /* no such option */ 256 #define PDC_ERR_COMPL -3 /* unable to complete w/o error */ 257 #define PDC_ERR_EOD -9 /* end of device list */ 258 #define PDC_ERR_INVAL -10 /* invalid argument */ 259 #define PDC_ERR_PFAIL -12 /* aborted by powerfail */ 260 261 #if !defined(_LOCORE) 262 263 struct iomod; 264 265 typedef int (*pdcio_t) __P((int, int, ...)); 266 typedef int (*iodcio_t) __P((struct iomod *, int, ...)); 267 268 /* 269 * Commonly used PDC calls and the structures they return. 270 */ 271 272 struct pdc_pim { /* PDC_PIM */ 273 u_int count; /* actual (HPMC, LPMC) or total (SIZE) count */ 274 u_int archsize; /* size of architected regions (see "pim.h") */ 275 u_int filler[30]; 276 }; 277 278 struct pdc_model { /* PDC_MODEL */ 279 u_int hvers; /* hardware version */ 280 u_int rev : 4; /* zero for all native processors */ 281 u_int model : 20; /* 4 for all native processors */ 282 u_int sh : 1; /* shadow registers are present */ 283 u_int reserved : 2; /* reserved */ 284 u_int mc : 1; /* module category (A - 0, B - 1) */ 285 u_int reserved1 : 2; /* reserved */ 286 u_int pa_lvl : 2; /* PA-RISC level */ 287 u_int hw_id; /* unique processor hardware identifier */ 288 u_int boot_id; /* same as hw_id */ 289 u_int sw_id; /* software security and licensing */ 290 u_int sw_cap; /* OS capabilities of processor */ 291 u_int arch_rev; /* architecture revision */ 292 u_int pot_key; /* potential key */ 293 u_int curr_key; /* current key */ 294 int filler1; 295 u_int filler2[22]; 296 }; 297 298 struct pdc_cpuid { /* PDC_MODEL, PDC_CPUID */ 299 u_int reserved : 20; 300 u_int version : 7; /* CPU version */ 301 u_int revision : 5; /* CPU revision */ 302 u_int filler[31]; 303 }; 304 305 struct cache_cf { /* PDC_CACHE (for "struct pdc_cache") */ 306 u_int cc_resv0: 4, 307 cc_block: 4, /* used to determine most efficient stride */ 308 cc_line : 3, /* max data written by store (16-byte mults) */ 309 cc_resv1: 2, /* (reserved) */ 310 cc_wt : 1, /* D-cache: write-to = 0, write-through = 1 */ 311 cc_sh : 2, /* separate I and D = 0, shared I and D = 1 */ 312 cc_cst : 3, /* D-cache: incoherent = 0, coherent = 1 */ 313 cc_resv2: 5, /* (reserved) */ 314 cc_assoc: 8; /* D-cache: associativity of cache */ 315 }; 316 317 struct tlb_cf { /* PDC_CACHE (for "struct pdc_cache") */ 318 u_int tc_resv1:12, /* (reserved) */ 319 tc_sh : 2, /* separate I and D = 0, shared I and D = 1 */ 320 tc_hvers: 1, /* H-VERSION dependent */ 321 tc_page : 1, /* 2K page size = 0, 4k page size = 1 */ 322 tc_cst : 3, /* incoherent = 0, coherent = 1 */ 323 tc_resv2: 5, /* (reserved) */ 324 tc_assoc: 8; /* associativity of TLB */ 325 }; 326 327 struct pdc_cache { /* PDC_CACHE */ 328 /* Instruction cache */ 329 u_int ic_size; /* size of I-cache (in bytes) */ 330 struct cache_cf ic_conf;/* cache configuration (see above) */ 331 u_int ic_base; /* start addr of I-cache (for FICE flush) */ 332 u_int ic_stride; /* addr incr per i_count iteration (flush) */ 333 u_int ic_count; /* number of i_loop iterations (flush) */ 334 u_int ic_loop; /* number of FICE's per addr stride (flush) */ 335 /* Data cache */ 336 u_int dc_size; /* size of D-cache (in bytes) */ 337 struct cache_cf dc_conf;/* cache configuration (see above) */ 338 u_int dc_base; /* start addr of D-cache (for FDCE flush) */ 339 u_int dc_stride; /* addr incr per d_count iteration (flush) */ 340 u_int dc_count; /* number of d_loop iterations (flush) */ 341 u_int dc_loop; /* number of FDCE's per addr stride (flush) */ 342 /* Instruction TLB */ 343 u_int it_size; /* number of entries in I-TLB */ 344 struct tlb_cf it_conf; /* I-TLB configuration (see above) */ 345 u_int it_sp_base; /* start space of I-TLB (for PITLBE flush) */ 346 u_int it_sp_stride; /* space incr per sp_count iteration (flush) */ 347 u_int it_sp_count; /* number of off_count iterations (flush) */ 348 u_int it_off_base; /* start offset of I-TLB (for PITLBE flush) */ 349 u_int it_off_stride; /* offset incr per off_count iteration (flush)*/ 350 u_int it_off_count; /* number of it_loop iterations/space (flush) */ 351 u_int it_loop; /* number of PITLBE's per off_stride (flush) */ 352 /* Data TLB */ 353 u_int dt_size; /* number of entries in D-TLB */ 354 struct tlb_cf dt_conf; /* D-TLB configuration (see above) */ 355 u_int dt_sp_base; /* start space of D-TLB (for PDTLBE flush) */ 356 u_int dt_sp_stride; /* space incr per sp_count iteration (flush) */ 357 u_int dt_sp_count; /* number of off_count iterations (flush) */ 358 u_int dt_off_base; /* start offset of D-TLB (for PDTLBE flush) */ 359 u_int dt_off_stride; /* offset incr per off_count iteration (flush)*/ 360 u_int dt_off_count; /* number of dt_loop iterations/space (flush) */ 361 u_int dt_loop; /* number of PDTLBE's per off_stride (flush) */ 362 u_int filler[2]; 363 }; 364 365 struct pdc_spidb { /* PDC_CACHE, PDC_CACHE_GETSPIDB */ 366 u_int spidR1 : 4; 367 u_int spidbits : 12; 368 u_int spidR2 : 16; 369 u_int filler[31]; 370 }; 371 372 struct pdc_cst { 373 u_int cstR1 : 16; 374 u_int cst : 3; 375 u_int cstR2 : 13; 376 }; 377 378 struct pdc_coherence { /* PDC_CACHE, PDC_CACHE_SETCS */ 379 struct pdc_cst ia; 380 #define ia_cst ia.cst 381 struct pdc_cst da; 382 #define da_cst da.cst 383 struct pdc_cst ita; 384 #define ita_cst ita.cst 385 struct pdc_cst dta; 386 #define dta_cst dta.cst 387 u_int filler[28]; 388 }; 389 390 struct pdc_hpa { /* PDC_HPA */ 391 hppa_hpa_t hpa; /* HPA of processor */ 392 int filler1; 393 u_int filler2[30]; 394 }; 395 396 struct pdc_coproc { /* PDC_COPROC */ 397 u_int ccr_enable; /* same format as CCR (CR 10) */ 398 u_int ccr_present; /* which co-proc's are present (bitset) */ 399 u_int pad[15]; 400 u_int fpu_model; 401 u_int fpu_revision; 402 u_int filler2[13]; 403 }; 404 405 struct pdc_tod { /* PDC_TOD, PDC_TOD_READ */ 406 u_int sec; /* elapsed time since 00:00:00 GMT, 1/1/70 */ 407 u_int usec; /* accurate to microseconds */ 408 u_int filler2[30]; 409 }; 410 411 struct pdc_instr { /* PDC_INSTR */ 412 u_int instr; /* instruction that invokes PDC mchk entry pt */ 413 int filler1; 414 u_int filler2[30]; 415 }; 416 417 struct pdc_iodc_read { /* PDC_IODC, PDC_IODC_READ */ 418 int size; /* number of bytes in selected entry point */ 419 int filler1; 420 u_int filler2[30]; 421 }; 422 423 struct pdc_iodc_minit { /* PDC_IODC, PDC_IODC_NINIT or PDC_IODC_DINIT */ 424 u_int stat; /* HPA.io_status style error returns */ 425 u_int max_spa; /* size of SPA (in bytes) > max_mem+map_mem */ 426 u_int max_mem; /* size of "implemented" memory (in bytes) */ 427 u_int map_mem; /* size of "mapable-only" memory (in bytes) */ 428 u_int filler[28]; 429 }; 430 431 struct btlb_info { /* for "struct pdc_btlb" (PDC_BTLB) */ 432 u_int resv0: 8, /* (reserved) */ 433 num_i: 8, /* Number of instruction slots */ 434 num_d: 8, /* Number of data slots */ 435 num_c: 8; /* Number of combined slots */ 436 }; 437 438 struct pdc_btlb { /* PDC_BLOCK_TLB */ 439 u_int min_size; /* Min size in pages */ 440 u_int max_size; /* Max size in pages */ 441 struct btlb_info finfo; /* Fixed range info */ 442 struct btlb_info vinfo; /* Variable range info */ 443 u_int filler[28]; 444 }; 445 446 struct pdc_hwtlb { /* PDC_TLB */ 447 u_int min_size; /* What do these mean? */ 448 u_int max_size; 449 u_int filler[30]; 450 }; 451 452 struct pdc_pat_io_num { /* PDC_PAT_IO */ 453 u_int num; 454 u_int filler[31]; 455 }; 456 457 struct pdc_memmap { /* PDC_MEMMAP */ 458 u_int hpa; /* HPA for module */ 459 u_int morepages; /* additional IO pages */ 460 u_int filler[30]; 461 }; 462 463 struct pdc_lan_station_id { /* PDC_LAN_STATION_ID */ 464 u_int8_t addr[6]; 465 u_int8_t filler1[2]; 466 u_int filler2[30]; 467 }; 468 469 /* 470 * The PDC_CHASSIS is a strange bird. The format for updating the display 471 * is as follows: 472 * 473 * 0 11 12 14 15 16 19 20 23 24 27 28 31 474 * +-------+----------+-------+--------+--------+--------+--------+ 475 * | R | OS State | Blank | Hex1 | Hex2 | Hex3 | Hex4 | 476 * +-------+----------+-------+--------+--------+--------+--------+ 477 * 478 * Unfortunately, someone forgot to tell the hardware designers that 479 * there was supposed to be a hex display somewhere. The result is, 480 * you can only toggle 5 LED's and the fault light. 481 * 482 * Interesting values for Hex1-Hex4 and the resulting LED displays: 483 * 484 * FnFF CnFF: 485 * 0 - - - - - Counts in binary from 0x0 - 0xF 486 * 2 o - - - - for corresponding values of `n'. 487 * 4 o o - - - 488 * 6 o o o - - 489 * 8 o o o o - 490 * A o o o o o 491 * 492 * If the "Blank" bit is set, the display should be made blank. 493 * The values for "OS State" are defined below. 494 */ 495 496 #define PDC_CHASSIS_BAR 0xF0FF /* create a bar graph with LEDs */ 497 #define PDC_CHASSIS_CNT 0xC0FF /* count with LEDs */ 498 499 #define PDC_OSTAT(os) (((os) & 0x7) << 17) 500 #define PDC_OSTAT_OFF 0x0 /* all off */ 501 #define PDC_OSTAT_FAULT 0x1 /* the red LED of death */ 502 #define PDC_OSTAT_TEST 0x2 /* self test */ 503 #define PDC_OSTAT_BOOT 0x3 /* boot program running */ 504 #define PDC_OSTAT_SHUT 0x4 /* shutdown in progress */ 505 #define PDC_OSTAT_WARN 0x5 /* battery dying, etc */ 506 #define PDC_OSTAT_RUN 0x6 /* OS running */ 507 #define PDC_OSTAT_ON 0x7 /* all on */ 508 509 /* 510 * Device path specifications used by PDC. 511 */ 512 struct device_path { 513 u_char dp_flags; /* see bit definitions below */ 514 char dp_bc[6]; /* Bus Converter routing info to a specific */ 515 /* I/O adaptor (< 0 means none, > 63 resvd) */ 516 u_char dp_mod; /* fixed field of specified module */ 517 int dp_layers[6]; /* device-specific info (ctlr #, unit # ...) */ 518 }; 519 520 /* dp_flags */ 521 #define PF_AUTOBOOT 0x80 /* These two are PDC flags for how to locate */ 522 #define PF_AUTOSEARCH 0x40 /* the "boot device" */ 523 #define PF_TIMER 0x0f /* power of 2 # secs "boot timer" (0 == dflt) */ 524 525 /* 526 * A processors Stable Storage is accessed through the PDC. There are 527 * at least 96 bytes of stable storage (the device path information may 528 * or may not exist). However, as far as I know, processors provide at 529 * least 192 bytes of stable storage. 530 */ 531 struct stable_storage { 532 struct device_path ss_pri_boot; /* (see above) */ 533 char ss_filenames[32]; 534 u_short ss_os_version; /* 0 == none, 1 == HP-UX, 2 == MPE-XL */ 535 char ss_os[22]; /* OS-dependant information */ 536 char ss_pdc[7]; /* reserved */ 537 char ss_fast_size; /* how much memory to test. 0xf == all, or */ 538 /* else it's (256KB << ss_fast_size) */ 539 struct device_path ss_console; 540 struct device_path ss_alt_boot; 541 struct device_path ss_keyboard; 542 }; 543 544 /* 545 * Recoverable error indications provided to boot code by the PDC. 546 * Any non-zero value indicates error. 547 */ 548 struct boot_err { 549 u_int be_resv : 10, /* (reserved) */ 550 be_fixed : 6, /* module that produced error */ 551 be_chas : 16; /* error code (interpret as 4 hex digits) */ 552 }; 553 554 #define HPBE_HBOOT_CORRECTABLE 0 /* hard-boot corrctable error */ 555 #define HPBE_HBOOT_UNCORRECTBL 1 /* hard-boot uncorrectable error */ 556 #define HPBE_SBOOT_CORRECTABLE 2 /* soft-boot correctable error */ 557 #define HPBE_SBOOT_UNCORRECTBL 3 /* soft-boot uncorrectable error */ 558 #define HPBE_ETEST_MODUNUSABLE 4 /* ENTRY_TEST err: module's unusable */ 559 #define HPBE_ETEST_MODDEGRADED 5 /* ENTRY_TEST err: module in degraded mode */ 560 561 562 /* 563 * The PDC uses the following structure to completely define an I/O 564 * module and the interface to its IODC. 565 */ 566 typedef 567 struct pz_device { 568 struct device_path pz_dp; 569 #define pz_flags pz_dp.dp_flags 570 #define pz_bc pz_dp.dp_bc 571 #define pz_mod pz_dp.dp_mod 572 #define pz_layers pz_dp.dp_layers 573 struct iomod *pz_hpa; /* HPA base address of device */ 574 caddr_t pz_spa; /* SPA base address (zero if no SPA exists) */ 575 iodcio_t pz_iodc_io; /* entry point of device's driver routines */ 576 short pz_resv; /* (reserved) */ 577 u_short pz_class; /* (see below) */ 578 } pz_device_t; 579 580 /* pz_class */ 581 #define PCL_NULL 0 /* illegal */ 582 #define PCL_RANDOM 1 /* random access (disk) */ 583 #define PCL_SEQU 2 /* sequential access (tape) */ 584 #define PCL_DUPLEX 7 /* full-duplex point-to-point (RS-232, Net) */ 585 #define PCL_KEYBD 8 /* half-duplex input (HIL Keyboard) */ 586 #define PCL_DISPL 9 /* half-duplex ouptput (display) */ 587 #define PCL_CLASS_MASK 0xf /* XXX class mask */ 588 #define PCL_NET_MASK 0x1000 /* mask for bootp/tftp device */ 589 590 /* 591 * The following structure defines what a particular IODC returns when 592 * given the IODC_DATA argument. 593 */ 594 struct iodc_data { 595 u_int iodc_model: 8, /* hardware model number */ 596 iodc_revision:8, /* software revision */ 597 iodc_spa_io: 1, /* 0:memory, 1:device */ 598 iodc_spa_pack:1, /* 1:packed multiplexor */ 599 iodc_spa_enb:1, /* 1:has an spa */ 600 iodc_spa_shift:5, /* power of two # bytes in SPA space */ 601 iodc_more: 1, /* iodc_data is: 0:8-byte, 1:16-byte */ 602 iodc_word: 1, /* iodc_data is: 0:byte, 1:word */ 603 iodc_pf: 1, /* 1:supports powerfail */ 604 iodc_type: 5; /* see below */ 605 u_int iodc_sv_rev: 4, /* software version revision number */ 606 iodc_sv_model:20, /* software interface model # */ 607 iodc_sv_opt: 8; /* type-specific options */ 608 u_char iodc_rev; /* revision number of IODC code */ 609 u_char iodc_dep; /* module-dependent information */ 610 u_char iodc_rsv[2]; /* reserved */ 611 u_short iodc_cksum; /* 16-bit checksum of whole IODC */ 612 u_short iodc_length; /* number of entry points in IODC */ 613 /* IODC entry points follow... */ 614 }; 615 616 extern pdcio_t pdc; 617 618 #ifdef _KERNEL 619 struct consdev; 620 621 extern int kernelmapped; 622 623 void pdc_init __P((void)); 624 int pdc_call __P((iodcio_t, int, ...)); 625 626 void pdccnprobe __P((struct consdev *)); 627 void pdccninit __P((struct consdev *)); 628 int pdccngetc __P((dev_t)); 629 void pdccnputc __P((dev_t, int)); 630 void pdccnpollc __P((dev_t, int)); 631 #endif 632 633 #endif /* !(_LOCORE) */ 634 635 #endif /* _MACHINE_PDC_H_ */ 636