1 /* $OpenBSD: intr.h,v 1.42 2015/09/13 14:58:20 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2002-2004 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _MACHINE_INTR_H_ 30 #define _MACHINE_INTR_H_ 31 32 #include <machine/psl.h> 33 34 #define CPU_NINTS 32 35 #define NIPL 17 36 37 #define IPL_NONE 0 38 #define IPL_SOFTCLOCK 1 39 #define IPL_SOFTNET 2 40 #define IPL_BIO 3 41 #define IPL_NET 4 42 #define IPL_SOFTTTY 5 43 #define IPL_TTY 6 44 #define IPL_VM 7 45 #define IPL_AUDIO 8 46 #define IPL_CLOCK 9 47 #define IPL_STATCLOCK 10 48 #define IPL_SCHED 10 49 #define IPL_HIGH 10 50 #define IPL_IPI 11 51 #define IPL_NESTED 12 /* pseudo-level for sub-tables */ 52 53 #define IPL_MPSAFE 0 /* no "mpsafe" interrupts */ 54 55 #define IST_NONE 0 56 #define IST_PULSE 1 57 #define IST_EDGE 2 58 #define IST_LEVEL 3 59 60 #ifdef MULTIPROCESSOR 61 #define HPPA_IPI_NOP 0 62 #define HPPA_IPI_HALT 1 63 #define HPPA_IPI_FPU_SAVE 2 64 #define HPPA_IPI_FPU_FLUSH 3 65 #define HPPA_NIPI 4 66 #endif 67 68 #if !defined(_LOCORE) && defined(_KERNEL) 69 70 extern volatile u_long imask[NIPL]; 71 72 #ifdef DIAGNOSTIC 73 void splassert_fail(int, int, const char *); 74 extern int splassert_ctl; 75 void splassert_check(int, const char *); 76 #define splassert(__wantipl) do { \ 77 if (splassert_ctl > 0) { \ 78 splassert_check(__wantipl, __func__); \ 79 } \ 80 } while (0) 81 #define splsoftassert(__wantipl) splassert(__wantipl) 82 #else 83 #define splassert(__wantipl) do { /* nada */ } while (0) 84 #define splsoftassert(__wantipl) do { /* nada */ } while (0) 85 #endif /* DIAGNOSTIC */ 86 87 void cpu_intr_init(void); 88 void cpu_intr(void *); 89 90 void intr_barrier(void *); 91 92 static __inline int 93 spllower(int ncpl) 94 { 95 register int ocpl asm("r28") = ncpl; 96 __asm volatile("copy %0, %%arg0\n\tbreak %1, %2" 97 : "+r" (ocpl) : "i" (HPPA_BREAK_KERNEL), "i" (HPPA_BREAK_SPLLOWER) 98 : "r26", "memory"); 99 return (ocpl); 100 } 101 102 static __inline int 103 splraise(int ncpl) 104 { 105 struct cpu_info *ci = curcpu(); 106 int ocpl = ci->ci_cpl; 107 108 if (ocpl < ncpl) 109 ci->ci_cpl = ncpl; 110 __asm volatile ("sync" : : : "memory"); 111 112 return (ocpl); 113 } 114 115 static __inline void 116 splx(int ncpl) 117 { 118 (void)spllower(ncpl); 119 } 120 121 static __inline register_t 122 hppa_intr_disable(void) 123 { 124 register_t eiem; 125 126 __asm volatile("mfctl %%cr15, %0": "=r" (eiem)); 127 __asm volatile("mtctl %r0, %cr15"); 128 129 return eiem; 130 } 131 132 static __inline void 133 hppa_intr_enable(register_t eiem) 134 { 135 __asm volatile("mtctl %0, %%cr15":: "r" (eiem)); 136 } 137 138 #define splsoftclock() splraise(IPL_SOFTCLOCK) 139 #define splsoftnet() splraise(IPL_SOFTNET) 140 #define splbio() splraise(IPL_BIO) 141 #define splnet() splraise(IPL_NET) 142 #define splsofttty() splraise(IPL_SOFTTTY) 143 #define spltty() splraise(IPL_TTY) 144 #define splvm() splraise(IPL_VM) 145 #define splaudio() splraise(IPL_AUDIO) 146 #define splclock() splraise(IPL_CLOCK) 147 #define splsched() splraise(IPL_SCHED) 148 #define splstatclock() splraise(IPL_STATCLOCK) 149 #define splhigh() splraise(IPL_HIGH) 150 #define splipi() splraise(IPL_IPI) 151 #define spl0() spllower(IPL_NONE) 152 153 #define SOFTINT_MASK ((1 << (IPL_SOFTCLOCK - 1)) | \ 154 (1 << (IPL_SOFTNET - 1)) | (1 << (IPL_SOFTTTY - 1))) 155 156 #ifdef MULTIPROCESSOR 157 void hppa_ipi_init(struct cpu_info *); 158 int hppa_ipi_send(struct cpu_info *, u_long); 159 int hppa_ipi_broadcast(u_long); 160 #endif 161 162 #define setsoftast(p) (p->p_md.md_astpending = 1) 163 164 void *softintr_establish(int, void (*)(void *), void *); 165 void softintr_disestablish(void *); 166 void softintr_schedule(void *); 167 168 #ifdef MULTIPROCESSOR 169 void hppa_ipi_init(struct cpu_info *); 170 int hppa_ipi_intr(void *arg); 171 int hppa_ipi_send(struct cpu_info *, u_long); 172 #endif 173 174 #endif /* !_LOCORE && _KERNEL */ 175 #endif /* _MACHINE_INTR_H_ */ 176