1 /* $OpenBSD: dino.c,v 1.25 2009/03/30 21:24:57 kettenis Exp $ */ 2 3 /* 4 * Copyright (c) 2003-2005 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "cardbus.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/reboot.h> 35 #include <sys/malloc.h> 36 #include <sys/extent.h> 37 38 #include <machine/iomod.h> 39 #include <machine/autoconf.h> 40 41 #include <hppa/dev/cpudevs.h> 42 43 #if NCARDBUS > 0 44 #include <dev/cardbus/rbus.h> 45 #endif 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #include <machine/pdc.h> 52 #include <dev/cons.h> 53 54 #define DINO_MEM_CHUNK 0x800000 55 #define DINO_MEM_WINDOW (2 * DINO_MEM_CHUNK) 56 57 struct dino_regs { 58 u_int32_t pad0; /* 0x000 */ 59 u_int32_t iar0; /* 0x004 rw intr addr reg 0 */ 60 u_int32_t iodc; /* 0x008 rw iodc data/addr */ 61 u_int32_t irr0; /* 0x00c r intr req reg 0 */ 62 u_int32_t iar1; /* 0x010 rw intr addr reg 1 */ 63 u_int32_t irr1; /* 0x014 r intr req reg 1 */ 64 u_int32_t imr; /* 0x018 rw intr mask reg */ 65 u_int32_t ipr; /* 0x01c rw intr pending reg */ 66 u_int32_t toc_addr; /* 0x020 rw TOC addr reg */ 67 u_int32_t icr; /* 0x024 rw intr control reg */ 68 u_int32_t ilr; /* 0x028 r intr level reg */ 69 u_int32_t pad1; /* 0x02c */ 70 u_int32_t io_command; /* 0x030 w command register */ 71 u_int32_t io_status; /* 0x034 r status register */ 72 u_int32_t io_control; /* 0x038 rw control register */ 73 u_int32_t pad2; /* 0x03c AUX registers follow */ 74 u_int32_t io_gsc_err_addr;/* 0x040 GSC error address */ 75 u_int32_t io_err_info; /* 0x044 error info register */ 76 u_int32_t io_pci_err_addr;/* 0x048 PCI error address */ 77 u_int32_t pad3[4]; /* 0x04c */ 78 u_int32_t io_fbb_en; /* 0x05c fast back2back enable reg */ 79 u_int32_t io_addr_en; /* 0x060 address enable reg */ 80 u_int32_t pci_addr; /* 0x064 PCI conf/io/mem addr reg */ 81 u_int32_t pci_conf_data; /* 0x068 PCI conf data reg */ 82 u_int32_t pci_io_data; /* 0x06c PCI io data reg */ 83 u_int32_t pci_mem_data; /* 0x070 PCI memory data reg */ 84 u_int32_t pad4[0x740/4]; /* 0x074 */ 85 u_int32_t gsc2x_config; /* 0x7b4 GSC2X config reg */ 86 u_int32_t pad5[0x48/4]; /* 0x7b8: BSRS registers follow */ 87 u_int32_t gmask; /* 0x800 GSC arbitration mask */ 88 u_int32_t pamr; /* 0x804 PCI arbitration mask */ 89 u_int32_t papr; /* 0x808 PCI arbitration priority */ 90 u_int32_t damode; /* 0x80c PCI arbitration mode */ 91 u_int32_t pcicmd; /* 0x810 PCI command register */ 92 u_int32_t pcists; /* 0x814 PCI status register */ 93 u_int32_t pad6; /* 0x818 */ 94 u_int32_t mltim; /* 0x81c PCI master latency timer */ 95 u_int32_t brdg_feat; /* 0x820 PCI bridge feature enable */ 96 u_int32_t pciror; /* 0x824 PCI read optimization reg */ 97 u_int32_t pciwor; /* 0x828 PCI write optimization reg */ 98 u_int32_t pad7; /* 0x82c */ 99 u_int32_t tltim; /* 0x830 PCI target latency reg */ 100 }; 101 102 struct dino_softc { 103 struct device sc_dv; 104 105 int sc_ver; 106 void *sc_ih; 107 u_int32_t sc_imr; 108 bus_space_tag_t sc_bt; 109 bus_space_handle_t sc_bh; 110 bus_dma_tag_t sc_dmat; 111 volatile struct dino_regs *sc_regs; 112 113 struct hppa_pci_chipset_tag sc_pc; 114 struct hppa_bus_space_tag sc_iot; 115 char sc_ioexname[20]; 116 struct extent *sc_ioex; 117 struct hppa_bus_space_tag sc_memt; 118 char sc_memexname[20]; 119 struct extent *sc_memex; 120 struct hppa_bus_dma_tag sc_dmatag; 121 122 u_int32_t io_shadow; 123 }; 124 125 int dinomatch(struct device *, void *, void *); 126 void dinoattach(struct device *, struct device *, void *); 127 int dino_intr(void *); 128 129 struct cfattach dino_ca = { 130 sizeof(struct dino_softc), dinomatch, dinoattach 131 }; 132 133 struct cfdriver dino_cd = { 134 NULL, "dino", DV_DULL 135 }; 136 137 int 138 dinomatch(parent, cfdata, aux) 139 struct device *parent; 140 void *cfdata; 141 void *aux; 142 { 143 struct confargs *ca = aux; 144 /* struct cfdata *cf = cfdata; */ 145 146 /* there will be only one */ 147 if (ca->ca_type.iodc_type != HPPA_TYPE_BRIDGE || 148 ca->ca_type.iodc_sv_model != HPPA_BRIDGE_DINO) 149 return (0); 150 151 /* do not match on the elroy family */ 152 if (ca->ca_type.iodc_model == 0x78) 153 return (0); 154 155 return (1); 156 } 157 158 void dino_attach_hook(struct device *, struct device *, 159 struct pcibus_attach_args *); 160 int dino_maxdevs(void *, int); 161 pcitag_t dino_make_tag(void *, int, int, int); 162 void dino_decompose_tag(void *, pcitag_t, int *, int *, int *); 163 pcireg_t dino_conf_read(void *, pcitag_t, int); 164 void dino_conf_write(void *, pcitag_t, int, pcireg_t); 165 int dino_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 166 const char *dino_intr_string(void *, pci_intr_handle_t); 167 void * dino_intr_establish(void *, pci_intr_handle_t, int, int (*)(void *), 168 void *, char *); 169 void dino_intr_disestablish(void *, void *); 170 int dino_iomap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 171 int dino_memmap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 172 int dino_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t, 173 bus_space_handle_t *); 174 int dino_ioalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, 175 bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 176 int dino_memalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, 177 bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 178 void dino_unmap(void *, bus_space_handle_t, bus_size_t); 179 void dino_free(void *, bus_space_handle_t, bus_size_t); 180 void dino_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int); 181 void * dino_alloc_parent(struct device *, struct pci_attach_args *, int); 182 void * dino_vaddr(void *, bus_space_handle_t); 183 u_int8_t dino_r1(void *, bus_space_handle_t, bus_size_t); 184 u_int16_t dino_r2(void *, bus_space_handle_t, bus_size_t); 185 u_int32_t dino_r4(void *, bus_space_handle_t, bus_size_t); 186 u_int64_t dino_r8(void *, bus_space_handle_t, bus_size_t); 187 void dino_w1(void *, bus_space_handle_t, bus_size_t, u_int8_t); 188 void dino_w2(void *, bus_space_handle_t, bus_size_t, u_int16_t); 189 void dino_w4(void *, bus_space_handle_t, bus_size_t, u_int32_t); 190 void dino_w8(void *, bus_space_handle_t, bus_size_t, u_int64_t); 191 void dino_rm_1(void *, bus_space_handle_t, bus_size_t, u_int8_t *, 192 bus_size_t); 193 void dino_rm_2(void *, bus_space_handle_t, bus_size_t, u_int16_t *, 194 bus_size_t); 195 void dino_rm_4(void *, bus_space_handle_t, bus_size_t, u_int32_t *, 196 bus_size_t); 197 void dino_rm_8(void *, bus_space_handle_t, bus_size_t, u_int64_t *, 198 bus_size_t); 199 void dino_wm_1(void *, bus_space_handle_t, bus_size_t, const u_int8_t *, 200 bus_size_t); 201 void dino_wm_2(void *, bus_space_handle_t, bus_size_t, const u_int16_t *, 202 bus_size_t); 203 void dino_wm_4(void *, bus_space_handle_t, bus_size_t, const u_int32_t *, 204 bus_size_t); 205 void dino_wm_8(void *, bus_space_handle_t, bus_size_t, const u_int64_t *, 206 bus_size_t); 207 void dino_sm_1(void *, bus_space_handle_t, bus_size_t, u_int8_t, bus_size_t); 208 void dino_sm_2(void *, bus_space_handle_t, bus_size_t, u_int16_t, 209 bus_size_t); 210 void dino_sm_4(void *, bus_space_handle_t, bus_size_t, u_int32_t, 211 bus_size_t); 212 void dino_sm_8(void *, bus_space_handle_t, bus_size_t, u_int64_t, 213 bus_size_t); 214 void dino_rrm_2(void *, bus_space_handle_t, bus_size_t, u_int8_t *, 215 bus_size_t); 216 void dino_rrm_4(void *, bus_space_handle_t, bus_size_t, u_int8_t *, 217 bus_size_t); 218 void dino_rrm_8(void *, bus_space_handle_t, bus_size_t, u_int8_t *, 219 bus_size_t); 220 void dino_wrm_2(void *, bus_space_handle_t, bus_size_t, const u_int8_t *, 221 bus_size_t); 222 void dino_wrm_4(void *, bus_space_handle_t, bus_size_t, const u_int8_t *, 223 bus_size_t); 224 void dino_wrm_8(void *, bus_space_handle_t, bus_size_t, const u_int8_t *, 225 bus_size_t); 226 void dino_rr_1(void *, bus_space_handle_t, bus_size_t, u_int8_t *, 227 bus_size_t); 228 void dino_rr_2(void *, bus_space_handle_t, bus_size_t, u_int16_t *, 229 bus_size_t); 230 void dino_rr_4(void *, bus_space_handle_t, bus_size_t, u_int32_t *, 231 bus_size_t); 232 void dino_rr_8(void *, bus_space_handle_t, bus_size_t, u_int64_t *, 233 bus_size_t); 234 void dino_wr_1(void *, bus_space_handle_t, bus_size_t, const u_int8_t *, 235 bus_size_t); 236 void dino_wr_2(void *, bus_space_handle_t, bus_size_t, const u_int16_t *, 237 bus_size_t); 238 void dino_wr_4(void *, bus_space_handle_t, bus_size_t, const u_int32_t *, 239 bus_size_t); 240 void dino_wr_8(void *, bus_space_handle_t, bus_size_t, const u_int64_t *, 241 bus_size_t); 242 void dino_rrr_2(void *, bus_space_handle_t, bus_size_t, u_int8_t *, 243 bus_size_t); 244 void dino_rrr_4(void *, bus_space_handle_t, bus_size_t, u_int8_t *, 245 bus_size_t); 246 void dino_rrr_8(void *, bus_space_handle_t, bus_size_t, u_int8_t *, 247 bus_size_t); 248 void dino_wrr_2(void *, bus_space_handle_t, bus_size_t, const u_int8_t *, 249 bus_size_t); 250 void dino_wrr_4(void *, bus_space_handle_t, bus_size_t, const u_int8_t *, 251 bus_size_t); 252 void dino_wrr_8(void *, bus_space_handle_t, bus_size_t, const u_int8_t *, 253 bus_size_t); 254 void dino_sr_1(void *, bus_space_handle_t, bus_size_t, u_int8_t, bus_size_t); 255 void dino_sr_2(void *, bus_space_handle_t, bus_size_t, u_int16_t, 256 bus_size_t); 257 void dino_sr_4(void *, bus_space_handle_t, bus_size_t, u_int32_t, 258 bus_size_t); 259 void dino_sr_8(void *, bus_space_handle_t, bus_size_t, u_int64_t, 260 bus_size_t); 261 void dino_cp_1(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 262 bus_size_t, bus_size_t); 263 void dino_cp_2(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 264 bus_size_t, bus_size_t); 265 void dino_cp_4(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 266 bus_size_t, bus_size_t); 267 void dino_cp_8(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 268 bus_size_t, bus_size_t); 269 int dino_dmamap_create(void *, bus_size_t, int, bus_size_t, bus_size_t, int, 270 bus_dmamap_t *); 271 void dino_dmamap_destroy(void *, bus_dmamap_t); 272 int dino_dmamap_load(void *, bus_dmamap_t, void *, bus_size_t, 273 struct proc *, int); 274 int dino_dmamap_load_mbuf(void *, bus_dmamap_t, struct mbuf *, int); 275 int dino_dmamap_load_uio(void *, bus_dmamap_t, struct uio *, int); 276 int dino_dmamap_load_raw(void *, bus_dmamap_t, bus_dma_segment_t *, int, 277 bus_size_t, int); 278 void dino_dmamap_unload(void *, bus_dmamap_t); 279 void dino_dmamap_sync(void *, bus_dmamap_t, bus_addr_t, bus_size_t, int); 280 int dino_dmamem_alloc(void *, bus_size_t, bus_size_t, bus_size_t, 281 bus_dma_segment_t *, int, int *, int); 282 void dino_dmamem_free(void *, bus_dma_segment_t *, int); 283 int dino_dmamem_map(void *, bus_dma_segment_t *, int, size_t, caddr_t *, 284 int); 285 void dino_dmamem_unmap(void *, caddr_t, size_t); 286 paddr_t dino_dmamem_mmap(void *, bus_dma_segment_t *, int, off_t, int, int); 287 int dinoprint(void *, const char *); 288 void dino_clear_pdc_mappings(void *); 289 290 void 291 dino_attach_hook(struct device *parent, struct device *self, 292 struct pcibus_attach_args *pba) 293 { 294 295 } 296 297 int 298 dino_maxdevs(void *v, int bus) 299 { 300 return (32); 301 } 302 303 pcitag_t 304 dino_make_tag(void *v, int bus, int dev, int func) 305 { 306 if (bus > 255 || dev > 31 || func > 7) 307 panic("dino_make_tag: bad request"); 308 309 return ((bus << 16) | (dev << 11) | (func << 8)); 310 } 311 312 void 313 dino_decompose_tag(void *v, pcitag_t tag, int *bus, int *dev, int *func) 314 { 315 *bus = (tag >> 16) & 0xff; 316 *dev = (tag >> 11) & 0x1f; 317 *func= (tag >> 8) & 0x07; 318 } 319 320 pcireg_t 321 dino_conf_read(void *v, pcitag_t tag, int reg) 322 { 323 struct dino_softc *sc = v; 324 volatile struct dino_regs *r = sc->sc_regs; 325 pcireg_t data; 326 u_int32_t pamr; 327 328 /* fix arbitration errata by disabling all pci devs on config read */ 329 pamr = r->pamr; 330 r->pamr = 0; 331 332 r->pci_addr = tag | reg; 333 data = r->pci_conf_data; 334 335 /* restore arbitration */ 336 r->pamr = pamr; 337 338 return (letoh32(data)); 339 } 340 341 void 342 dino_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 343 { 344 struct dino_softc *sc = v; 345 volatile struct dino_regs *r = sc->sc_regs; 346 pcireg_t data1; 347 u_int32_t pamr; 348 349 /* fix arbitration errata by disabling all pci devs on config read */ 350 pamr = r->pamr; 351 r->pamr = 0; 352 353 r->pci_addr = tag | reg; 354 r->pci_conf_data = htole32(data); 355 356 /* fix coalescing config and io writes by interleaving w/ a read */ 357 r->pci_addr = tag | PCI_ID_REG; 358 data1 = r->pci_conf_data; 359 360 /* restore arbitration */ 361 r->pamr = pamr; 362 } 363 364 int 365 dino_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 366 { 367 /* struct dino_softc *sc = v; 368 volatile struct dino_regs *r = sc->sc_regs; */ 369 pci_chipset_tag_t pc = pa->pa_pc; 370 pcitag_t tag = pa->pa_tag; 371 pcireg_t reg; 372 373 reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 374 375 if (PCI_INTERRUPT_LINE(reg) == 0xff) 376 return (1); 377 378 *ihp = PCI_INTERRUPT_LINE(reg) + 1; 379 return (0); 380 } 381 382 const char * 383 dino_intr_string(void *v, pci_intr_handle_t ih) 384 { 385 static char buf[32]; 386 387 snprintf(buf, 32, "irq %ld", ih); 388 389 return (buf); 390 } 391 392 void * 393 dino_intr_establish(void *v, pci_intr_handle_t ih, 394 int pri, int (*handler)(void *), void *arg, char *name) 395 { 396 struct dino_softc *sc = v; 397 volatile struct dino_regs *r = sc->sc_regs; 398 void *iv; 399 400 /* no mapping or bogus */ 401 if (ih <= 0 || ih > 11) 402 return (NULL); 403 404 if ((iv = cpu_intr_map(sc->sc_ih, pri, ih - 1, handler, arg, name))) { 405 if (cold) 406 sc->sc_imr |= (1 << (ih - 1)); 407 else 408 r->imr = sc->sc_imr |= (1 << (ih - 1)); 409 } 410 411 return (iv); 412 } 413 414 void 415 dino_intr_disestablish(void *v, void *cookie) 416 { 417 #if 0 418 struct dino_softc *sc = v; 419 volatile struct dino_regs *r = sc->sc_regs; 420 421 r->imr &= ~(1 << (ih - 1)); 422 423 TODO cpu_intr_unmap(sc->sc_ih, cookie); 424 #endif 425 } 426 427 int 428 dino_iomap(void *v, bus_addr_t bpa, bus_size_t size, 429 int flags, bus_space_handle_t *bshp) 430 { 431 struct dino_softc *sc = v; 432 int error; 433 434 if ((error = extent_alloc_region(sc->sc_ioex, bpa, size, EX_NOWAIT))) 435 return (error); 436 437 if (bshp) 438 *bshp = bpa; 439 440 return (0); 441 } 442 443 int 444 dino_memmap(void *v, bus_addr_t bpa, bus_size_t size, 445 int flags, bus_space_handle_t *bshp) 446 { 447 struct dino_softc *sc = v; 448 volatile struct dino_regs *r = sc->sc_regs; 449 bus_addr_t sbpa; 450 bus_space_handle_t bush; 451 u_int32_t reg; 452 int first = 1; 453 int error; 454 455 while (size != 0) { 456 sbpa = bpa & 0xff800000; 457 reg = sc->io_shadow; 458 reg |= 1 << ((bpa >> 23) & 0x1f); 459 if (reg & 0x80000001) { 460 #ifdef DEBUG 461 panic("mapping outside the mem extent range"); 462 #endif 463 return (EINVAL); 464 } 465 /* map into the upper bus space, if not yet mapped this 8M */ 466 if (reg != sc->io_shadow) { 467 468 if ((error = bus_space_map(sc->sc_bt, sbpa, 469 DINO_MEM_CHUNK, flags, &bush))) { 470 return (error); 471 } 472 r->io_addr_en |= reg; 473 sc->io_shadow = reg; 474 475 if (first) { 476 if (bshp) 477 *bshp = bush + (bpa - sbpa); 478 } 479 } else { 480 if (first) { 481 if (bshp) 482 *bshp = bpa; 483 } 484 } 485 486 if (first) { 487 size += (bpa - sbpa); 488 first = 0; 489 } 490 491 if (size < DINO_MEM_CHUNK) 492 size = 0; 493 else { 494 size -= DINO_MEM_CHUNK; 495 bpa = sbpa + DINO_MEM_CHUNK; 496 } 497 } 498 499 return (0); 500 } 501 502 int 503 dino_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset, 504 bus_size_t size, bus_space_handle_t *nbshp) 505 { 506 *nbshp = bsh + offset; 507 return (0); 508 } 509 510 int 511 dino_ioalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 512 bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, 513 bus_space_handle_t *bshp) 514 { 515 struct dino_softc *sc = v; 516 struct extent *ex = sc->sc_ioex; 517 bus_addr_t bpa; 518 int error; 519 520 if (rstart < ex->ex_start || rend > ex->ex_end) 521 panic("dino_ioalloc: bad region start/end"); 522 523 if ((error = extent_alloc_subregion(ex, rstart, rend, size, 524 align, 0, boundary, EX_NOWAIT, &bpa))) 525 return (error); 526 527 if (addrp) 528 *addrp = bpa; 529 if (bshp) 530 *bshp = bpa; 531 532 return (0); 533 } 534 535 int 536 dino_memalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 537 bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, 538 bus_space_handle_t *bshp) 539 { 540 struct dino_softc *sc = v; 541 volatile struct dino_regs *r = sc->sc_regs; 542 u_int32_t reg; 543 544 if (bus_space_alloc(sc->sc_bt, rstart, rend, size, 545 align, boundary, flags, addrp, bshp)) 546 return (ENOMEM); 547 548 reg = sc->io_shadow; 549 reg |= 1 << ((*addrp >> 23) & 0x1f); 550 if (reg & 0x80000001) { 551 #ifdef DEBUG 552 panic("mapping outside the mem extent range"); 553 #endif 554 return (EINVAL); 555 } 556 r->io_addr_en |= reg; 557 sc->io_shadow = reg; 558 559 return (0); 560 } 561 562 void 563 dino_unmap(void *v, bus_space_handle_t bsh, bus_size_t size) 564 { 565 struct dino_softc *sc = v; 566 struct extent *ex; 567 bus_addr_t bpa; 568 569 bpa = bsh; 570 if (bsh & 0xf0000000) { 571 /* TODO dino_unmap mem */ 572 /* TODO unmap from the upper bus if the last use in this 8M */ 573 return; 574 } else 575 ex = sc->sc_ioex; 576 577 if (extent_free(ex, bpa, size, EX_NOWAIT)) 578 printf("dino_unmap: ps 0x%lx, size 0x%lx\n" 579 "dino_unmap: can't free region\n", bpa, size); 580 } 581 582 void 583 dino_free(void *v, bus_space_handle_t bh, bus_size_t size) 584 { 585 /* should be enough */ 586 dino_unmap(v, bh, size); 587 } 588 589 void 590 dino_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int op) 591 { 592 sync_caches(); 593 } 594 595 #if NCARDBUS > 0 596 void * 597 dino_alloc_parent(struct device *self, struct pci_attach_args *pa, int io) 598 { 599 struct dino_softc *sc = pa->pa_pc->_cookie; 600 struct extent *ex; 601 bus_space_tag_t tag; 602 bus_addr_t start; 603 bus_size_t size; 604 605 if (io) { 606 ex = sc->sc_ioex; 607 tag = pa->pa_iot; 608 start = 0xa000; 609 size = 0x1000; 610 } else { 611 if (!sc->sc_memex) { 612 bus_space_handle_t memh; 613 bus_addr_t mem_start; 614 615 if (dino_memalloc(sc, 0xf0800000, 0xff7fffff, 616 DINO_MEM_WINDOW, DINO_MEM_WINDOW, EX_NOBOUNDARY, 617 0, &mem_start, &memh)) 618 return (NULL); 619 620 snprintf(sc->sc_memexname, sizeof(sc->sc_memexname), 621 "%s_mem", sc->sc_dv.dv_xname); 622 if ((sc->sc_memex = extent_create(sc->sc_memexname, 623 mem_start, mem_start + DINO_MEM_WINDOW, M_DEVBUF, 624 NULL, 0, EX_NOWAIT | EX_MALLOCOK)) == NULL) { 625 extent_destroy(sc->sc_ioex); 626 bus_space_free(sc->sc_bt, memh, 627 DINO_MEM_WINDOW); 628 return (NULL); 629 } 630 } 631 ex = sc->sc_memex; 632 tag = pa->pa_memt; 633 start = ex->ex_start; 634 size = DINO_MEM_CHUNK; 635 } 636 637 if (extent_alloc_subregion(ex, start, ex->ex_end, size, size, 0, 638 EX_NOBOUNDARY, EX_NOWAIT, &start)) 639 return (NULL); 640 641 extent_free(ex, start, size, EX_NOWAIT); 642 return rbus_new_root_share(tag, ex, start, size, 0); 643 } 644 #endif 645 646 void * 647 dino_vaddr(void *v, bus_space_handle_t h) 648 { 649 if (h & 0xf0000000) 650 return ((void *)h); 651 else 652 return (NULL); 653 } 654 655 u_int8_t 656 dino_r1(void *v, bus_space_handle_t h, bus_size_t o) 657 { 658 h += o; 659 if (h & 0xf0000000) 660 return *(volatile u_int8_t *)h; 661 else { 662 struct dino_softc *sc = v; 663 volatile struct dino_regs *r = sc->sc_regs; 664 u_int8_t data; 665 666 r->pci_addr = h; 667 data = *((volatile u_int8_t *)&r->pci_io_data + (h & 3)); 668 return (data); 669 } 670 } 671 672 u_int16_t 673 dino_r2(void *v, bus_space_handle_t h, bus_size_t o) 674 { 675 volatile u_int16_t *p; 676 677 h += o; 678 if (h & 0xf0000000) 679 p = (volatile u_int16_t *)h; 680 else { 681 struct dino_softc *sc = v; 682 volatile struct dino_regs *r = sc->sc_regs; 683 684 r->pci_addr = h; 685 p = (volatile u_int16_t *)&r->pci_io_data; 686 if (h & 2) 687 p++; 688 } 689 690 return (letoh16(*p)); 691 } 692 693 u_int32_t 694 dino_r4(void *v, bus_space_handle_t h, bus_size_t o) 695 { 696 u_int32_t data; 697 698 h += o; 699 if (h & 0xf0000000) 700 data = *(volatile u_int32_t *)h; 701 else { 702 struct dino_softc *sc = v; 703 volatile struct dino_regs *r = sc->sc_regs; 704 705 r->pci_addr = h; 706 data = r->pci_io_data; 707 } 708 709 return (letoh32(data)); 710 } 711 712 u_int64_t 713 dino_r8(void *v, bus_space_handle_t h, bus_size_t o) 714 { 715 u_int64_t data; 716 717 h += o; 718 if (h & 0xf0000000) 719 data = *(volatile u_int64_t *)h; 720 else 721 panic("dino_r8: not implemented"); 722 723 return (letoh64(data)); 724 } 725 726 void 727 dino_w1(void *v, bus_space_handle_t h, bus_size_t o, u_int8_t vv) 728 { 729 h += o; 730 if (h & 0xf0000000) 731 *(volatile u_int8_t *)h = vv; 732 else { 733 struct dino_softc *sc = v; 734 volatile struct dino_regs *r = sc->sc_regs; 735 736 r->pci_addr = h; 737 *((volatile u_int8_t *)&r->pci_io_data + (h & 3)) = vv; 738 } 739 } 740 741 void 742 dino_w2(void *v, bus_space_handle_t h, bus_size_t o, u_int16_t vv) 743 { 744 volatile u_int16_t *p; 745 746 h += o; 747 if (h & 0xf0000000) 748 p = (volatile u_int16_t *)h; 749 else { 750 struct dino_softc *sc = v; 751 volatile struct dino_regs *r = sc->sc_regs; 752 753 r->pci_addr = h; 754 p = (volatile u_int16_t *)&r->pci_io_data; 755 if (h & 2) 756 p++; 757 } 758 759 *p = htole16(vv); 760 } 761 762 void 763 dino_w4(void *v, bus_space_handle_t h, bus_size_t o, u_int32_t vv) 764 { 765 h += o; 766 vv = htole32(vv); 767 if (h & 0xf0000000) 768 *(volatile u_int32_t *)h = vv; 769 else { 770 struct dino_softc *sc = v; 771 volatile struct dino_regs *r = sc->sc_regs; 772 773 r->pci_addr = h; 774 r->pci_io_data = vv; 775 } 776 } 777 778 void 779 dino_w8(void *v, bus_space_handle_t h, bus_size_t o, u_int64_t vv) 780 { 781 h += o; 782 if (h & 0xf0000000) 783 *(volatile u_int64_t *)h = htole64(vv); 784 else 785 panic("dino_w8: not implemented"); 786 } 787 788 789 void 790 dino_rm_1(void *v, bus_space_handle_t h, bus_size_t o, u_int8_t *a, bus_size_t c) 791 { 792 volatile u_int8_t *p; 793 794 h += o; 795 if (h & 0xf0000000) 796 p = (volatile u_int8_t *)h; 797 else { 798 struct dino_softc *sc = v; 799 volatile struct dino_regs *r = sc->sc_regs; 800 801 r->pci_addr = h; 802 p = (volatile u_int8_t *)&r->pci_io_data + (h & 3); 803 } 804 805 while (c--) 806 *a++ = *p; 807 } 808 809 void 810 dino_rm_2(void *v, bus_space_handle_t h, bus_size_t o, u_int16_t *a, bus_size_t c) 811 { 812 volatile u_int16_t *p; 813 814 h += o; 815 if (h & 0xf0000000) 816 p = (volatile u_int16_t *)h; 817 else { 818 struct dino_softc *sc = v; 819 volatile struct dino_regs *r = sc->sc_regs; 820 821 r->pci_addr = h; 822 p = (volatile u_int16_t *)&r->pci_io_data; 823 if (h & 2) 824 p++; 825 } 826 827 while (c--) 828 *a++ = letoh16(*p); 829 } 830 831 void 832 dino_rm_4(void *v, bus_space_handle_t h, bus_size_t o, u_int32_t *a, bus_size_t c) 833 { 834 volatile u_int32_t *p; 835 836 h += o; 837 if (h & 0xf0000000) 838 p = (volatile u_int32_t *)h; 839 else { 840 struct dino_softc *sc = v; 841 volatile struct dino_regs *r = sc->sc_regs; 842 843 r->pci_addr = h; 844 p = (volatile u_int32_t *)&r->pci_io_data; 845 } 846 847 while (c--) 848 *a++ = letoh32(*p); 849 } 850 851 void 852 dino_rm_8(void *v, bus_space_handle_t h, bus_size_t o, u_int64_t *a, bus_size_t c) 853 { 854 panic("dino_rm_8: not implemented"); 855 } 856 857 void 858 dino_wm_1(void *v, bus_space_handle_t h, bus_size_t o, const u_int8_t *a, bus_size_t c) 859 { 860 volatile u_int8_t *p; 861 862 h += o; 863 if (h & 0xf0000000) 864 p = (volatile u_int8_t *)h; 865 else { 866 struct dino_softc *sc = v; 867 volatile struct dino_regs *r = sc->sc_regs; 868 869 r->pci_addr = h; 870 p = (volatile u_int8_t *)&r->pci_io_data + (h & 3); 871 } 872 873 while (c--) 874 *p = *a++; 875 } 876 877 void 878 dino_wm_2(void *v, bus_space_handle_t h, bus_size_t o, const u_int16_t *a, bus_size_t c) 879 { 880 volatile u_int16_t *p; 881 882 h += o; 883 if (h & 0xf0000000) 884 p = (volatile u_int16_t *)h; 885 else { 886 struct dino_softc *sc = v; 887 volatile struct dino_regs *r = sc->sc_regs; 888 889 r->pci_addr = h; 890 p = (volatile u_int16_t *)&r->pci_io_data; 891 if (h & 2) 892 p++; 893 } 894 895 while (c--) 896 *p = htole16(*a++); 897 } 898 899 void 900 dino_wm_4(void *v, bus_space_handle_t h, bus_size_t o, const u_int32_t *a, bus_size_t c) 901 { 902 volatile u_int32_t *p; 903 904 h += o; 905 if (h & 0xf0000000) 906 p = (volatile u_int32_t *)h; 907 else { 908 struct dino_softc *sc = v; 909 volatile struct dino_regs *r = sc->sc_regs; 910 911 r->pci_addr = h; 912 p = (volatile u_int32_t *)&r->pci_io_data; 913 } 914 915 while (c--) 916 *p = htole32(*a++); 917 } 918 919 void 920 dino_wm_8(void *v, bus_space_handle_t h, bus_size_t o, const u_int64_t *a, bus_size_t c) 921 { 922 panic("dino_wm_8: not implemented"); 923 } 924 925 void 926 dino_sm_1(void *v, bus_space_handle_t h, bus_size_t o, u_int8_t vv, bus_size_t c) 927 { 928 volatile u_int8_t *p; 929 930 h += o; 931 if (h & 0xf0000000) 932 p = (volatile u_int8_t *)h; 933 else { 934 struct dino_softc *sc = v; 935 volatile struct dino_regs *r = sc->sc_regs; 936 937 r->pci_addr = h; 938 p = (volatile u_int8_t *)&r->pci_io_data + (h & 3); 939 } 940 941 while (c--) 942 *p = vv; 943 } 944 945 void 946 dino_sm_2(void *v, bus_space_handle_t h, bus_size_t o, u_int16_t vv, bus_size_t c) 947 { 948 volatile u_int16_t *p; 949 950 h += o; 951 if (h & 0xf0000000) 952 p = (volatile u_int16_t *)h; 953 else { 954 struct dino_softc *sc = v; 955 volatile struct dino_regs *r = sc->sc_regs; 956 957 r->pci_addr = h; 958 p = (volatile u_int16_t *)&r->pci_io_data; 959 if (h & 2) 960 p++; 961 } 962 963 vv = htole16(vv); 964 while (c--) 965 *p = vv; 966 } 967 968 void 969 dino_sm_4(void *v, bus_space_handle_t h, bus_size_t o, u_int32_t vv, bus_size_t c) 970 { 971 volatile u_int32_t *p; 972 973 h += o; 974 if (h & 0xf0000000) 975 p = (volatile u_int32_t *)h; 976 else { 977 struct dino_softc *sc = v; 978 volatile struct dino_regs *r = sc->sc_regs; 979 980 r->pci_addr = h; 981 p = (volatile u_int32_t *)&r->pci_io_data; 982 } 983 984 vv = htole32(vv); 985 while (c--) 986 *p = vv; 987 } 988 989 void 990 dino_sm_8(void *v, bus_space_handle_t h, bus_size_t o, u_int64_t vv, bus_size_t c) 991 { 992 panic("dino_sm_8: not implemented"); 993 } 994 995 void 996 dino_rrm_2(void *v, bus_space_handle_t h, bus_size_t o, 997 u_int8_t *a, bus_size_t c) 998 { 999 volatile u_int16_t *p, *q = (u_int16_t *)a; 1000 1001 h += o; 1002 if (h & 0xf0000000) 1003 p = (volatile u_int16_t *)h; 1004 else { 1005 struct dino_softc *sc = v; 1006 volatile struct dino_regs *r = sc->sc_regs; 1007 1008 r->pci_addr = h; 1009 p = (volatile u_int16_t *)&r->pci_io_data; 1010 if (h & 2) 1011 p++; 1012 } 1013 1014 c /= 2; 1015 while (c--) 1016 *q++ = *p; 1017 } 1018 1019 void 1020 dino_rrm_4(void *v, bus_space_handle_t h, bus_size_t o, 1021 u_int8_t *a, bus_size_t c) 1022 { 1023 volatile u_int32_t *p, *q = (u_int32_t *)a; 1024 1025 h += o; 1026 if (h & 0xf0000000) 1027 p = (volatile u_int32_t *)h; 1028 else { 1029 struct dino_softc *sc = v; 1030 volatile struct dino_regs *r = sc->sc_regs; 1031 1032 r->pci_addr = h; 1033 p = (volatile u_int32_t *)&r->pci_io_data; 1034 } 1035 1036 c /= 4; 1037 while (c--) 1038 *q++ = *p; 1039 } 1040 1041 void 1042 dino_rrm_8(void *v, bus_space_handle_t h, bus_size_t o, 1043 u_int8_t *a, bus_size_t c) 1044 { 1045 panic("dino_rrm_8: not implemented"); 1046 } 1047 1048 void 1049 dino_wrm_2(void *v, bus_space_handle_t h, bus_size_t o, 1050 const u_int8_t *a, bus_size_t c) 1051 { 1052 volatile u_int16_t *p; 1053 const u_int16_t *q = (const u_int16_t *)a; 1054 1055 h += o; 1056 if (h & 0xf0000000) 1057 p = (volatile u_int16_t *)h; 1058 else { 1059 struct dino_softc *sc = v; 1060 volatile struct dino_regs *r = sc->sc_regs; 1061 1062 r->pci_addr = h; 1063 p = (volatile u_int16_t *)&r->pci_io_data; 1064 if (h & 2) 1065 p++; 1066 } 1067 1068 c /= 2; 1069 while (c--) 1070 *p = *q++; 1071 } 1072 1073 void 1074 dino_wrm_4(void *v, bus_space_handle_t h, bus_size_t o, 1075 const u_int8_t *a, bus_size_t c) 1076 { 1077 volatile u_int32_t *p; 1078 const u_int32_t *q = (const u_int32_t *)a; 1079 1080 h += o; 1081 if (h & 0xf0000000) 1082 p = (volatile u_int32_t *)h; 1083 else { 1084 struct dino_softc *sc = v; 1085 volatile struct dino_regs *r = sc->sc_regs; 1086 1087 r->pci_addr = h; 1088 p = (volatile u_int32_t *)&r->pci_io_data; 1089 } 1090 1091 c /= 4; 1092 while (c--) 1093 *p = *q++; 1094 } 1095 1096 void 1097 dino_wrm_8(void *v, bus_space_handle_t h, bus_size_t o, 1098 const u_int8_t *a, bus_size_t c) 1099 { 1100 panic("dino_wrm_8: not implemented"); 1101 } 1102 1103 void 1104 dino_rr_1(void *v, bus_space_handle_t h, bus_size_t o, u_int8_t *a, bus_size_t c) 1105 { 1106 volatile u_int8_t *p; 1107 1108 h += o; 1109 if (h & 0xf0000000) { 1110 p = (volatile u_int8_t *)h; 1111 while (c--) 1112 *a++ = *p++; 1113 } else { 1114 struct dino_softc *sc = v; 1115 volatile struct dino_regs *r = sc->sc_regs; 1116 1117 for (; c--; h++) { 1118 r->pci_addr = h; 1119 p = (volatile u_int8_t *)&r->pci_io_data + (h & 3); 1120 *a++ = *p; 1121 } 1122 } 1123 } 1124 1125 void 1126 dino_rr_2(void *v, bus_space_handle_t h, bus_size_t o, u_int16_t *a, bus_size_t c) 1127 { 1128 volatile u_int16_t *p, data; 1129 1130 h += o; 1131 if (h & 0xf0000000) { 1132 p = (volatile u_int16_t *)h; 1133 while (c--) { 1134 data = *p++; 1135 *a++ = letoh16(data); 1136 } 1137 } else { 1138 struct dino_softc *sc = v; 1139 volatile struct dino_regs *r = sc->sc_regs; 1140 1141 for (; c--; h += 2) { 1142 r->pci_addr = h; 1143 p = (volatile u_int16_t *)&r->pci_io_data; 1144 if (h & 2) 1145 p++; 1146 data = *p; 1147 *a++ = letoh16(data); 1148 } 1149 } 1150 } 1151 1152 void 1153 dino_rr_4(void *v, bus_space_handle_t h, bus_size_t o, u_int32_t *a, bus_size_t c) 1154 { 1155 volatile u_int32_t *p, data; 1156 1157 h += o; 1158 if (h & 0xf0000000) { 1159 p = (volatile u_int32_t *)h; 1160 while (c--) { 1161 data = *p++; 1162 *a++ = letoh32(data); 1163 } 1164 } else { 1165 struct dino_softc *sc = v; 1166 volatile struct dino_regs *r = sc->sc_regs; 1167 1168 for (; c--; h += 4) { 1169 r->pci_addr = h; 1170 data = r->pci_io_data; 1171 *a++ = letoh32(data); 1172 } 1173 } 1174 } 1175 1176 void 1177 dino_rr_8(void *v, bus_space_handle_t h, bus_size_t o, u_int64_t *a, bus_size_t c) 1178 { 1179 panic("dino_rr_8: not implemented"); 1180 } 1181 1182 void 1183 dino_wr_1(void *v, bus_space_handle_t h, bus_size_t o, const u_int8_t *a, bus_size_t c) 1184 { 1185 volatile u_int8_t *p; 1186 1187 h += o; 1188 if (h & 0xf0000000) { 1189 p = (volatile u_int8_t *)h; 1190 while (c--) 1191 *p++ = *a++; 1192 } else { 1193 struct dino_softc *sc = v; 1194 volatile struct dino_regs *r = sc->sc_regs; 1195 1196 for (; c--; h++) { 1197 r->pci_addr = h; 1198 p = (volatile u_int8_t *)&r->pci_io_data + (h & 3); 1199 *p = *a++; 1200 } 1201 } 1202 } 1203 1204 void 1205 dino_wr_2(void *v, bus_space_handle_t h, bus_size_t o, const u_int16_t *a, bus_size_t c) 1206 { 1207 volatile u_int16_t *p, data; 1208 1209 h += o; 1210 if (h & 0xf0000000) { 1211 p = (volatile u_int16_t *)h; 1212 while (c--) { 1213 data = *a++; 1214 *p++ = htole16(data); 1215 } 1216 } else { 1217 struct dino_softc *sc = v; 1218 volatile struct dino_regs *r = sc->sc_regs; 1219 1220 for (; c--; h += 2) { 1221 r->pci_addr = h; 1222 p = (volatile u_int16_t *)&r->pci_io_data; 1223 if (h & 2) 1224 p++; 1225 data = *a++; 1226 *p = htole16(data); 1227 } 1228 } 1229 } 1230 1231 void 1232 dino_wr_4(void *v, bus_space_handle_t h, bus_size_t o, const u_int32_t *a, bus_size_t c) 1233 { 1234 volatile u_int32_t *p, data; 1235 1236 h += o; 1237 if (h & 0xf0000000) { 1238 p = (volatile u_int32_t *)h; 1239 while (c--) { 1240 data = *a++; 1241 *p++ = htole32(data); 1242 } 1243 } else { 1244 struct dino_softc *sc = v; 1245 volatile struct dino_regs *r = sc->sc_regs; 1246 1247 for (; c--; h += 4) { 1248 r->pci_addr = h; 1249 data = *a++; 1250 r->pci_io_data = htole32(data); 1251 } 1252 } 1253 } 1254 1255 void 1256 dino_wr_8(void *v, bus_space_handle_t h, bus_size_t o, const u_int64_t *a, bus_size_t c) 1257 { 1258 panic("dino_wr_8: not implemented"); 1259 } 1260 1261 void 1262 dino_rrr_2(void *v, bus_space_handle_t h, bus_size_t o, 1263 u_int8_t *a, bus_size_t c) 1264 { 1265 volatile u_int16_t *p, *q = (u_int16_t *)a; 1266 1267 c /= 2; 1268 h += o; 1269 if (h & 0xf0000000) { 1270 p = (volatile u_int16_t *)h; 1271 while (c--) 1272 *q++ = *p++; 1273 } else { 1274 struct dino_softc *sc = v; 1275 volatile struct dino_regs *r = sc->sc_regs; 1276 1277 for (; c--; h += 2) { 1278 r->pci_addr = h; 1279 p = (volatile u_int16_t *)&r->pci_io_data; 1280 if (h & 2) 1281 p++; 1282 *q++ = *p; 1283 } 1284 } 1285 } 1286 1287 void 1288 dino_rrr_4(void *v, bus_space_handle_t h, bus_size_t o, 1289 u_int8_t *a, bus_size_t c) 1290 { 1291 volatile u_int32_t *p, *q = (u_int32_t *)a; 1292 1293 c /= 4; 1294 h += o; 1295 if (h & 0xf0000000) { 1296 p = (volatile u_int32_t *)h; 1297 while (c--) 1298 *q++ = *p++; 1299 } else { 1300 struct dino_softc *sc = v; 1301 volatile struct dino_regs *r = sc->sc_regs; 1302 1303 for (; c--; h += 4) { 1304 r->pci_addr = h; 1305 *q++ = r->pci_io_data; 1306 } 1307 } 1308 } 1309 1310 void 1311 dino_rrr_8(void *v, bus_space_handle_t h, bus_size_t o, 1312 u_int8_t *a, bus_size_t c) 1313 { 1314 panic("dino_rrr_8: not implemented"); 1315 } 1316 1317 void 1318 dino_wrr_2(void *v, bus_space_handle_t h, bus_size_t o, 1319 const u_int8_t *a, bus_size_t c) 1320 { 1321 volatile u_int16_t *p; 1322 const u_int16_t *q = (u_int16_t *)a; 1323 1324 c /= 2; 1325 h += o; 1326 if (h & 0xf0000000) { 1327 p = (volatile u_int16_t *)h; 1328 while (c--) 1329 *p++ = *q++; 1330 } else { 1331 struct dino_softc *sc = v; 1332 volatile struct dino_regs *r = sc->sc_regs; 1333 1334 for (; c--; h += 2) { 1335 r->pci_addr = h; 1336 p = (volatile u_int16_t *)&r->pci_io_data; 1337 if (h & 2) 1338 p++; 1339 *p = *q++; 1340 } 1341 } 1342 } 1343 1344 void 1345 dino_wrr_4(void *v, bus_space_handle_t h, bus_size_t o, 1346 const u_int8_t *a, bus_size_t c) 1347 { 1348 volatile u_int32_t *p; 1349 const u_int32_t *q = (u_int32_t *)a; 1350 1351 c /= 4; 1352 h += o; 1353 if (h & 0xf0000000) { 1354 p = (volatile u_int32_t *)h; 1355 while (c--) 1356 *p++ = *q++; 1357 } else { 1358 struct dino_softc *sc = v; 1359 volatile struct dino_regs *r = sc->sc_regs; 1360 1361 for (; c--; h += 4) { 1362 r->pci_addr = h; 1363 r->pci_io_data = *q++; 1364 } 1365 } 1366 } 1367 1368 void 1369 dino_wrr_8(void *v, bus_space_handle_t h, bus_size_t o, 1370 const u_int8_t *a, bus_size_t c) 1371 { 1372 panic("dino_wrr_8: not implemented"); 1373 } 1374 1375 void 1376 dino_sr_1(void *v, bus_space_handle_t h, bus_size_t o, u_int8_t vv, bus_size_t c) 1377 { 1378 volatile u_int8_t *p; 1379 1380 h += o; 1381 if (h & 0xf0000000) { 1382 p = (volatile u_int8_t *)h; 1383 while (c--) 1384 *p++ = vv; 1385 } else { 1386 struct dino_softc *sc = v; 1387 volatile struct dino_regs *r = sc->sc_regs; 1388 1389 for (; c--; h++) { 1390 r->pci_addr = h; 1391 p = (volatile u_int8_t *)&r->pci_io_data + (h & 3); 1392 *p = vv; 1393 } 1394 } 1395 } 1396 1397 void 1398 dino_sr_2(void *v, bus_space_handle_t h, bus_size_t o, u_int16_t vv, bus_size_t c) 1399 { 1400 volatile u_int16_t *p; 1401 1402 h += o; 1403 vv = htole16(vv); 1404 if (h & 0xf0000000) { 1405 p = (volatile u_int16_t *)h; 1406 while (c--) 1407 *p++ = vv; 1408 } else { 1409 struct dino_softc *sc = v; 1410 volatile struct dino_regs *r = sc->sc_regs; 1411 1412 for (; c--; h += 2) { 1413 r->pci_addr = h; 1414 p = (volatile u_int16_t *)&r->pci_io_data; 1415 if (h & 2) 1416 p++; 1417 *p = vv; 1418 } 1419 } 1420 } 1421 1422 void 1423 dino_sr_4(void *v, bus_space_handle_t h, bus_size_t o, u_int32_t vv, bus_size_t c) 1424 { 1425 volatile u_int32_t *p; 1426 1427 h += o; 1428 vv = htole32(vv); 1429 if (h & 0xf0000000) { 1430 p = (volatile u_int32_t *)h; 1431 while (c--) 1432 *p++ = vv; 1433 } else { 1434 struct dino_softc *sc = v; 1435 volatile struct dino_regs *r = sc->sc_regs; 1436 1437 for (; c--; h += 4) { 1438 r->pci_addr = h; 1439 r->pci_io_data = vv; 1440 } 1441 } 1442 } 1443 1444 void 1445 dino_sr_8(void *v, bus_space_handle_t h, bus_size_t o, u_int64_t vv, bus_size_t c) 1446 { 1447 panic("dino_sr_8: not implemented"); 1448 } 1449 1450 void 1451 dino_cp_1(void *v, bus_space_handle_t h1, bus_size_t o1, 1452 bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1453 { 1454 while (c--) 1455 dino_w1(v, h1, o1++, dino_r1(v, h2, o2++)); 1456 } 1457 1458 void 1459 dino_cp_2(void *v, bus_space_handle_t h1, bus_size_t o1, 1460 bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1461 { 1462 while (c--) { 1463 dino_w2(v, h1, o1, dino_r2(v, h2, o2)); 1464 o1 += 2; 1465 o2 += 2; 1466 } 1467 } 1468 1469 void 1470 dino_cp_4(void *v, bus_space_handle_t h1, bus_size_t o1, 1471 bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1472 { 1473 while (c--) { 1474 dino_w4(v, h1, o1, dino_r4(v, h2, o2)); 1475 o1 += 4; 1476 o2 += 4; 1477 } 1478 } 1479 1480 void 1481 dino_cp_8(void *v, bus_space_handle_t h1, bus_size_t o1, 1482 bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1483 { 1484 while (c--) { 1485 dino_w8(v, h1, o1, dino_r8(v, h2, o2)); 1486 o1 += 8; 1487 o2 += 8; 1488 } 1489 } 1490 1491 1492 const struct hppa_bus_space_tag dino_iomemt = { 1493 NULL, 1494 1495 NULL, dino_unmap, dino_subregion, NULL, dino_free, 1496 dino_barrier, dino_vaddr, 1497 dino_r1, dino_r2, dino_r4, dino_r8, 1498 dino_w1, dino_w2, dino_w4, dino_w8, 1499 dino_rm_1, dino_rm_2, dino_rm_4, dino_rm_8, 1500 dino_wm_1, dino_wm_2, dino_wm_4, dino_wm_8, 1501 dino_sm_1, dino_sm_2, dino_sm_4, dino_sm_8, 1502 dino_rrm_2, dino_rrm_4, dino_rrm_8, 1503 dino_wrm_2, dino_wrm_4, dino_wrm_8, 1504 dino_rr_1, dino_rr_2, dino_rr_4, dino_rr_8, 1505 dino_wr_1, dino_wr_2, dino_wr_4, dino_wr_8, 1506 dino_rrr_2, dino_rrr_4, dino_rrr_8, 1507 dino_wrr_2, dino_wrr_4, dino_wrr_8, 1508 dino_sr_1, dino_sr_2, dino_sr_4, dino_sr_8, 1509 dino_cp_1, dino_cp_2, dino_cp_4, dino_cp_8 1510 }; 1511 1512 int 1513 dino_dmamap_create(void *v, bus_size_t size, int nsegments, 1514 bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp) 1515 { 1516 struct dino_softc *sc = v; 1517 1518 /* TODO check the addresses, boundary, enable dma */ 1519 1520 return (bus_dmamap_create(sc->sc_dmat, size, nsegments, 1521 maxsegsz, boundary, flags, dmamp)); 1522 } 1523 1524 void 1525 dino_dmamap_destroy(void *v, bus_dmamap_t map) 1526 { 1527 struct dino_softc *sc = v; 1528 1529 bus_dmamap_destroy(sc->sc_dmat, map); 1530 } 1531 1532 int 1533 dino_dmamap_load(void *v, bus_dmamap_t map, void *addr, bus_size_t size, 1534 struct proc *p, int flags) 1535 { 1536 struct dino_softc *sc = v; 1537 1538 return (bus_dmamap_load(sc->sc_dmat, map, addr, size, p, flags)); 1539 } 1540 1541 int 1542 dino_dmamap_load_mbuf(void *v, bus_dmamap_t map, struct mbuf *m, int flags) 1543 { 1544 struct dino_softc *sc = v; 1545 1546 return (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, flags)); 1547 } 1548 1549 int 1550 dino_dmamap_load_uio(void *v, bus_dmamap_t map, struct uio *uio, int flags) 1551 { 1552 struct dino_softc *sc = v; 1553 1554 return (bus_dmamap_load_uio(sc->sc_dmat, map, uio, flags)); 1555 } 1556 1557 int 1558 dino_dmamap_load_raw(void *v, bus_dmamap_t map, bus_dma_segment_t *segs, 1559 int nsegs, bus_size_t size, int flags) 1560 { 1561 struct dino_softc *sc = v; 1562 1563 return (bus_dmamap_load_raw(sc->sc_dmat, map, segs, nsegs, size, flags)); 1564 } 1565 1566 void 1567 dino_dmamap_unload(void *v, bus_dmamap_t map) 1568 { 1569 struct dino_softc *sc = v; 1570 1571 bus_dmamap_unload(sc->sc_dmat, map); 1572 } 1573 1574 void 1575 dino_dmamap_sync(void *v, bus_dmamap_t map, bus_addr_t off, 1576 bus_size_t len, int ops) 1577 { 1578 struct dino_softc *sc = v; 1579 1580 return (bus_dmamap_sync(sc->sc_dmat, map, off, len, ops)); 1581 } 1582 1583 int 1584 dino_dmamem_alloc(void *v, bus_size_t size, bus_size_t alignment, 1585 bus_size_t boundary, bus_dma_segment_t *segs, 1586 int nsegs, int *rsegs, int flags) 1587 { 1588 struct dino_softc *sc = v; 1589 1590 return (bus_dmamem_alloc(sc->sc_dmat, size, alignment, boundary, 1591 segs, nsegs, rsegs, flags)); 1592 } 1593 1594 void 1595 dino_dmamem_free(void *v, bus_dma_segment_t *segs, int nsegs) 1596 { 1597 struct dino_softc *sc = v; 1598 1599 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1600 } 1601 1602 int 1603 dino_dmamem_map(void *v, bus_dma_segment_t *segs, int nsegs, size_t size, 1604 caddr_t *kvap, int flags) 1605 { 1606 struct dino_softc *sc = v; 1607 1608 return (bus_dmamem_map(sc->sc_dmat, segs, nsegs, size, kvap, flags)); 1609 } 1610 1611 void 1612 dino_dmamem_unmap(void *v, caddr_t kva, size_t size) 1613 { 1614 struct dino_softc *sc = v; 1615 1616 bus_dmamem_unmap(sc->sc_dmat, kva, size); 1617 } 1618 1619 paddr_t 1620 dino_dmamem_mmap(void *v, bus_dma_segment_t *segs, int nsegs, off_t off, 1621 int prot, int flags) 1622 { 1623 struct dino_softc *sc = v; 1624 1625 return (bus_dmamem_mmap(sc->sc_dmat, segs, nsegs, off, prot, flags)); 1626 } 1627 1628 const struct hppa_bus_dma_tag dino_dmat = { 1629 NULL, 1630 dino_dmamap_create, dino_dmamap_destroy, 1631 dino_dmamap_load, dino_dmamap_load_mbuf, 1632 dino_dmamap_load_uio, dino_dmamap_load_raw, 1633 dino_dmamap_unload, dino_dmamap_sync, 1634 1635 dino_dmamem_alloc, dino_dmamem_free, dino_dmamem_map, 1636 dino_dmamem_unmap, dino_dmamem_mmap 1637 }; 1638 1639 const struct hppa_pci_chipset_tag dino_pc = { 1640 NULL, 1641 dino_attach_hook, dino_maxdevs, dino_make_tag, dino_decompose_tag, 1642 dino_conf_read, dino_conf_write, 1643 dino_intr_map, dino_intr_string, 1644 dino_intr_establish, dino_intr_disestablish, 1645 #if NCARDBUS > 0 1646 dino_alloc_parent 1647 #else 1648 NULL 1649 #endif 1650 }; 1651 1652 int 1653 dinoprint(void *aux, const char *pnp) 1654 { 1655 struct pcibus_attach_args *pba = aux; 1656 1657 if (pnp) 1658 printf("%s at %s\n", pba->pba_busname, pnp); 1659 return (UNCONF); 1660 } 1661 1662 void 1663 dinoattach(parent, self, aux) 1664 struct device *parent; 1665 struct device *self; 1666 void *aux; 1667 { 1668 struct dino_softc *sc = (struct dino_softc *)self; 1669 struct confargs *ca = (struct confargs *)aux; 1670 struct pcibus_attach_args pba; 1671 volatile struct dino_regs *r; 1672 const char *p = NULL; 1673 u_int data; 1674 int s; 1675 1676 sc->sc_bt = ca->ca_iot; 1677 sc->sc_dmat = ca->ca_dmatag; 1678 if (bus_space_map(sc->sc_bt, ca->ca_hpa, PAGE_SIZE, 0, &sc->sc_bh)) { 1679 printf(": can't map space\n"); 1680 return; 1681 } 1682 1683 sc->sc_regs = r = (volatile struct dino_regs *)sc->sc_bh; 1684 r->pciror = 0; 1685 r->pciwor = 0; 1686 1687 /* 1688 * Do not reset enabled io mappings mask if we are still running 1689 * with PDC console - we'll do it after autoconf. 1690 */ 1691 if (cn_tab->cn_putc != pdccnputc) 1692 r->io_addr_en = 0; 1693 sc->io_shadow = 0; 1694 1695 r->gmask &= ~1; /* allow GSC bus req */ 1696 r->brdg_feat &= ~0xf00; 1697 r->brdg_feat |= 3; 1698 #ifdef notyet_card_mode 1699 r->io_control = 0x80; 1700 r->pamr = 0; 1701 r->papr = 0; 1702 r->io_fbb_en |= 1; 1703 r->damode = 0; 1704 r->brdg_feat = 0xc0000000 XXX; 1705 r->mltim = 0x40; /* 64 clocks */ 1706 r->tltim = 0x8c; /* 12 clocks */ 1707 1708 /* PCI reset */ 1709 r->pcicmd = 0x6f; 1710 DELAY(10000); /* 10ms for reset to settle */ 1711 #endif 1712 1713 snprintf(sc->sc_ioexname, sizeof(sc->sc_ioexname), 1714 "%s_io", sc->sc_dv.dv_xname); 1715 if ((sc->sc_ioex = extent_create(sc->sc_ioexname, 0, 0xffff, 1716 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_MALLOCOK)) == NULL) { 1717 printf(": cannot allocate I/O extent map\n"); 1718 bus_space_unmap(sc->sc_bt, sc->sc_bh, PAGE_SIZE); 1719 return; 1720 } 1721 1722 /* TODO reserve dino's pci space ? */ 1723 1724 s = splhigh(); 1725 r->imr = ~0; 1726 data = r->irr0; 1727 data = r->irr1; 1728 r->imr = 0; 1729 __asm __volatile ("" ::: "memory"); 1730 r->icr = 0; 1731 r->iar0 = cpu_gethpa(0) | (31 - ca->ca_irq); 1732 splx(s); 1733 1734 sc->sc_ih = cpu_intr_establish(IPL_NESTED, ca->ca_irq, 1735 dino_intr, (void *)sc->sc_regs, sc->sc_dv.dv_xname); 1736 /* TODO establish the bus error interrupt */ 1737 1738 sc->sc_ver = ca->ca_type.iodc_revision; 1739 switch ((ca->ca_type.iodc_model << 4) | 1740 (ca->ca_type.iodc_revision >> 4)) { 1741 case 0x05d: /* j2240 */ 1742 p = "Dino(card)"; 1743 case 0x680: 1744 if (!p) 1745 p = "Dino"; 1746 switch (ca->ca_type.iodc_revision & 0xf) { 1747 case 0: sc->sc_ver = 0x20; break; 1748 case 1: sc->sc_ver = 0x21; break; 1749 case 2: sc->sc_ver = 0x30; break; 1750 case 3: sc->sc_ver = 0x31; break; 1751 } 1752 break; 1753 1754 case 0x682: 1755 p = "Cujo"; 1756 switch (ca->ca_type.iodc_revision & 0xf) { 1757 case 0: sc->sc_ver = 0x10; break; 1758 case 1: sc->sc_ver = 0x20; break; 1759 } 1760 break; 1761 1762 default: 1763 p = "Mojo"; 1764 break; 1765 } 1766 1767 printf(": %s V%d.%d\n", p, sc->sc_ver >> 4, sc->sc_ver & 0xf); 1768 1769 sc->sc_iot = dino_iomemt; 1770 sc->sc_iot.hbt_cookie = sc; 1771 sc->sc_iot.hbt_map = dino_iomap; 1772 sc->sc_iot.hbt_alloc = dino_ioalloc; 1773 sc->sc_memt = dino_iomemt; 1774 sc->sc_memt.hbt_cookie = sc; 1775 sc->sc_memt.hbt_map = dino_memmap; 1776 sc->sc_memt.hbt_alloc = dino_memalloc; 1777 sc->sc_pc = dino_pc; 1778 sc->sc_pc._cookie = sc; 1779 sc->sc_dmatag = dino_dmat; 1780 sc->sc_dmatag._cookie = sc; 1781 1782 /* scan for ps2 kbd/ms, serial, and flying toasters */ 1783 ca->ca_hpamask = -1; 1784 pdc_scanbus(self, ca, MAXMODBUS, 0); 1785 1786 bzero(&pba, sizeof(pba)); 1787 pba.pba_busname = "pci"; 1788 pba.pba_iot = &sc->sc_iot; 1789 pba.pba_memt = &sc->sc_memt; 1790 pba.pba_dmat = &sc->sc_dmatag; 1791 pba.pba_pc = &sc->sc_pc; 1792 pba.pba_domain = pci_ndomains++; 1793 pba.pba_bus = 0; 1794 config_found(self, &pba, dinoprint); 1795 1796 /* postpone cleanup if necessary */ 1797 if (r->io_addr_en != sc->io_shadow) 1798 startuphook_establish(dino_clear_pdc_mappings, sc); 1799 1800 /* enable interrupts now that all the devices are there */ 1801 r->imr = sc->sc_imr; 1802 } 1803 1804 void 1805 dino_clear_pdc_mappings(void *v) 1806 { 1807 struct dino_softc *sc = (struct dino_softc *)v; 1808 volatile struct dino_regs *r; 1809 1810 if (cn_tab->cn_putc == pdccnputc) { 1811 /* damn! */ 1812 return; 1813 } 1814 1815 r = sc->sc_regs; 1816 r->io_addr_en = sc->io_shadow; 1817 } 1818