1 /* $OpenBSD: pte.h,v 1.8 2016/08/27 14:22:35 kettenis Exp $ */ 2 /* $NetBSD: pte.h,v 1.6 2003/04/18 11:08:28 scw Exp $ */ 3 4 /* 5 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 6 * All rights reserved. 7 * 8 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * Wasabi Systems, Inc. 22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _ARM_PTE_H_ 40 #define _ARM_PTE_H_ 41 42 /* 43 * The ARM MMU architecture was introduced with ARM v3 (previous ARM 44 * architecture versions used an optional off-CPU memory controller 45 * to perform address translation). 46 * 47 * The ARM MMU consists of a TLB and translation table walking logic. 48 * There is typically one TLB per memory interface (or, put another 49 * way, one TLB per software-visible cache). 50 * 51 * The ARM MMU is capable of mapping memory in the following chunks: 52 * 53 * 1M Sections (L1 table) 54 * 55 * 64K Large Pages (L2 table) 56 * 57 * 4K Small Pages (L2 table) 58 * 59 * 1K Tiny Pages (L2 table) 60 * 61 * There are two types of L2 tables: Coarse Tables and Fine Tables. 62 * Coarse Tables can map Large and Small Pages. Fine Tables can 63 * map Tiny Pages. 64 * 65 * Coarse Tables can define 4 Subpages within Large and Small pages. 66 * Subpages define different permissions for each Subpage within 67 * a Page. 68 * 69 * Coarse Tables are 1K in length. Fine tables are 4K in length. 70 * 71 * The Translation Table Base register holds the pointer to the 72 * L1 Table. The L1 Table is a 16K contiguous chunk of memory 73 * aligned to a 16K boundary. Each entry in the L1 Table maps 74 * 1M of virtual address space, either via a Section mapping or 75 * via an L2 Table. 76 * 77 * In addition, the Fast Context Switching Extension (FCSE) is available 78 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating 79 * TLB/cache flushes on context switch by use of a smaller address space 80 * and a "process ID" that modifies the virtual address before being 81 * presented to the translation logic. 82 */ 83 84 #ifndef _LOCORE 85 typedef uint32_t pd_entry_t; /* L1 table entry */ 86 typedef uint32_t pt_entry_t; /* L2 table entry */ 87 #endif /* _LOCORE */ 88 89 #define L1_S_SIZE 0x00100000 /* 1M */ 90 #define L1_S_OFFSET (L1_S_SIZE - 1) 91 #define L1_S_FRAME (~L1_S_OFFSET) 92 #define L1_S_SHIFT 20 93 94 #define L2_L_SIZE 0x00010000 /* 64K */ 95 #define L2_L_OFFSET (L2_L_SIZE - 1) 96 #define L2_L_FRAME (~L2_L_OFFSET) 97 #define L2_L_SHIFT 16 98 99 #define L2_S_SIZE 0x00001000 /* 4K */ 100 #define L2_S_OFFSET (L2_S_SIZE - 1) 101 #define L2_S_FRAME (~L2_S_OFFSET) 102 #define L2_S_SHIFT 12 103 104 #define L2_T_SIZE 0x00000400 /* 1K */ 105 #define L2_T_OFFSET (L2_T_SIZE - 1) 106 #define L2_T_FRAME (~L2_T_OFFSET) 107 #define L2_T_SHIFT 10 108 109 /* 110 * The NetBSD VM implementation only works on whole pages (4K), 111 * whereas the ARM MMU's Coarse tables are sized in terms of 1K 112 * (16K L1 table, 1K L2 table). 113 * 114 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2 115 * table. 116 */ 117 #define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */ 118 #define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */ 119 120 #define L1_TABLE_SIZE 0x4000 /* 16K */ 121 #define L2_TABLE_SIZE 0x1000 /* 4K */ 122 /* 123 * The new pmap deals with the 1KB coarse L2 tables by 124 * allocating them from a pool. Until every port has been converted, 125 * keep the old L2_TABLE_SIZE define lying around. Converted ports 126 * should use L2_TABLE_SIZE_REAL until then. 127 */ 128 #define L2_TABLE_SIZE_REAL 0x400 /* 1K */ 129 130 /* 131 * ARM L1 Descriptors 132 */ 133 134 #define L1_TYPE_INV 0x00 /* Invalid (fault) */ 135 #define L1_TYPE_C 0x01 /* Coarse L2 */ 136 #define L1_TYPE_S 0x02 /* Section or Supersection */ 137 #define L1_TYPE_F 0x03 /* Fine L2 (pre-V7) */ 138 #define L1_TYPE_MASK 0x03 /* mask of type bits */ 139 140 /* L1 Section Descriptor */ 141 #define L1_S_B 0x00000004 /* bufferable Section */ 142 #define L1_S_C 0x00000008 /* cacheable Section */ 143 #define L1_S_IMP 0x00000010 /* implementation defined */ 144 #define L1_S_DOM(x) ((x) << 5) /* domain */ 145 #define L1_S_DOM_MASK L1_S_DOM(0xf) 146 #define L1_S_AP(x) ((x) << 10) /* access permissions */ 147 #define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ 148 149 #define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ 150 #define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */ 151 152 #define L1_S_V7_TEX(x) (((x) & 0x7) << 12) /* Type Extension */ 153 #define L1_S_V7_TEX_MASK (0x7 << 12) /* Type Extension */ 154 #define L1_S_V7_NS 0x00080000 /* Non-secure */ 155 #define L1_S_V7_SS 0x00040000 /* Supersection */ 156 #define L1_S_V7_nG 0x00020000 /* not Global */ 157 #define L1_S_V7_S 0x00010000 /* Shareable */ 158 #define L1_S_V7_AP(x) ((((x) & 0x4) << 13) | (((x) & 0x2) << 10)) /* AP */ 159 #define L1_S_V7_AF 0x00000400 /* Access Flag */ 160 #define L1_S_V7_IMP 0x00000200 /* implementation defined */ 161 #define L1_S_V7_XN 0x00000010 /* eXecute Never */ 162 #define L1_S_V7_PXN 0x00000001 /* Privileged eXecute Never */ 163 164 /* L1 Coarse Descriptor */ 165 #define L1_C_IMP0 0x00000004 /* implementation defined */ 166 #define L1_C_IMP1 0x00000008 /* implementation defined */ 167 #define L1_C_IMP2 0x00000010 /* implementation defined */ 168 #define L1_C_DOM(x) ((x) << 5) /* domain */ 169 #define L1_C_DOM_MASK L1_C_DOM(0xf) 170 #define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 171 172 #define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */ 173 174 #define L1_C_V7_IMP 0x00000200 /* implementation defined */ 175 #define L1_C_V7_NS 0x00000008 /* Non-secure */ 176 #define L1_C_V7_PXN 0x00000004 /* Privileged eXecute Never */ 177 178 /* L1 Fine Descriptor */ 179 #define L1_F_IMP0 0x00000004 /* implementation defined */ 180 #define L1_F_IMP1 0x00000008 /* implementation defined */ 181 #define L1_F_IMP2 0x00000010 /* implementation defined */ 182 #define L1_F_DOM(x) ((x) << 5) /* domain */ 183 #define L1_F_DOM_MASK L1_F_DOM(0xf) 184 #define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */ 185 186 #define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */ 187 188 /* 189 * ARM L2 Descriptors 190 */ 191 192 #define L2_TYPE_INV 0x00 /* Invalid (fault) */ 193 #define L2_TYPE_L 0x01 /* Large Page */ 194 #define L2_TYPE_S 0x02 /* Small Page */ 195 #define L2_TYPE_T 0x03 /* Tiny Page (pre-V7) */ 196 #define L2_TYPE_MASK 0x03 /* mask of type bits */ 197 198 /* 199 * This L2 Descriptor type is available on XScale processors 200 * when using a Coarse L1 Descriptor. The Extended Small 201 * Descriptor has the same format as the XScale Tiny Descriptor, 202 * but describes a 4K page, rather than a 1K page. 203 */ 204 #define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */ 205 206 #define L2_B 0x00000004 /* Bufferable page */ 207 #define L2_C 0x00000008 /* Cacheable page */ 208 #define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ 209 #define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ 210 #define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ 211 #define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ 212 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 213 214 #define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */ 215 #define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */ 216 217 #define L2_V7_L_TEX(x) (((x) & 0x7) << 12) /* Type Extension */ 218 #define L2_V7_L_TEX_MASK (0x7 << 12) /* Type Extension */ 219 #define L2_V7_L_XN 0x00008000 /* eXecute Never */ 220 #define L2_V7_S_TEX(x) (((x) & 0x7) << 6) /* Type Extension */ 221 #define L2_V7_S_TEX_MASK (0x7 << 6) /* Type Extension */ 222 #define L2_V7_S_XN 0x00000001 /* eXecute Never */ 223 224 #define L2_V7_AP(x) ((((x) & 0x4) << 7) | (((x) & 0x2) << 4)) /* AP */ 225 #define L2_V7_AF 0x00000010 /* Access Flag */ 226 #define L2_V7_S 0x00000400 /* Sharable */ 227 #define L2_V7_nG 0x00000800 /* not Global */ 228 229 /* 230 * Access Permissions for L1 and L2 Descriptors. (except for V7) 231 */ 232 #define AP_W 0x01 /* writable */ 233 #define AP_U 0x02 /* user */ 234 235 /* 236 * Short-hand for common AP_* constants. 237 * 238 * Note: These values assume the S (System) bit is set and 239 * the R (ROM) bit is clear in CP15 register 1. 240 */ 241 #define AP_KR 0x00 /* kernel read */ 242 #define AP_V7_KR 0x05 243 #define AP_KRW 0x01 /* kernel read/write */ 244 #define AP_KRWUR 0x02 /* kernel read/write usr read */ 245 #define AP_V7_KRUR 0x07 /* kernel read usr read */ 246 #define AP_KRWURW 0x03 /* kernel read/write usr read/write */ 247 248 /* 249 * Domain Types for the Domain Access Control Register. 250 */ 251 #define DOMAIN_FAULT 0x00 /* no access */ 252 #define DOMAIN_CLIENT 0x01 /* client */ 253 #define DOMAIN_RESERVED 0x02 /* reserved */ 254 #define DOMAIN_MANAGER 0x03 /* manager */ 255 256 /* 257 * Type Extension bits for XScale processors. 258 * 259 * Behavior of C and B when X == 0: 260 * 261 * C B Cacheable Bufferable Write Policy Line Allocate Policy 262 * 0 0 N N - - 263 * 0 1 N Y - - 264 * 1 0 Y Y Write-through Read Allocate 265 * 1 1 Y Y Write-back Read Allocate 266 * 267 * Behavior of C and B when X == 1: 268 * C B Cacheable Bufferable Write Policy Line Allocate Policy 269 * 0 0 - - - - DO NOT USE 270 * 0 1 N Y - - 271 * 1 0 Mini-Data - - - 272 * 1 1 Y Y Write-back R/W Allocate 273 */ 274 #define TEX_XSCALE_X 0x01 /* X modifies C and B */ 275 276 #endif /* _ARM_PTE_H_ */ 277