1 /* $OpenBSD: pmap.h,v 1.25 2014/01/30 18:16:41 miod Exp $ */ 2 /* $NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $ */ 3 4 /* 5 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 6 * All rights reserved. 7 * 8 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * Wasabi Systems, Inc. 22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1994,1995 Mark Brinicombe. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Mark Brinicombe 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 #ifndef _ARM_PMAP_H_ 70 #define _ARM_PMAP_H_ 71 72 #include <sys/lock.h> /* struct simplelock */ 73 74 #ifdef _KERNEL 75 76 #include <arm/cpuconf.h> 77 #include <arm/pte.h> 78 #ifndef _LOCORE 79 #include <arm/cpufunc.h> 80 #endif 81 82 /* 83 * a pmap describes a processes' 4GB virtual address space. this 84 * virtual address space can be broken up into 4096 1MB regions which 85 * are described by L1 PTEs in the L1 table. 86 * 87 * There is a line drawn at KERNEL_BASE. Everything below that line 88 * changes when the VM context is switched. Everything above that line 89 * is the same no matter which VM context is running. This is achieved 90 * by making the L1 PTEs for those slots above KERNEL_BASE reference 91 * kernel L2 tables. 92 * 93 * The basic layout of the virtual address space thus looks like this: 94 * 95 * 0xffffffff 96 * . 97 * . 98 * . 99 * KERNEL_BASE 100 * -------------------- 101 * . 102 * . 103 * . 104 * 0x00000000 105 */ 106 107 /* 108 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 109 * A bucket size of 16 provides for 16MB of contiguous virtual address 110 * space per l2_dtable. Most processes will, therefore, require only two or 111 * three of these to map their whole working set. 112 */ 113 #define L2_BUCKET_LOG2 4 114 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 115 116 /* 117 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 118 * of l2_dtable structures required to track all possible page descriptors 119 * mappable by an L1 translation table is given by the following constants: 120 */ 121 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 122 #define L2_SIZE (1 << L2_LOG2) 123 124 #ifndef _LOCORE 125 126 struct l1_ttable; 127 struct l2_dtable; 128 129 /* 130 * Track cache/tlb occupancy using the following structure 131 */ 132 union pmap_cache_state { 133 struct { 134 union { 135 u_int8_t csu_cache_b[2]; 136 u_int16_t csu_cache; 137 } cs_cache_u; 138 139 union { 140 u_int8_t csu_tlb_b[2]; 141 u_int16_t csu_tlb; 142 } cs_tlb_u; 143 } cs_s; 144 u_int32_t cs_all; 145 }; 146 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 147 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 148 #define cs_cache cs_s.cs_cache_u.csu_cache 149 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 150 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 151 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 152 153 /* 154 * Assigned to cs_all to force cacheops to work for a particular pmap 155 */ 156 #define PMAP_CACHE_STATE_ALL 0xffffffffu 157 158 /* 159 * This structure is used by machine-dependent code to describe 160 * static mappings of devices, created at bootstrap time. 161 */ 162 struct pmap_devmap { 163 vaddr_t pd_va; /* virtual address */ 164 paddr_t pd_pa; /* physical address */ 165 psize_t pd_size; /* size of region */ 166 vm_prot_t pd_prot; /* protection code */ 167 int pd_cache; /* cache attributes */ 168 }; 169 170 /* 171 * The pmap structure itself 172 */ 173 struct pmap { 174 u_int8_t pm_domain; 175 boolean_t pm_remove_all; 176 struct l1_ttable *pm_l1; 177 union pmap_cache_state pm_cstate; 178 u_int pm_refs; 179 simple_lock_data_t pm_lock; 180 struct l2_dtable *pm_l2[L2_SIZE]; 181 struct pmap_statistics pm_stats; 182 }; 183 184 typedef struct pmap *pmap_t; 185 186 /* 187 * Physical / virtual address structure. In a number of places (particularly 188 * during bootstrapping) we need to keep track of the physical and virtual 189 * addresses of various pages 190 */ 191 typedef struct pv_addr { 192 SLIST_ENTRY(pv_addr) pv_list; 193 paddr_t pv_pa; 194 vaddr_t pv_va; 195 } pv_addr_t; 196 197 /* 198 * Determine various modes for PTEs (user vs. kernel, cacheable 199 * vs. non-cacheable). 200 */ 201 #define PTE_KERNEL 0 202 #define PTE_USER 1 203 #define PTE_NOCACHE 0 204 #define PTE_CACHE 1 205 #define PTE_PAGETABLE 2 206 207 /* 208 * Flags that indicate attributes of pages or mappings of pages. 209 * 210 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 211 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 212 * pv_entry's for each page. They live in the same "namespace" so 213 * that we can clear multiple attributes at a time. 214 * 215 * Note the "non-cacheable" flag generally means the page has 216 * multiple mappings in a given address space. 217 */ 218 #define PVF_MOD 0x01 /* page is modified */ 219 #define PVF_REF 0x02 /* page is referenced */ 220 #define PVF_WIRED 0x04 /* mapping is wired */ 221 #define PVF_WRITE 0x08 /* mapping is writable */ 222 #define PVF_EXEC 0x10 /* mapping is executable */ 223 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 224 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 225 #define PVF_NC (PVF_UNC|PVF_KNC) 226 227 /* 228 * Commonly referenced structures 229 */ 230 extern struct pmap kernel_pmap_store; 231 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 232 233 /* 234 * Macros that we need to export 235 */ 236 #define pmap_kernel() (&kernel_pmap_store) 237 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 238 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 239 240 #define pmap_is_modified(pg) \ 241 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 242 #define pmap_is_referenced(pg) \ 243 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 244 245 #define pmap_deactivate(p) do { /* nothing */ } while (0) 246 #define pmap_copy(dp, sp, da, l, sa) do { /* nothing */ } while (0) 247 248 #define pmap_unuse_final(p) do { /* nothing */ } while (0) 249 #define pmap_remove_holes(map) do { /* nothing */ } while (0) 250 251 /* 252 * Functions that we need to export 253 */ 254 void pmap_remove_all(pmap_t); 255 void pmap_uncache_page(paddr_t, vaddr_t); 256 257 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 258 259 /* Functions we use internally. */ 260 void pmap_bootstrap(pd_entry_t *, vaddr_t, vaddr_t); 261 262 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 263 boolean_t pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 264 boolean_t pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 265 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 266 267 void pmap_debug(int); 268 void pmap_postinit(void); 269 270 void vector_page_setprot(int); 271 272 /* XXX */ 273 void pmap_kenter_cache(vaddr_t va, paddr_t pa, vm_prot_t prot, int cacheable); 274 275 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 276 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 277 278 /* Bootstrapping routines. */ 279 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 280 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 281 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 282 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 283 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 284 void pmap_devmap_register(const struct pmap_devmap *); 285 286 /* 287 * Special page zero routine for use by the idle loop (no cache cleans). 288 */ 289 boolean_t pmap_pageidlezero(struct vm_page *); 290 #define PMAP_PAGEIDLEZERO(pg) pmap_pageidlezero((pg)) 291 292 /* 293 * The current top of kernel VM 294 */ 295 extern vaddr_t pmap_curmaxkvaddr; 296 297 /* 298 * Useful macros and constants 299 */ 300 301 /* Virtual address to page table entry */ 302 static __inline pt_entry_t * 303 vtopte(vaddr_t va) 304 { 305 pd_entry_t *pdep; 306 pt_entry_t *ptep; 307 308 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 309 return (NULL); 310 return (ptep); 311 } 312 313 /* 314 * The new pmap ensures that page-tables are always mapping Write-Thru. 315 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 316 * on every change. 317 * 318 * Unfortunately, not all CPUs have a write-through cache mode. So we 319 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 320 * and if there is the chance for PTE syncs to be needed, we define 321 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 322 * the code. 323 */ 324 extern int pmap_needs_pte_sync; 325 326 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 327 #define PMAP_INCLUDE_PTE_SYNC 328 329 #define PTE_SYNC(pte) \ 330 do { \ 331 if (PMAP_NEEDS_PTE_SYNC) { \ 332 paddr_t pa; \ 333 cpu_drain_writebuf(); \ 334 cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\ 335 if (cpu_sdcache_enabled()) { \ 336 (void)pmap_extract(pmap_kernel(), (vaddr_t)(pte), &pa); \ 337 cpu_sdcache_wb_range((vaddr_t)(pte), (paddr_t)(pa), \ 338 sizeof(pt_entry_t)); \ 339 }; \ 340 cpu_drain_writebuf(); \ 341 } \ 342 } while (/*CONSTCOND*/0) 343 344 #define PTE_SYNC_RANGE(pte, cnt) \ 345 do { \ 346 if (PMAP_NEEDS_PTE_SYNC) { \ 347 paddr_t pa; \ 348 cpu_drain_writebuf(); \ 349 cpu_dcache_wb_range((vaddr_t)(pte), \ 350 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 351 if (cpu_sdcache_enabled()) { \ 352 (void)pmap_extract(pmap_kernel(), (vaddr_t)(pte), &pa);\ 353 cpu_sdcache_wb_range((vaddr_t)(pte), (paddr_t)(pa), \ 354 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 355 }; \ 356 cpu_drain_writebuf(); \ 357 } \ 358 } while (/*CONSTCOND*/0) 359 360 #define l1pte_valid(pde) (((pde) & L1_TYPE_MASK) != L1_TYPE_INV) 361 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 362 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 363 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 364 365 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 366 #define l2pte_valid(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 367 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 368 #define l2pte_minidata(pte) (((pte) & \ 369 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 370 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 371 372 /* L1 and L2 page table macros */ 373 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 374 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 375 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 376 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 377 378 /* Size of the kernel part of the L1 page table */ 379 #define KERNEL_PD_SIZE \ 380 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 381 382 /************************* ARM MMU configuration *****************************/ 383 384 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V7) != 0 385 void pmap_copy_page_generic(struct vm_page *, struct vm_page *); 386 void pmap_zero_page_generic(struct vm_page *); 387 388 void pmap_pte_init_generic(void); 389 #if defined(CPU_ARM8) 390 void pmap_pte_init_arm8(void); 391 #endif 392 #if defined(CPU_ARM9) 393 void pmap_pte_init_arm9(void); 394 #endif /* CPU_ARM9 */ 395 #if defined(CPU_ARM10) 396 void pmap_pte_init_arm10(void); 397 #endif /* CPU_ARM10 */ 398 #if defined(CPU_ARM11) 399 void pmap_pte_init_arm11(void); 400 #endif /* CPU_ARM11 */ 401 #if defined(CPU_ARMv7) 402 void pmap_pte_init_armv7(void); 403 #endif /* CPU_ARMv7 */ 404 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V7) != 0 */ 405 406 #if ARM_MMU_SA1 == 1 407 void pmap_pte_init_sa1(void); 408 #endif /* ARM_MMU_SA1 == 1 */ 409 410 #if ARM_MMU_V7 == 1 411 void pmap_pte_init_v7(void); 412 #endif /* ARM_MMU_V7 == 1 */ 413 414 #if ARM_MMU_XSCALE == 1 415 void pmap_copy_page_xscale(struct vm_page *, struct vm_page *); 416 void pmap_zero_page_xscale(struct vm_page *); 417 418 void pmap_pte_init_xscale(void); 419 420 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 421 422 #define PMAP_UAREA(va) pmap_uarea(va) 423 void pmap_uarea(vaddr_t); 424 #endif /* ARM_MMU_XSCALE == 1 */ 425 426 extern pt_entry_t pte_l1_s_cache_mode; 427 extern pt_entry_t pte_l1_s_cache_mask; 428 429 extern pt_entry_t pte_l2_l_cache_mode; 430 extern pt_entry_t pte_l2_l_cache_mask; 431 432 extern pt_entry_t pte_l2_s_cache_mode; 433 extern pt_entry_t pte_l2_s_cache_mask; 434 435 extern pt_entry_t pte_l1_s_cache_mode_pt; 436 extern pt_entry_t pte_l2_l_cache_mode_pt; 437 extern pt_entry_t pte_l2_s_cache_mode_pt; 438 439 extern pt_entry_t pte_l1_s_coherent; 440 extern pt_entry_t pte_l2_l_coherent; 441 extern pt_entry_t pte_l2_s_coherent; 442 443 extern pt_entry_t pte_l2_s_prot_ur; 444 extern pt_entry_t pte_l2_s_prot_uw; 445 extern pt_entry_t pte_l2_s_prot_kr; 446 extern pt_entry_t pte_l2_s_prot_kw; 447 extern pt_entry_t pte_l2_s_prot_mask; 448 449 extern pt_entry_t pte_l1_s_proto; 450 extern pt_entry_t pte_l1_c_proto; 451 extern pt_entry_t pte_l2_s_proto; 452 453 extern void (*pmap_copy_page_func)(struct vm_page *, struct vm_page *); 454 extern void (*pmap_zero_page_func)(struct vm_page *); 455 456 #endif /* !_LOCORE */ 457 458 /*****************************************************************************/ 459 460 /* 461 * Definitions for MMU domains 462 */ 463 #define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */ 464 #define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */ 465 #define PMAP_DOMAIN_USER_V7 0 /* V7 Userland uses a single domain */ 466 467 /* 468 * These macros define the various bit masks in the PTE. 469 * 470 * We use these macros since we use different bits on different processor 471 * models. 472 */ 473 #define L1_S_PROT_U (L1_S_AP(AP_U)) 474 #define L1_S_PROT_W (L1_S_AP(AP_W)) 475 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 476 477 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 478 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)) 479 #define L1_S_CACHE_MASK_v7 (L1_S_B|L1_S_C|L1_S_V7_TEX_MASK) 480 481 #define L1_S_COHERENT_generic (L1_S_B|L1_S_C) 482 #define L1_S_COHERENT_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)) 483 #define L1_S_COHERENT_v7 (L1_S_C|L1_S_V7_TEX_MASK) 484 485 #define L2_L_PROT_KR (L2_AP(0)) 486 #define L2_L_PROT_UR (L2_AP(AP_U)) 487 #define L2_L_PROT_KW (L2_AP(AP_W)) 488 #define L2_L_PROT_UW (L2_AP(AP_U|AP_W)) 489 #define L2_L_PROT_MASK (L2_AP(AP_U|AP_W)) 490 491 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 492 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X)) 493 #define L2_L_CACHE_MASK_v7 (L2_B|L2_C|L2_V7_L_TEX_MASK) 494 495 #define L2_L_COHERENT_generic (L2_B|L2_C) 496 #define L2_L_COHERENT_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X)) 497 #define L2_L_COHERENT_v7 (L2_C|L2_V7_L_TEX_MASK) 498 499 #define L2_S_PROT_UR_generic (L2_AP(AP_U)) 500 #define L2_S_PROT_UW_generic (L2_AP(AP_U|AP_W)) 501 #define L2_S_PROT_KR_generic (L2_AP(0)) 502 #define L2_S_PROT_KW_generic (L2_AP(AP_W)) 503 #define L2_S_PROT_MASK_generic (L2_AP(AP_U|AP_W)) 504 505 #define L2_S_PROT_UR_xscale (L2_AP0(AP_U)) 506 #define L2_S_PROT_UW_xscale (L2_AP0(AP_U|AP_W)) 507 #define L2_S_PROT_KR_xscale (L2_AP0(0)) 508 #define L2_S_PROT_KW_xscale (L2_AP0(AP_W)) 509 #define L2_S_PROT_MASK_xscale (L2_AP0(AP_U|AP_W)) 510 511 #define L2_S_PROT_UR_v7 (L2_V7_AP(AP_KRWUR)) 512 #define L2_S_PROT_UW_v7 (L2_V7_AP(AP_KRWURW)) 513 #define L2_S_PROT_KR_v7 (L2_V7_AP(AP_V7_KR)) 514 #define L2_S_PROT_KW_v7 (L2_V7_AP(AP_KRW)) 515 #define L2_S_PROT_MASK_v7 (L2_V7_AP(0x07) | L2_V7_S_XN) 516 517 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 518 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)) 519 #define L2_S_CACHE_MASK_v7 (L2_B|L2_C|L2_V7_S_TEX_MASK) 520 521 #define L2_S_COHERENT_generic (L2_B|L2_C) 522 #define L2_S_COHERENT_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)) 523 #define L2_S_COHERENT_v7 (L2_C|L2_V7_S_TEX_MASK) 524 525 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 526 #define L1_S_PROTO_xscale (L1_TYPE_S) 527 #define L1_S_PROTO_v7 (L1_TYPE_S) 528 529 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 530 #define L1_C_PROTO_xscale (L1_TYPE_C) 531 #define L1_C_PROTO_v7 (L1_TYPE_C) 532 533 #define L2_L_PROTO (L2_TYPE_L) 534 535 #define L2_S_PROTO_generic (L2_TYPE_S) 536 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 537 #define L2_S_PROTO_v7 (L2_TYPE_S) 538 539 /* 540 * User-visible names for the ones that vary with MMU class. 541 */ 542 543 #if ARM_NMMUS > 1 544 /* More than one MMU class configured; use variables. */ 545 #define L2_S_PROT_UR pte_l2_s_prot_ur 546 #define L2_S_PROT_UW pte_l2_s_prot_uw 547 #define L2_S_PROT_KR pte_l2_s_prot_kr 548 #define L2_S_PROT_KW pte_l2_s_prot_kw 549 #define L2_S_PROT_MASK pte_l2_s_prot_mask 550 551 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 552 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 553 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 554 555 #define L1_S_COHERENT pte_l1_s_coherent 556 #define L2_L_COHERENT pte_l2_l_coherent 557 #define L2_S_COHERENT pte_l2_s_coherent 558 559 #define L1_S_PROTO pte_l1_s_proto 560 #define L1_C_PROTO pte_l1_c_proto 561 #define L2_S_PROTO pte_l2_s_proto 562 563 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 564 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 565 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 566 #define L2_S_PROT_UR L2_S_PROT_UR_generic 567 #define L2_S_PROT_UW L2_S_PROT_UW_generic 568 #define L2_S_PROT_KR L2_S_PROT_KR_generic 569 #define L2_S_PROT_KW L2_S_PROT_KW_generic 570 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 571 572 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 573 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 574 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 575 576 #define L1_S_COHERENT L1_S_COHERENT_generic 577 #define L2_L_COHERENT L2_L_COHERENT_generic 578 #define L2_S_COHERENT L2_S_COHERENT_generic 579 580 #define L1_S_PROTO L1_S_PROTO_generic 581 #define L1_C_PROTO L1_C_PROTO_generic 582 #define L2_S_PROTO L2_S_PROTO_generic 583 584 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 585 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 586 #elif ARM_MMU_XSCALE == 1 587 #define L2_S_PROT_UR L2_S_PROT_UR_xscale 588 #define L2_S_PROT_UW L2_S_PROT_UW_xscale 589 #define L2_S_PROT_KR L2_S_PROT_KR_xscale 590 #define L2_S_PROT_KW L2_S_PROT_KW_xscale 591 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 592 593 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 594 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 595 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 596 597 #define L1_S_COHERENT L1_S_COHERENT_xscale 598 #define L2_L_COHERENT L2_L_COHERENT_xscale 599 #define L2_S_COHERENT L2_S_COHERENT_xscale 600 601 #define L1_S_PROTO L1_S_PROTO_xscale 602 #define L1_C_PROTO L1_C_PROTO_xscale 603 #define L2_S_PROTO L2_S_PROTO_xscale 604 605 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 606 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 607 #elif ARM_MMU_V7 == 1 608 #define L2_S_PROT_UR L2_S_PROT_UR_v7 609 #define L2_S_PROT_UW L2_S_PROT_UW_v7 610 #define L2_S_PROT_KR L2_S_PROT_KR_v7 611 #define L2_S_PROT_KW L2_S_PROT_KW_v7 612 #define L2_S_PROT_MASK L2_S_PROT_MASK_v7 613 614 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_v7 615 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_v7 616 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_v7 617 618 #define L1_S_COHERENT L1_S_COHERENT_v7 619 #define L2_L_COHERENT L2_L_COHERENT_v7 620 #define L2_S_COHERENT L2_S_COHERENT_v7 621 622 #define L1_S_PROTO L1_S_PROTO_v7 623 #define L1_C_PROTO L1_C_PROTO_v7 624 #define L2_S_PROTO L2_S_PROTO_v7 625 626 #define pmap_copy_page(s, d) pmap_copy_page_v7((s), (d)) 627 #define pmap_zero_page(d) pmap_zero_page_v7((d)) 628 #endif /* ARM_NMMUS > 1 */ 629 630 /* 631 * These macros return various bits based on kernel/user and protection. 632 * Note that the compiler will usually fold these at compile time. 633 */ 634 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 635 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 636 637 #ifndef _LOCORE 638 static __inline pt_entry_t 639 L2_L_PROT(int ku, vm_prot_t pr) 640 { 641 pt_entry_t pte; 642 643 if (ku == PTE_USER) 644 pte = (pr & VM_PROT_WRITE) ? L2_L_PROT_UW : L2_L_PROT_UR; 645 else 646 pte = (pr & VM_PROT_WRITE) ? L2_L_PROT_KW : L2_L_PROT_KR; 647 /* 648 * If we set the XN bit, the abort handlers or the vector page 649 * might be marked as such. Needs Debugging. 650 */ 651 /* 652 if ((pr & VM_PROT_EXECUTE) == 0) 653 pte |= L2_V7_L_XN; 654 */ 655 656 return pte; 657 } 658 static __inline pt_entry_t 659 L2_S_PROT(int ku, vm_prot_t pr) 660 { 661 pt_entry_t pte; 662 663 if (ku == PTE_USER) 664 pte = (pr & VM_PROT_WRITE) ? L2_S_PROT_UW : L2_S_PROT_UR; 665 else 666 pte = (pr & VM_PROT_WRITE) ? L2_S_PROT_KW : L2_S_PROT_KR; 667 /* 668 * If we set the XN bit, the abort handlers or the vector page 669 * might be marked as such. Needs Debugging. 670 */ 671 /* 672 if ((pr & VM_PROT_EXECUTE) == 0) 673 pte |= L2_V7_S_XN; 674 */ 675 676 return pte; 677 } 678 679 static __inline boolean_t 680 l2pte_is_writeable(pt_entry_t pte, struct pmap *pm) 681 { 682 /* XXX use of L2_V7_S_XN */ 683 return (pte & L2_S_PROT_MASK & ~L2_V7_S_XN) == 684 L2_S_PROT(pm == pmap_kernel() ? PTE_KERNEL : PTE_USER, 685 VM_PROT_WRITE); 686 } 687 #endif 688 689 /* 690 * Macros to test if a mapping is mappable with an L1 Section mapping 691 * or an L2 Large Page mapping. 692 */ 693 #define L1_S_MAPPABLE_P(va, pa, size) \ 694 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 695 696 #define L2_L_MAPPABLE_P(va, pa, size) \ 697 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 698 699 #ifndef _LOCORE 700 /* pmap_prefer bits for VIPT ARMv7 */ 701 #define PMAP_PREFER(fo, ap) pmap_prefer((fo), (ap)) 702 vaddr_t pmap_prefer(vaddr_t, vaddr_t); 703 704 extern uint32_t pmap_alias_dist; 705 extern uint32_t pmap_alias_bits; 706 707 /* pmap prefer alias alignment. */ 708 #define PMAP_PREFER_ALIGN() (pmap_alias_dist) 709 /* pmap prefer offset withing alignment. */ 710 #define PMAP_PREFER_OFFSET(of) \ 711 (PMAP_PREFER_ALIGN() == 0 ? 0 : ((of) & (PMAP_PREFER_ALIGN() - 1))) 712 713 714 #endif /* _LOCORE */ 715 716 #endif /* _KERNEL */ 717 718 #ifndef _LOCORE 719 /* 720 * pmap-specific data store in the vm_page structure. 721 */ 722 struct vm_page_md { 723 struct pv_entry *pvh_list; /* pv_entry list */ 724 struct simplelock pvh_slock; /* lock on this head */ 725 int pvh_attrs; /* page attributes */ 726 u_int uro_mappings; 727 u_int urw_mappings; 728 union { 729 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 730 u_int i_mappings; 731 } k_u; 732 #define kro_mappings k_u.s_mappings[0] 733 #define krw_mappings k_u.s_mappings[1] 734 #define k_mappings k_u.i_mappings 735 }; 736 737 #define VM_MDPAGE_INIT(pg) \ 738 do { \ 739 (pg)->mdpage.pvh_list = NULL; \ 740 simple_lock_init(&(pg)->mdpage.pvh_slock); \ 741 (pg)->mdpage.pvh_attrs = 0; \ 742 (pg)->mdpage.uro_mappings = 0; \ 743 (pg)->mdpage.urw_mappings = 0; \ 744 (pg)->mdpage.k_mappings = 0; \ 745 } while (/*CONSTCOND*/0) 746 #endif /* _LOCORE */ 747 748 #endif /* _ARM_PMAP_H_ */ 749