1 /* $OpenBSD: pmap.h,v 1.21 2011/11/05 18:11:26 miod Exp $ */ 2 /* $NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $ */ 3 4 /* 5 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 6 * All rights reserved. 7 * 8 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed for the NetBSD Project by 21 * Wasabi Systems, Inc. 22 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1994,1995 Mark Brinicombe. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Mark Brinicombe 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 #ifndef _ARM_PMAP_H_ 70 #define _ARM_PMAP_H_ 71 72 #ifdef _KERNEL 73 74 #include <arm/cpuconf.h> 75 #include <arm/pte.h> 76 #ifndef _LOCORE 77 #include <arm/cpufunc.h> 78 #endif 79 80 /* 81 * a pmap describes a processes' 4GB virtual address space. this 82 * virtual address space can be broken up into 4096 1MB regions which 83 * are described by L1 PTEs in the L1 table. 84 * 85 * There is a line drawn at KERNEL_BASE. Everything below that line 86 * changes when the VM context is switched. Everything above that line 87 * is the same no matter which VM context is running. This is achieved 88 * by making the L1 PTEs for those slots above KERNEL_BASE reference 89 * kernel L2 tables. 90 * 91 * The basic layout of the virtual address space thus looks like this: 92 * 93 * 0xffffffff 94 * . 95 * . 96 * . 97 * KERNEL_BASE 98 * -------------------- 99 * . 100 * . 101 * . 102 * 0x00000000 103 */ 104 105 /* 106 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 107 * A bucket size of 16 provides for 16MB of contiguous virtual address 108 * space per l2_dtable. Most processes will, therefore, require only two or 109 * three of these to map their whole working set. 110 */ 111 #define L2_BUCKET_LOG2 4 112 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 113 114 /* 115 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 116 * of l2_dtable structures required to track all possible page descriptors 117 * mappable by an L1 translation table is given by the following constants: 118 */ 119 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 120 #define L2_SIZE (1 << L2_LOG2) 121 122 #ifndef _LOCORE 123 124 struct l1_ttable; 125 struct l2_dtable; 126 127 /* 128 * Track cache/tlb occupancy using the following structure 129 */ 130 union pmap_cache_state { 131 struct { 132 union { 133 u_int8_t csu_cache_b[2]; 134 u_int16_t csu_cache; 135 } cs_cache_u; 136 137 union { 138 u_int8_t csu_tlb_b[2]; 139 u_int16_t csu_tlb; 140 } cs_tlb_u; 141 } cs_s; 142 u_int32_t cs_all; 143 }; 144 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 145 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 146 #define cs_cache cs_s.cs_cache_u.csu_cache 147 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 148 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 149 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 150 151 /* 152 * Assigned to cs_all to force cacheops to work for a particular pmap 153 */ 154 #define PMAP_CACHE_STATE_ALL 0xffffffffu 155 156 /* 157 * This structure is used by machine-dependent code to describe 158 * static mappings of devices, created at bootstrap time. 159 */ 160 struct pmap_devmap { 161 vaddr_t pd_va; /* virtual address */ 162 paddr_t pd_pa; /* physical address */ 163 psize_t pd_size; /* size of region */ 164 vm_prot_t pd_prot; /* protection code */ 165 int pd_cache; /* cache attributes */ 166 }; 167 168 /* 169 * The pmap structure itself 170 */ 171 struct pmap { 172 u_int8_t pm_domain; 173 boolean_t pm_remove_all; 174 struct l1_ttable *pm_l1; 175 union pmap_cache_state pm_cstate; 176 u_int pm_refs; 177 simple_lock_data_t pm_lock; 178 struct l2_dtable *pm_l2[L2_SIZE]; 179 struct pmap_statistics pm_stats; 180 }; 181 182 typedef struct pmap *pmap_t; 183 184 /* 185 * Physical / virtual address structure. In a number of places (particularly 186 * during bootstrapping) we need to keep track of the physical and virtual 187 * addresses of various pages 188 */ 189 typedef struct pv_addr { 190 SLIST_ENTRY(pv_addr) pv_list; 191 paddr_t pv_pa; 192 vaddr_t pv_va; 193 } pv_addr_t; 194 195 /* 196 * Determine various modes for PTEs (user vs. kernel, cacheable 197 * vs. non-cacheable). 198 */ 199 #define PTE_KERNEL 0 200 #define PTE_USER 1 201 #define PTE_NOCACHE 0 202 #define PTE_CACHE 1 203 #define PTE_PAGETABLE 2 204 205 /* 206 * Flags that indicate attributes of pages or mappings of pages. 207 * 208 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 209 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 210 * pv_entry's for each page. They live in the same "namespace" so 211 * that we can clear multiple attributes at a time. 212 * 213 * Note the "non-cacheable" flag generally means the page has 214 * multiple mappings in a given address space. 215 */ 216 #define PVF_MOD 0x01 /* page is modified */ 217 #define PVF_REF 0x02 /* page is referenced */ 218 #define PVF_WIRED 0x04 /* mapping is wired */ 219 #define PVF_WRITE 0x08 /* mapping is writable */ 220 #define PVF_EXEC 0x10 /* mapping is executable */ 221 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 222 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 223 #define PVF_NC (PVF_UNC|PVF_KNC) 224 225 /* 226 * Commonly referenced structures 227 */ 228 extern struct pmap kernel_pmap_store; 229 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 230 231 /* 232 * Macros that we need to export 233 */ 234 #define pmap_kernel() (&kernel_pmap_store) 235 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 236 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 237 238 #define pmap_is_modified(pg) \ 239 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 240 #define pmap_is_referenced(pg) \ 241 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 242 243 #define pmap_deactivate(p) do { /* nothing */ } while (0) 244 #define pmap_copy(dp, sp, da, l, sa) do { /* nothing */ } while (0) 245 246 #define pmap_unuse_final(p) do { /* nothing */ } while (0) 247 #define pmap_remove_holes(map) do { /* nothing */ } while (0) 248 249 /* 250 * Functions that we need to export 251 */ 252 void pmap_remove_all(pmap_t); 253 void pmap_uncache_page(paddr_t, vaddr_t); 254 255 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 256 257 /* Functions we use internally. */ 258 void pmap_bootstrap(pd_entry_t *, vaddr_t, vaddr_t); 259 260 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 261 boolean_t pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 262 boolean_t pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 263 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 264 265 void pmap_debug(int); 266 void pmap_postinit(void); 267 268 void vector_page_setprot(int); 269 270 /* XXX */ 271 void pmap_kenter_cache(vaddr_t va, paddr_t pa, vm_prot_t prot, int cacheable); 272 273 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 274 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 275 276 /* Bootstrapping routines. */ 277 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 278 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 279 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 280 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 281 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 282 void pmap_devmap_register(const struct pmap_devmap *); 283 284 /* 285 * Special page zero routine for use by the idle loop (no cache cleans). 286 */ 287 boolean_t pmap_pageidlezero(struct vm_page *); 288 #define PMAP_PAGEIDLEZERO(pg) pmap_pageidlezero((pg)) 289 290 /* 291 * The current top of kernel VM 292 */ 293 extern vaddr_t pmap_curmaxkvaddr; 294 295 /* 296 * Useful macros and constants 297 */ 298 299 /* Virtual address to page table entry */ 300 static __inline pt_entry_t * 301 vtopte(vaddr_t va) 302 { 303 pd_entry_t *pdep; 304 pt_entry_t *ptep; 305 306 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 307 return (NULL); 308 return (ptep); 309 } 310 311 /* 312 * The new pmap ensures that page-tables are always mapping Write-Thru. 313 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 314 * on every change. 315 * 316 * Unfortunately, not all CPUs have a write-through cache mode. So we 317 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 318 * and if there is the chance for PTE syncs to be needed, we define 319 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 320 * the code. 321 */ 322 extern int pmap_needs_pte_sync; 323 324 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 325 #define PMAP_INCLUDE_PTE_SYNC 326 327 #define PTE_SYNC(pte) \ 328 do { \ 329 if (PMAP_NEEDS_PTE_SYNC) \ 330 cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\ 331 } while (/*CONSTCOND*/0) 332 333 #define PTE_SYNC_RANGE(pte, cnt) \ 334 do { \ 335 if (PMAP_NEEDS_PTE_SYNC) { \ 336 cpu_dcache_wb_range((vaddr_t)(pte), \ 337 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 338 } \ 339 } while (/*CONSTCOND*/0) 340 341 #define l1pte_valid(pde) ((pde) != 0) 342 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 343 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 344 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 345 346 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 347 #define l2pte_valid(pte) ((pte) != 0) 348 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 349 #define l2pte_minidata(pte) (((pte) & \ 350 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 351 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 352 353 /* L1 and L2 page table macros */ 354 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 355 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 356 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 357 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 358 359 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 360 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 361 362 /* Size of the kernel part of the L1 page table */ 363 #define KERNEL_PD_SIZE \ 364 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 365 366 /************************* ARM MMU configuration *****************************/ 367 368 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 369 void pmap_copy_page_generic(struct vm_page *, struct vm_page *); 370 void pmap_zero_page_generic(struct vm_page *); 371 372 void pmap_pte_init_generic(void); 373 #if defined(CPU_ARM8) 374 void pmap_pte_init_arm8(void); 375 #endif 376 #if defined(CPU_ARM9) 377 void pmap_pte_init_arm9(void); 378 #endif /* CPU_ARM9 */ 379 #if defined(CPU_ARM10) 380 void pmap_pte_init_arm10(void); 381 #endif /* CPU_ARM10 */ 382 #if defined(CPU_ARM11) 383 void pmap_pte_init_arm11(void); 384 #endif /* CPU_ARM11 */ 385 #if defined(CPU_ARMv7) 386 void pmap_pte_init_armv7(void); 387 #endif /* CPU_ARMv7 */ 388 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 389 390 #if ARM_MMU_SA1 == 1 391 void pmap_pte_init_sa1(void); 392 #endif /* ARM_MMU_SA1 == 1 */ 393 394 #if ARM_MMU_V7 == 1 395 void pmap_copy_page_v7(struct vm_page *, struct vm_page *); 396 void pmap_zero_page_v7(struct vm_page *); 397 398 void pmap_pte_init_v7(void); 399 #endif /* ARM_MMU_V7 == 1 */ 400 401 #if ARM_MMU_XSCALE == 1 402 void pmap_copy_page_xscale(struct vm_page *, struct vm_page *); 403 void pmap_zero_page_xscale(struct vm_page *); 404 405 void pmap_pte_init_xscale(void); 406 407 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 408 409 #define PMAP_UAREA(va) pmap_uarea(va) 410 void pmap_uarea(vaddr_t); 411 #endif /* ARM_MMU_XSCALE == 1 */ 412 413 extern pt_entry_t pte_l1_s_cache_mode; 414 extern pt_entry_t pte_l1_s_cache_mask; 415 416 extern pt_entry_t pte_l2_l_cache_mode; 417 extern pt_entry_t pte_l2_l_cache_mask; 418 419 extern pt_entry_t pte_l2_s_cache_mode; 420 extern pt_entry_t pte_l2_s_cache_mask; 421 422 extern pt_entry_t pte_l1_s_cache_mode_pt; 423 extern pt_entry_t pte_l2_l_cache_mode_pt; 424 extern pt_entry_t pte_l2_s_cache_mode_pt; 425 426 extern pt_entry_t pte_l2_s_prot_u; 427 extern pt_entry_t pte_l2_s_prot_w; 428 extern pt_entry_t pte_l2_s_prot_mask; 429 430 extern pt_entry_t pte_l1_s_proto; 431 extern pt_entry_t pte_l1_c_proto; 432 extern pt_entry_t pte_l2_s_proto; 433 434 extern void (*pmap_copy_page_func)(struct vm_page *, struct vm_page *); 435 extern void (*pmap_zero_page_func)(struct vm_page *); 436 437 #endif /* !_LOCORE */ 438 439 /*****************************************************************************/ 440 441 /* 442 * Definitions for MMU domains 443 */ 444 #define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */ 445 #define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */ 446 447 /* 448 * These macros define the various bit masks in the PTE. 449 * 450 * We use these macros since we use different bits on different processor 451 * models. 452 */ 453 #define L1_S_PROT_U (L1_S_AP(AP_U)) 454 #define L1_S_PROT_W (L1_S_AP(AP_W)) 455 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 456 457 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 458 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)) 459 #define L1_S_CACHE_MASK_v7 (L1_S_B|L1_S_C|L1_S_V7_TEX(TEX_V7_X)) 460 461 #define L2_L_PROT_U (L2_AP(AP_U)) 462 #define L2_L_PROT_W (L2_AP(AP_W)) 463 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 464 465 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 466 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X)) 467 #define L2_L_CACHE_MASK_v7 (L2_B|L2_C|L2_V7_L_TEX(TEX_V7_X)) 468 469 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 470 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 471 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 472 473 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 474 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 475 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 476 477 #define L2_S_PROT_U_v7 (L2_AP0(AP_U)) 478 #define L2_S_PROT_W_v7 (L2_AP0(AP_W)) 479 #define L2_S_PROT_MASK_v7 (L2_S_PROT_U|L2_S_PROT_W) 480 481 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 482 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)) 483 #define L2_S_CACHE_MASK_v7 (L2_B|L2_C) 484 485 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 486 #define L1_S_PROTO_xscale (L1_TYPE_S) 487 #define L1_S_PROTO_v7 (L1_TYPE_S) 488 489 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 490 #define L1_C_PROTO_xscale (L1_TYPE_C) 491 #define L1_C_PROTO_v7 (L1_TYPE_C) 492 493 #define L2_L_PROTO (L2_TYPE_L) 494 495 #define L2_S_PROTO_generic (L2_TYPE_S) 496 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 497 #define L2_S_PROTO_v7 (L2_TYPE_S) 498 499 /* 500 * User-visible names for the ones that vary with MMU class. 501 */ 502 503 #if ARM_NMMUS > 1 504 /* More than one MMU class configured; use variables. */ 505 #define L2_S_PROT_U pte_l2_s_prot_u 506 #define L2_S_PROT_W pte_l2_s_prot_w 507 #define L2_S_PROT_MASK pte_l2_s_prot_mask 508 509 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 510 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 511 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 512 513 #define L1_S_PROTO pte_l1_s_proto 514 #define L1_C_PROTO pte_l1_c_proto 515 #define L2_S_PROTO pte_l2_s_proto 516 517 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 518 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 519 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 520 #define L2_S_PROT_U L2_S_PROT_U_generic 521 #define L2_S_PROT_W L2_S_PROT_W_generic 522 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 523 524 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 525 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 526 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 527 528 #define L1_S_PROTO L1_S_PROTO_generic 529 #define L1_C_PROTO L1_C_PROTO_generic 530 #define L2_S_PROTO L2_S_PROTO_generic 531 532 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 533 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 534 #elif ARM_MMU_XSCALE == 1 535 #define L2_S_PROT_U L2_S_PROT_U_xscale 536 #define L2_S_PROT_W L2_S_PROT_W_xscale 537 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 538 539 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 540 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 541 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 542 543 #define L1_S_PROTO L1_S_PROTO_xscale 544 #define L1_C_PROTO L1_C_PROTO_xscale 545 #define L2_S_PROTO L2_S_PROTO_xscale 546 547 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 548 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 549 #elif ARM_MMU_V7 == 1 550 #define L2_S_PROT_U L2_S_PROT_U_v7 551 #define L2_S_PROT_W L2_S_PROT_W_v7 552 #define L2_S_PROT_MASK L2_S_PROT_MASK_v7 553 554 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_v7 555 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_v7 556 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_v7 557 558 #define L1_S_PROTO L1_S_PROTO_v7 559 #define L1_C_PROTO L1_C_PROTO_v7 560 #define L2_S_PROTO L2_S_PROTO_v7 561 562 #define pmap_copy_page(s, d) pmap_copy_page_v7((s), (d)) 563 #define pmap_zero_page(d) pmap_zero_page_v7((d)) 564 #endif /* ARM_NMMUS > 1 */ 565 566 /* 567 * These macros return various bits based on kernel/user and protection. 568 * Note that the compiler will usually fold these at compile time. 569 */ 570 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 571 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 572 573 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 574 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 575 576 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 577 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 578 579 /* 580 * Macros to test if a mapping is mappable with an L1 Section mapping 581 * or an L2 Large Page mapping. 582 */ 583 #define L1_S_MAPPABLE_P(va, pa, size) \ 584 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 585 586 #define L2_L_MAPPABLE_P(va, pa, size) \ 587 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 588 589 #ifndef _LOCORE 590 /* pmap_prefer bits for VIPT ARMv7 */ 591 #define PMAP_PREFER(fo, ap) pmap_prefer((fo), (ap)) 592 vaddr_t pmap_prefer(vaddr_t, vaddr_t); 593 594 extern uint32_t pmap_alias_dist; 595 extern uint32_t pmap_alias_bits; 596 597 /* pmap prefer alias alignment. */ 598 #define PMAP_PREFER_ALIGN() (pmap_alias_dist) 599 /* pmap prefer offset withing alignment. */ 600 #define PMAP_PREFER_OFFSET(of) \ 601 (PMAP_PREFER_ALIGN() == 0 ? 0 : ((of) & (PMAP_PREFER_ALIGN() - 1))) 602 603 604 #endif /* _LOCORE */ 605 606 #endif /* _KERNEL */ 607 608 #endif /* _ARM_PMAP_H_ */ 609