xref: /openbsd-src/sys/arch/arm/include/pci_machdep.h (revision 919fac9de7a640c17e71e8b0559cc8916b92e9b1)
1*919fac9dSkettenis /*	$OpenBSD: pci_machdep.h,v 1.18 2022/01/06 08:46:50 kettenis Exp $ */
2e1e4f5b1Sdrahn 
3e1e4f5b1Sdrahn /*
4b00e6b02Spatrick  * Copyright (c) 2003-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
5e1e4f5b1Sdrahn  *
6b00e6b02Spatrick  * Redistribution and use in source and binary forms, with or without
7b00e6b02Spatrick  * modification, are permitted provided that the following conditions
8b00e6b02Spatrick  * are met:
9b00e6b02Spatrick  * 1. Redistributions of source code must retain the above copyright
10b00e6b02Spatrick  *    notice, this list of conditions and the following disclaimer.
11b00e6b02Spatrick  * 2. Redistributions in binary form must reproduce the above copyright
12b00e6b02Spatrick  *    notice, this list of conditions and the following disclaimer in the
13b00e6b02Spatrick  *    documentation and/or other materials provided with the distribution.
14e1e4f5b1Sdrahn  *
15b00e6b02Spatrick  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
16b00e6b02Spatrick  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17b00e6b02Spatrick  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18b00e6b02Spatrick  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19b00e6b02Spatrick  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20b00e6b02Spatrick  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21b00e6b02Spatrick  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22b00e6b02Spatrick  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23b00e6b02Spatrick  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24b00e6b02Spatrick  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25b00e6b02Spatrick  * SUCH DAMAGE.
26e1e4f5b1Sdrahn  *
27e1e4f5b1Sdrahn  */
28e1e4f5b1Sdrahn 
29e1e4f5b1Sdrahn typedef struct arm32_pci_chipset *pci_chipset_tag_t;
30*919fac9dSkettenis typedef uint64_t pcitag_t;
31*919fac9dSkettenis 
32*919fac9dSkettenis #define PCITAG_NODE(x)		((x) >> 32)
33*919fac9dSkettenis #define PCITAG_OFFSET(x)	((x) & 0xffffffff)
34*919fac9dSkettenis 
35e1e4f5b1Sdrahn typedef u_long pci_intr_handle_t;
36e1e4f5b1Sdrahn 
37e1e4f5b1Sdrahn struct pci_attach_args;
38e1e4f5b1Sdrahn 
39e1e4f5b1Sdrahn /*
40e1e4f5b1Sdrahn  * arm32-specific PCI structure and type definitions.
41e1e4f5b1Sdrahn  * NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
42e1e4f5b1Sdrahn  */
43e1e4f5b1Sdrahn struct arm32_pci_chipset {
44e1e4f5b1Sdrahn 	void		*pc_conf_v;
45e1e4f5b1Sdrahn 	void		(*pc_attach_hook)(struct device *,
46e1e4f5b1Sdrahn 			    struct device *, struct pcibus_attach_args *);
47e1e4f5b1Sdrahn 	int		(*pc_bus_maxdevs)(void *, int);
48e1e4f5b1Sdrahn 	pcitag_t	(*pc_make_tag)(void *, int, int, int);
49e1e4f5b1Sdrahn 	void		(*pc_decompose_tag)(void *, pcitag_t, int *,
50e1e4f5b1Sdrahn 			    int *, int *);
51b1926db3Smiod 	int		(*pc_conf_size)(void *, pcitag_t);
52e1e4f5b1Sdrahn 	pcireg_t	(*pc_conf_read)(void *, pcitag_t, int);
53e1e4f5b1Sdrahn 	void		(*pc_conf_write)(void *, pcitag_t, int, pcireg_t);
54619b146dSpatrick 	int		(*pc_probe_device_hook)(void *, struct pci_attach_args *);
55e1e4f5b1Sdrahn 
56e1e4f5b1Sdrahn 	void		*pc_intr_v;
57e1e4f5b1Sdrahn 	int		(*pc_intr_map)(struct pci_attach_args *,
58e1e4f5b1Sdrahn 			    pci_intr_handle_t *);
59b00e6b02Spatrick 	int		(*pc_intr_map_msi)(struct pci_attach_args *,
60b00e6b02Spatrick 			    pci_intr_handle_t *);
61b00e6b02Spatrick 	int		(*pc_intr_map_msix)(struct pci_attach_args *,
62b00e6b02Spatrick 			    int, pci_intr_handle_t *);
63e1e4f5b1Sdrahn 	const char	*(*pc_intr_string)(void *, pci_intr_handle_t);
64e1e4f5b1Sdrahn 	void		*(*pc_intr_establish)(void *, pci_intr_handle_t,
65d67371fdSpatrick 			    int, struct cpu_info *, int (*)(void *), void *,
66d67371fdSpatrick 			    char *);
67e1e4f5b1Sdrahn 	void		(*pc_intr_disestablish)(void *, void *);
68e1e4f5b1Sdrahn };
69e1e4f5b1Sdrahn 
70e1e4f5b1Sdrahn /*
71e1e4f5b1Sdrahn  * Functions provided to machine-independent PCI code.
72e1e4f5b1Sdrahn  */
73e1e4f5b1Sdrahn #define	pci_attach_hook(p, s, pba)					\
74e1e4f5b1Sdrahn     (*(pba)->pba_pc->pc_attach_hook)((p), (s), (pba))
75e1e4f5b1Sdrahn #define	pci_bus_maxdevs(c, b)						\
76e1e4f5b1Sdrahn     (*(c)->pc_bus_maxdevs)((c)->pc_conf_v, (b))
77e1e4f5b1Sdrahn #define	pci_make_tag(c, b, d, f)					\
78e1e4f5b1Sdrahn     (*(c)->pc_make_tag)((c)->pc_conf_v, (b), (d), (f))
79e1e4f5b1Sdrahn #define	pci_decompose_tag(c, t, bp, dp, fp)				\
80e1e4f5b1Sdrahn     (*(c)->pc_decompose_tag)((c)->pc_conf_v, (t), (bp), (dp), (fp))
81b1926db3Smiod #define	pci_conf_size(c, t)						\
82b1926db3Smiod     (*(c)->pc_conf_size)((c)->pc_conf_v, (t))
83e1e4f5b1Sdrahn #define	pci_conf_read(c, t, r)						\
84e1e4f5b1Sdrahn     (*(c)->pc_conf_read)((c)->pc_conf_v, (t), (r))
85e1e4f5b1Sdrahn #define	pci_conf_write(c, t, r, v)					\
86e1e4f5b1Sdrahn     (*(c)->pc_conf_write)((c)->pc_conf_v, (t), (r), (v))
87619b146dSpatrick #define	pci_probe_device_hook(c, a)					\
88619b146dSpatrick     (*(c)->pc_probe_device_hook)((c)->pc_conf_v, (a))
89b00e6b02Spatrick #define	pci_intr_map(c, ihp)						\
90b00e6b02Spatrick     (*(c)->pa_pc->pc_intr_map)((c), (ihp))
91b00e6b02Spatrick #define	pci_intr_map_msi(c, ihp)					\
92b00e6b02Spatrick     (*(c)->pa_pc->pc_intr_map_msi)((c), (ihp))
93b00e6b02Spatrick #define	pci_intr_map_msix(c, vec, ihp)					\
94b00e6b02Spatrick     (*(c)->pa_pc->pc_intr_map_msix)((c), (vec), (ihp))
95e1e4f5b1Sdrahn #define	pci_intr_string(c, ih)						\
96e1e4f5b1Sdrahn     (*(c)->pc_intr_string)((c)->pc_intr_v, (ih))
97b00e6b02Spatrick #define	pci_intr_establish(c, ih, l, h, a, nm)				\
98d67371fdSpatrick     (*(c)->pc_intr_establish)((c)->pc_intr_v, (ih), (l), NULL, (h), (a),\
99d67371fdSpatrick 	(nm))
100d67371fdSpatrick #define	pci_intr_establish_cpu(c, ih, l, ci, h, a, nm)			\
101d67371fdSpatrick     (*(c)->pc_intr_establish)((c)->pc_intr_v, (ih), (l), (ci), (h), (a),\
102d67371fdSpatrick 	(nm))
103e1e4f5b1Sdrahn #define	pci_intr_disestablish(c, iv)					\
104e1e4f5b1Sdrahn     (*(c)->pc_intr_disestablish)((c)->pc_intr_v, (iv))
105ea14b1d7Sjordan 
1069a8f49f4Skettenis #define	pci_min_powerstate(c, t)	(PCI_PMCSR_STATE_D3)
10725b7ac45Smpi #define	pci_set_powerstate_md(c, t, s, p)
1089a8f49f4Skettenis 
109ea14b1d7Sjordan #define	pci_dev_postattach(a, b)
110