1 /* $OpenBSD: cpufunc.h,v 1.15 2014/03/29 18:09:28 guenther Exp $ */ 2 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 3 4 /* 5 * Copyright (c) 1997 Mark Brinicombe. 6 * Copyright (c) 1997 Causality Limited 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Causality Limited. 20 * 4. The name of Causality Limited may not be used to endorse or promote 21 * products derived from this software without specific prior written 22 * permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 25 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * RiscBSD kernel project 37 * 38 * cpufunc.h 39 * 40 * Prototypes for cpu, mmu and tlb related functions. 41 */ 42 43 #ifndef _ARM_CPUFUNC_H_ 44 #define _ARM_CPUFUNC_H_ 45 46 #ifdef _KERNEL 47 48 #include <sys/types.h> 49 #include <arm/cpuconf.h> 50 51 struct cpu_functions { 52 53 /* CPU functions */ 54 55 u_int (*cf_id) (void); 56 void (*cf_cpwait) (void); 57 58 /* MMU functions */ 59 60 u_int (*cf_control) (u_int bic, u_int eor); 61 void (*cf_domains) (u_int domains); 62 void (*cf_setttb) (u_int ttb); 63 u_int (*cf_dfsr) (void); 64 u_int (*cf_dfar) (void); 65 u_int (*cf_ifsr) (void); 66 u_int (*cf_ifar) (void); 67 68 /* TLB functions */ 69 70 void (*cf_tlb_flushID) (void); 71 void (*cf_tlb_flushID_SE) (u_int va); 72 void (*cf_tlb_flushI) (void); 73 void (*cf_tlb_flushI_SE) (u_int va); 74 void (*cf_tlb_flushD) (void); 75 void (*cf_tlb_flushD_SE) (u_int va); 76 77 /* 78 * Cache operations: 79 * 80 * We define the following primitives: 81 * 82 * icache_sync_all Synchronize I-cache 83 * icache_sync_range Synchronize I-cache range 84 * 85 * dcache_wbinv_all Write-back and Invalidate D-cache 86 * dcache_wbinv_range Write-back and Invalidate D-cache range 87 * dcache_inv_range Invalidate D-cache range 88 * dcache_wb_range Write-back D-cache range 89 * 90 * idcache_wbinv_all Write-back and Invalidate D-cache, 91 * Invalidate I-cache 92 * idcache_wbinv_range Write-back and Invalidate D-cache, 93 * Invalidate I-cache range 94 * 95 * Note that the ARM term for "write-back" is "clean". We use 96 * the term "write-back" since it's a more common way to describe 97 * the operation. 98 * 99 * There are some rules that must be followed: 100 * 101 * I-cache Synch (all or range): 102 * The goal is to synchronize the instruction stream, 103 * so you may beed to write-back dirty D-cache blocks 104 * first. If a range is requested, and you can't 105 * synchronize just a range, you have to hit the whole 106 * thing. 107 * 108 * D-cache Write-Back and Invalidate range: 109 * If you can't WB-Inv a range, you must WB-Inv the 110 * entire D-cache. 111 * 112 * D-cache Invalidate: 113 * If you can't Inv the D-cache, you must Write-Back 114 * and Invalidate. Code that uses this operation 115 * MUST NOT assume that the D-cache will not be written 116 * back to memory. 117 * 118 * D-cache Write-Back: 119 * If you can't Write-back without doing an Inv, 120 * that's fine. Then treat this as a WB-Inv. 121 * Skipping the invalidate is merely an optimization. 122 * 123 * All operations: 124 * Valid virtual addresses must be passed to each 125 * cache operation. 126 */ 127 void (*cf_icache_sync_all) (void); 128 void (*cf_icache_sync_range) (vaddr_t, vsize_t); 129 130 void (*cf_dcache_wbinv_all) (void); 131 void (*cf_dcache_wbinv_range) (vaddr_t, vsize_t); 132 void (*cf_dcache_inv_range) (vaddr_t, vsize_t); 133 void (*cf_dcache_wb_range) (vaddr_t, vsize_t); 134 135 void (*cf_idcache_wbinv_all) (void); 136 void (*cf_idcache_wbinv_range) (vaddr_t, vsize_t); 137 138 void (*cf_sdcache_wbinv_all) (void); 139 void (*cf_sdcache_wbinv_range) (vaddr_t, paddr_t, vsize_t); 140 void (*cf_sdcache_inv_range) (vaddr_t, paddr_t, vsize_t); 141 void (*cf_sdcache_wb_range) (vaddr_t, paddr_t, vsize_t); 142 143 /* Other functions */ 144 145 void (*cf_flush_prefetchbuf) (void); 146 void (*cf_drain_writebuf) (void); 147 148 void (*cf_sleep) (int mode); 149 150 /* Soft functions */ 151 void (*cf_context_switch) (u_int); 152 void (*cf_setup) (void); 153 }; 154 155 extern struct cpu_functions cpufuncs; 156 extern u_int cputype; 157 158 #define cpu_id() cpufuncs.cf_id() 159 #define cpu_cpwait() cpufuncs.cf_cpwait() 160 161 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 162 #define cpu_domains(d) cpufuncs.cf_domains(d) 163 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 164 #define cpu_dfsr() cpufuncs.cf_dfsr() 165 #define cpu_dfar() cpufuncs.cf_dfar() 166 #define cpu_ifsr() cpufuncs.cf_ifsr() 167 #define cpu_ifar() cpufuncs.cf_ifar() 168 169 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 170 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 171 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 172 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 173 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 174 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 175 176 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 177 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 178 179 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 180 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 181 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 182 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 183 184 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 185 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 186 187 #define cpu_sdcache_enabled() (cpufuncs.cf_sdcache_wbinv_all != cpufunc_nullop) 188 #define cpu_sdcache_wbinv_all() cpufuncs.cf_sdcache_wbinv_all() 189 #define cpu_sdcache_wbinv_range(va, pa, s) cpufuncs.cf_sdcache_wbinv_range((va), (pa), (s)) 190 #define cpu_sdcache_inv_range(va, pa, s) cpufuncs.cf_sdcache_inv_range((va), (pa), (s)) 191 #define cpu_sdcache_wb_range(va, pa, s) cpufuncs.cf_sdcache_wb_range((va), (pa), (s)) 192 193 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 194 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 195 196 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 197 198 #define cpu_context_switch(a) cpufuncs.cf_context_switch(a) 199 #define cpu_setup(a) cpufuncs.cf_setup(a) 200 201 int set_cpufuncs (void); 202 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 203 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 204 205 void cpufunc_nullop (void); 206 int early_abort_fixup (void *); 207 int late_abort_fixup (void *); 208 u_int cpufunc_id (void); 209 u_int cpufunc_control (u_int clear, u_int bic); 210 void cpufunc_domains (u_int domains); 211 u_int cpufunc_dfsr (void); 212 u_int cpufunc_dfar (void); 213 u_int cpufunc_ifsr (void); 214 u_int cpufunc_ifar (void); 215 216 #ifdef CPU_ARM8 217 void arm8_setttb (u_int ttb); 218 void arm8_tlb_flushID (void); 219 void arm8_tlb_flushID_SE (u_int va); 220 void arm8_cache_flushID (void); 221 void arm8_cache_flushID_E (u_int entry); 222 void arm8_cache_cleanID (void); 223 void arm8_cache_cleanID_E (u_int entry); 224 void arm8_cache_purgeID (void); 225 void arm8_cache_purgeID_E (u_int entry); 226 227 void arm8_cache_syncI (void); 228 void arm8_cache_cleanID_rng (vaddr_t start, vsize_t end); 229 void arm8_cache_cleanD_rng (vaddr_t start, vsize_t end); 230 void arm8_cache_purgeID_rng (vaddr_t start, vsize_t end); 231 void arm8_cache_purgeD_rng (vaddr_t start, vsize_t end); 232 void arm8_cache_syncI_rng (vaddr_t start, vsize_t end); 233 234 void arm8_context_switch (u_int); 235 236 void arm8_setup (void); 237 238 u_int arm8_clock_config (u_int, u_int); 239 #endif 240 241 #if defined(CPU_SA1100) || defined(CPU_SA1110) 242 void sa11x0_drain_readbuf (void); 243 244 void sa11x0_context_switch (u_int); 245 void sa11x0_cpu_sleep (int mode); 246 247 void sa11x0_setup (void); 248 #endif 249 250 #if defined(CPU_SA1100) || defined(CPU_SA1110) 251 void sa1_setttb (u_int ttb); 252 253 void sa1_tlb_flushID_SE (u_int va); 254 255 void sa1_cache_flushID (void); 256 void sa1_cache_flushI (void); 257 void sa1_cache_flushD (void); 258 void sa1_cache_flushD_SE (u_int entry); 259 260 void sa1_cache_cleanID (void); 261 void sa1_cache_cleanD (void); 262 void sa1_cache_cleanD_E (u_int entry); 263 264 void sa1_cache_purgeID (void); 265 void sa1_cache_purgeID_E (u_int entry); 266 void sa1_cache_purgeD (void); 267 void sa1_cache_purgeD_E (u_int entry); 268 269 void sa1_cache_syncI (void); 270 void sa1_cache_cleanID_rng (vaddr_t start, vsize_t end); 271 void sa1_cache_cleanD_rng (vaddr_t start, vsize_t end); 272 void sa1_cache_purgeID_rng (vaddr_t start, vsize_t end); 273 void sa1_cache_purgeD_rng (vaddr_t start, vsize_t end); 274 void sa1_cache_syncI_rng (vaddr_t start, vsize_t end); 275 276 #endif 277 278 #ifdef CPU_ARM9 279 void arm9_setttb (u_int); 280 281 void arm9_tlb_flushID_SE (u_int); 282 283 void arm9_icache_sync_all (void); 284 void arm9_icache_sync_range (vaddr_t, vsize_t); 285 286 void arm9_dcache_wbinv_all (void); 287 void arm9_dcache_wbinv_range (vaddr_t, vsize_t); 288 void arm9_dcache_inv_range (vaddr_t, vsize_t); 289 void arm9_dcache_wb_range (vaddr_t, vsize_t); 290 291 void arm9_idcache_wbinv_all (void); 292 void arm9_idcache_wbinv_range (vaddr_t, vsize_t); 293 294 void arm9_context_switch (u_int); 295 296 void arm9_setup (void); 297 298 extern unsigned arm9_dcache_sets_max; 299 extern unsigned arm9_dcache_sets_inc; 300 extern unsigned arm9_dcache_index_max; 301 extern unsigned arm9_dcache_index_inc; 302 #endif 303 304 #if defined(CPU_ARM9E) || defined(CPU_ARM10) 305 void arm10_tlb_flushID_SE (u_int); 306 void arm10_tlb_flushI_SE (u_int); 307 308 void arm10_context_switch (u_int); 309 310 void arm9e_setup (void); 311 void arm10_setup (void); 312 #endif 313 314 #if defined(CPU_ARM9E) || defined (CPU_ARM10) 315 void armv5_ec_setttb (u_int); 316 317 void armv5_ec_icache_sync_all (void); 318 void armv5_ec_icache_sync_range (vaddr_t, vsize_t); 319 320 void armv5_ec_dcache_wbinv_all (void); 321 void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t); 322 void armv5_ec_dcache_inv_range (vaddr_t, vsize_t); 323 void armv5_ec_dcache_wb_range (vaddr_t, vsize_t); 324 325 void armv5_ec_idcache_wbinv_all (void); 326 void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t); 327 #endif 328 329 #ifdef CPU_ARM11 330 void arm11_setttb (u_int); 331 332 void arm11_tlb_flushID_SE (u_int); 333 void arm11_tlb_flushI_SE (u_int); 334 335 void arm11_context_switch (u_int); 336 337 void arm11_setup (void); 338 void arm11_tlb_flushID (void); 339 void arm11_tlb_flushI (void); 340 void arm11_tlb_flushD (void); 341 void arm11_tlb_flushD_SE (u_int va); 342 343 void arm11_drain_writebuf (void); 344 void arm11_cpu_sleep (int mode); 345 #endif 346 347 348 #if defined (CPU_ARM10) || defined(CPU_ARM11) 349 void armv5_setttb (u_int); 350 351 void armv5_icache_sync_all (void); 352 void armv5_icache_sync_range (vaddr_t, vsize_t); 353 354 void armv5_dcache_wbinv_all (void); 355 void armv5_dcache_wbinv_range (vaddr_t, vsize_t); 356 void armv5_dcache_inv_range (vaddr_t, vsize_t); 357 void armv5_dcache_wb_range (vaddr_t, vsize_t); 358 359 void armv5_idcache_wbinv_all (void); 360 void armv5_idcache_wbinv_range (vaddr_t, vsize_t); 361 362 extern unsigned armv5_dcache_sets_max; 363 extern unsigned armv5_dcache_sets_inc; 364 extern unsigned armv5_dcache_index_max; 365 extern unsigned armv5_dcache_index_inc; 366 #endif 367 368 #ifdef CPU_ARMv7 369 void armv7_setttb (u_int); 370 371 void armv7_tlb_flushID_SE (u_int); 372 void armv7_tlb_flushI_SE (u_int); 373 374 void armv7_context_switch (u_int); 375 376 void armv7_setup (void); 377 void armv7_tlb_flushID (void); 378 void armv7_tlb_flushI (void); 379 void armv7_tlb_flushD (void); 380 void armv7_tlb_flushD_SE (u_int va); 381 382 void armv7_drain_writebuf (void); 383 void armv7_cpu_sleep (int mode); 384 385 u_int armv7_periphbase (void); 386 387 void armv7_icache_sync_all (void); 388 void armv7_icache_sync_range (vaddr_t, vsize_t); 389 390 void armv7_dcache_wbinv_all (void); 391 void armv7_dcache_wbinv_range (vaddr_t, vsize_t); 392 void armv7_dcache_inv_range (vaddr_t, vsize_t); 393 void armv7_dcache_wb_range (vaddr_t, vsize_t); 394 395 void armv7_idcache_wbinv_all (void); 396 void armv7_idcache_wbinv_range (vaddr_t, vsize_t); 397 398 extern unsigned armv7_dcache_sets_max; 399 extern unsigned armv7_dcache_sets_inc; 400 extern unsigned armv7_dcache_index_max; 401 extern unsigned armv7_dcache_index_inc; 402 #endif 403 404 405 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 406 defined(CPU_SA1100) || defined(CPU_SA1110) || \ 407 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 408 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 409 410 void armv4_tlb_flushID (void); 411 void armv4_tlb_flushI (void); 412 void armv4_tlb_flushD (void); 413 void armv4_tlb_flushD_SE (u_int va); 414 415 void armv4_drain_writebuf (void); 416 #endif 417 418 #if defined(CPU_IXP12X0) 419 void ixp12x0_drain_readbuf (void); 420 void ixp12x0_context_switch (u_int); 421 void ixp12x0_setup (void); 422 #endif 423 424 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 425 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 426 (ARM_MMU_XSCALE == 1) 427 void xscale_cpwait (void); 428 429 void xscale_cpu_sleep (int mode); 430 431 u_int xscale_control (u_int clear, u_int bic); 432 433 void xscale_setttb (u_int ttb); 434 435 void xscale_tlb_flushID_SE (u_int va); 436 437 void xscale_cache_flushID (void); 438 void xscale_cache_flushI (void); 439 void xscale_cache_flushD (void); 440 void xscale_cache_flushD_SE (u_int entry); 441 442 void xscale_cache_cleanID (void); 443 void xscale_cache_cleanD (void); 444 void xscale_cache_cleanD_E (u_int entry); 445 446 void xscale_cache_clean_minidata (void); 447 448 void xscale_cache_purgeID (void); 449 void xscale_cache_purgeID_E (u_int entry); 450 void xscale_cache_purgeD (void); 451 void xscale_cache_purgeD_E (u_int entry); 452 453 void xscale_cache_syncI (void); 454 void xscale_cache_cleanID_rng (vaddr_t start, vsize_t end); 455 void xscale_cache_cleanD_rng (vaddr_t start, vsize_t end); 456 void xscale_cache_purgeID_rng (vaddr_t start, vsize_t end); 457 void xscale_cache_purgeD_rng (vaddr_t start, vsize_t end); 458 void xscale_cache_syncI_rng (vaddr_t start, vsize_t end); 459 void xscale_cache_flushD_rng (vaddr_t start, vsize_t end); 460 461 void xscale_context_switch (u_int); 462 463 void xscale_setup (void); 464 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 465 466 #define tlb_flush cpu_tlb_flushID 467 #define setttb cpu_setttb 468 #define drain_writebuf cpu_drain_writebuf 469 470 /* 471 * Macros for manipulating CPU interrupts 472 */ 473 /* Functions to manipulate the CPSR. */ 474 static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor); 475 static __inline u_int32_t __get_cpsr(void); 476 477 static __inline u_int32_t 478 __set_cpsr_c(u_int bic, u_int eor) 479 { 480 u_int32_t tmp, ret; 481 482 __asm volatile( 483 "mrs %0, cpsr\n\t" /* Get the CPSR */ 484 "bic %1, %0, %2\n\t" /* Clear bits */ 485 "eor %1, %1, %3\n\t" /* XOR bits */ 486 "msr cpsr_c, %1" /* Set CPSR control field */ 487 : "=&r" (ret), "=&r" (tmp) 488 : "r" (bic), "r" (eor)); 489 490 return ret; 491 } 492 493 static __inline u_int32_t 494 __get_cpsr() 495 { 496 u_int32_t ret; 497 498 __asm volatile("mrs %0, cpsr" : "=&r" (ret)); 499 500 return ret; 501 } 502 503 #define disable_interrupts(mask) \ 504 (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ 505 (mask) & (I32_bit | F32_bit))) 506 507 #define enable_interrupts(mask) \ 508 (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) 509 510 #define restore_interrupts(old_cpsr) \ 511 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 512 513 /* 514 * Functions to manipulate cpu r13 515 * (in arm/arm/setstack.S) 516 */ 517 518 void set_stackptr (u_int mode, u_int address); 519 u_int get_stackptr (u_int mode); 520 521 /* 522 * Miscellany 523 */ 524 525 int get_pc_str_offset (void); 526 527 /* 528 * CPU functions from locore.S 529 */ 530 531 void cpu_reset (void) __attribute__((__noreturn__)); 532 533 /* 534 * Cache info variables. 535 */ 536 537 /* PRIMARY CACHE VARIABLES */ 538 extern int arm_picache_size; 539 extern int arm_picache_line_size; 540 extern int arm_picache_ways; 541 542 extern int arm_pdcache_size; /* and unified */ 543 extern int arm_pdcache_line_size; 544 extern int arm_pdcache_ways; 545 546 extern int arm_pcache_type; 547 extern int arm_pcache_unified; 548 549 extern int arm_dcache_align; 550 extern int arm_dcache_align_mask; 551 552 #endif /* _KERNEL */ 553 #endif /* _ARM_CPUFUNC_H_ */ 554 555 /* End of cpufunc.h */ 556