1 /* $OpenBSD: cpufunc.h,v 1.9 2011/09/20 22:02:13 miod Exp $ */ 2 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 3 4 /* 5 * Copyright (c) 1997 Mark Brinicombe. 6 * Copyright (c) 1997 Causality Limited 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Causality Limited. 20 * 4. The name of Causality Limited may not be used to endorse or promote 21 * products derived from this software without specific prior written 22 * permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 25 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * RiscBSD kernel project 37 * 38 * cpufunc.h 39 * 40 * Prototypes for cpu, mmu and tlb related functions. 41 */ 42 43 #ifndef _ARM_CPUFUNC_H_ 44 #define _ARM_CPUFUNC_H_ 45 46 #ifdef _KERNEL 47 48 #include <sys/types.h> 49 #include <arm/cpuconf.h> 50 51 struct cpu_functions { 52 53 /* CPU functions */ 54 55 u_int (*cf_id) (void); 56 void (*cf_cpwait) (void); 57 58 /* MMU functions */ 59 60 u_int (*cf_control) (u_int bic, u_int eor); 61 void (*cf_domains) (u_int domains); 62 void (*cf_setttb) (u_int ttb); 63 u_int (*cf_faultstatus) (void); 64 u_int (*cf_faultaddress) (void); 65 66 /* TLB functions */ 67 68 void (*cf_tlb_flushID) (void); 69 void (*cf_tlb_flushID_SE) (u_int va); 70 void (*cf_tlb_flushI) (void); 71 void (*cf_tlb_flushI_SE) (u_int va); 72 void (*cf_tlb_flushD) (void); 73 void (*cf_tlb_flushD_SE) (u_int va); 74 75 /* 76 * Cache operations: 77 * 78 * We define the following primitives: 79 * 80 * icache_sync_all Synchronize I-cache 81 * icache_sync_range Synchronize I-cache range 82 * 83 * dcache_wbinv_all Write-back and Invalidate D-cache 84 * dcache_wbinv_range Write-back and Invalidate D-cache range 85 * dcache_inv_range Invalidate D-cache range 86 * dcache_wb_range Write-back D-cache range 87 * 88 * idcache_wbinv_all Write-back and Invalidate D-cache, 89 * Invalidate I-cache 90 * idcache_wbinv_range Write-back and Invalidate D-cache, 91 * Invalidate I-cache range 92 * 93 * Note that the ARM term for "write-back" is "clean". We use 94 * the term "write-back" since it's a more common way to describe 95 * the operation. 96 * 97 * There are some rules that must be followed: 98 * 99 * I-cache Synch (all or range): 100 * The goal is to synchronize the instruction stream, 101 * so you may beed to write-back dirty D-cache blocks 102 * first. If a range is requested, and you can't 103 * synchronize just a range, you have to hit the whole 104 * thing. 105 * 106 * D-cache Write-Back and Invalidate range: 107 * If you can't WB-Inv a range, you must WB-Inv the 108 * entire D-cache. 109 * 110 * D-cache Invalidate: 111 * If you can't Inv the D-cache, you must Write-Back 112 * and Invalidate. Code that uses this operation 113 * MUST NOT assume that the D-cache will not be written 114 * back to memory. 115 * 116 * D-cache Write-Back: 117 * If you can't Write-back without doing an Inv, 118 * that's fine. Then treat this as a WB-Inv. 119 * Skipping the invalidate is merely an optimization. 120 * 121 * All operations: 122 * Valid virtual addresses must be passed to each 123 * cache operation. 124 */ 125 void (*cf_icache_sync_all) (void); 126 void (*cf_icache_sync_range) (vaddr_t, vsize_t); 127 128 void (*cf_dcache_wbinv_all) (void); 129 void (*cf_dcache_wbinv_range) (vaddr_t, vsize_t); 130 void (*cf_dcache_inv_range) (vaddr_t, vsize_t); 131 void (*cf_dcache_wb_range) (vaddr_t, vsize_t); 132 133 void (*cf_idcache_wbinv_all) (void); 134 void (*cf_idcache_wbinv_range) (vaddr_t, vsize_t); 135 136 /* Other functions */ 137 138 void (*cf_flush_prefetchbuf) (void); 139 void (*cf_drain_writebuf) (void); 140 141 void (*cf_sleep) (int mode); 142 143 /* Soft functions */ 144 void (*cf_context_switch) (u_int); 145 void (*cf_setup) (void); 146 }; 147 148 extern struct cpu_functions cpufuncs; 149 extern u_int cputype; 150 151 #define cpu_id() cpufuncs.cf_id() 152 #define cpu_cpwait() cpufuncs.cf_cpwait() 153 154 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 155 #define cpu_domains(d) cpufuncs.cf_domains(d) 156 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 157 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 158 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 159 160 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 161 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 162 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 163 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 164 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 165 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 166 167 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 168 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 169 170 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 171 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 172 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 173 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 174 175 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 176 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 177 178 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 179 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 180 181 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 182 183 #define cpu_context_switch(a) cpufuncs.cf_context_switch(a) 184 #define cpu_setup(a) cpufuncs.cf_setup(a) 185 186 int set_cpufuncs (void); 187 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 188 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 189 190 void cpufunc_nullop (void); 191 int early_abort_fixup (void *); 192 int late_abort_fixup (void *); 193 u_int cpufunc_id (void); 194 u_int cpufunc_control (u_int clear, u_int bic); 195 void cpufunc_domains (u_int domains); 196 u_int cpufunc_faultstatus (void); 197 u_int cpufunc_faultaddress (void); 198 199 #ifdef CPU_ARM8 200 void arm8_setttb (u_int ttb); 201 void arm8_tlb_flushID (void); 202 void arm8_tlb_flushID_SE (u_int va); 203 void arm8_cache_flushID (void); 204 void arm8_cache_flushID_E (u_int entry); 205 void arm8_cache_cleanID (void); 206 void arm8_cache_cleanID_E (u_int entry); 207 void arm8_cache_purgeID (void); 208 void arm8_cache_purgeID_E (u_int entry); 209 210 void arm8_cache_syncI (void); 211 void arm8_cache_cleanID_rng (vaddr_t start, vsize_t end); 212 void arm8_cache_cleanD_rng (vaddr_t start, vsize_t end); 213 void arm8_cache_purgeID_rng (vaddr_t start, vsize_t end); 214 void arm8_cache_purgeD_rng (vaddr_t start, vsize_t end); 215 void arm8_cache_syncI_rng (vaddr_t start, vsize_t end); 216 217 void arm8_context_switch (u_int); 218 219 void arm8_setup (void); 220 221 u_int arm8_clock_config (u_int, u_int); 222 #endif 223 224 #if defined(CPU_SA1100) || defined(CPU_SA1110) 225 void sa11x0_drain_readbuf (void); 226 227 void sa11x0_context_switch (u_int); 228 void sa11x0_cpu_sleep (int mode); 229 230 void sa11x0_setup (void); 231 #endif 232 233 #if defined(CPU_SA1100) || defined(CPU_SA1110) 234 void sa1_setttb (u_int ttb); 235 236 void sa1_tlb_flushID_SE (u_int va); 237 238 void sa1_cache_flushID (void); 239 void sa1_cache_flushI (void); 240 void sa1_cache_flushD (void); 241 void sa1_cache_flushD_SE (u_int entry); 242 243 void sa1_cache_cleanID (void); 244 void sa1_cache_cleanD (void); 245 void sa1_cache_cleanD_E (u_int entry); 246 247 void sa1_cache_purgeID (void); 248 void sa1_cache_purgeID_E (u_int entry); 249 void sa1_cache_purgeD (void); 250 void sa1_cache_purgeD_E (u_int entry); 251 252 void sa1_cache_syncI (void); 253 void sa1_cache_cleanID_rng (vaddr_t start, vsize_t end); 254 void sa1_cache_cleanD_rng (vaddr_t start, vsize_t end); 255 void sa1_cache_purgeID_rng (vaddr_t start, vsize_t end); 256 void sa1_cache_purgeD_rng (vaddr_t start, vsize_t end); 257 void sa1_cache_syncI_rng (vaddr_t start, vsize_t end); 258 259 #endif 260 261 #ifdef CPU_ARM9 262 void arm9_setttb (u_int); 263 264 void arm9_tlb_flushID_SE (u_int); 265 266 void arm9_icache_sync_all (void); 267 void arm9_icache_sync_range (vaddr_t, vsize_t); 268 269 void arm9_dcache_wbinv_all (void); 270 void arm9_dcache_wbinv_range (vaddr_t, vsize_t); 271 void arm9_dcache_inv_range (vaddr_t, vsize_t); 272 void arm9_dcache_wb_range (vaddr_t, vsize_t); 273 274 void arm9_idcache_wbinv_all (void); 275 void arm9_idcache_wbinv_range (vaddr_t, vsize_t); 276 277 void arm9_context_switch (u_int); 278 279 void arm9_setup (void); 280 281 extern unsigned arm9_dcache_sets_max; 282 extern unsigned arm9_dcache_sets_inc; 283 extern unsigned arm9_dcache_index_max; 284 extern unsigned arm9_dcache_index_inc; 285 #endif 286 287 #if defined(CPU_ARM9E) || defined(CPU_ARM10) 288 void arm10_tlb_flushID_SE (u_int); 289 void arm10_tlb_flushI_SE (u_int); 290 291 void arm10_context_switch (u_int); 292 293 void arm10_setup (void); 294 #endif 295 296 #if defined(CPU_ARM9E) || defined (CPU_ARM10) 297 void armv5_ec_setttb (u_int); 298 299 void armv5_ec_icache_sync_all (void); 300 void armv5_ec_icache_sync_range (vaddr_t, vsize_t); 301 302 void armv5_ec_dcache_wbinv_all (void); 303 void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t); 304 void armv5_ec_dcache_inv_range (vaddr_t, vsize_t); 305 void armv5_ec_dcache_wb_range (vaddr_t, vsize_t); 306 307 void armv5_ec_idcache_wbinv_all (void); 308 void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t); 309 #endif 310 311 #ifdef CPU_ARM11 312 void arm11_setttb (u_int); 313 314 void arm11_tlb_flushID_SE (u_int); 315 void arm11_tlb_flushI_SE (u_int); 316 317 void arm11_context_switch (u_int); 318 319 void arm11_setup (void); 320 void arm11_tlb_flushID (void); 321 void arm11_tlb_flushI (void); 322 void arm11_tlb_flushD (void); 323 void arm11_tlb_flushD_SE (u_int va); 324 325 void arm11_drain_writebuf (void); 326 void arm11_cpu_sleep (int mode); 327 #endif 328 329 330 #if defined (CPU_ARM10) || defined(CPU_ARM11) 331 void armv5_setttb (u_int); 332 333 void armv5_icache_sync_all (void); 334 void armv5_icache_sync_range (vaddr_t, vsize_t); 335 336 void armv5_dcache_wbinv_all (void); 337 void armv5_dcache_wbinv_range (vaddr_t, vsize_t); 338 void armv5_dcache_inv_range (vaddr_t, vsize_t); 339 void armv5_dcache_wb_range (vaddr_t, vsize_t); 340 341 void armv5_idcache_wbinv_all (void); 342 void armv5_idcache_wbinv_range (vaddr_t, vsize_t); 343 344 extern unsigned armv5_dcache_sets_max; 345 extern unsigned armv5_dcache_sets_inc; 346 extern unsigned armv5_dcache_index_max; 347 extern unsigned armv5_dcache_index_inc; 348 #endif 349 350 #ifdef CPU_ARMv7 351 void armv7_setttb (u_int); 352 353 void armv7_tlb_flushID_SE (u_int); 354 void armv7_tlb_flushI_SE (u_int); 355 356 void armv7_context_switch (u_int); 357 void armv7_context_switch (u_int); 358 359 void armv7_setup (void); 360 void armv7_tlb_flushID (void); 361 void armv7_tlb_flushI (void); 362 void armv7_tlb_flushD (void); 363 void armv7_tlb_flushD_SE (u_int va); 364 365 void armv7_drain_writebuf (void); 366 void armv7_cpu_sleep (int mode); 367 368 void armv7_setttb (u_int); 369 370 void armv7_icache_sync_all (void); 371 void armv7_icache_sync_range (vaddr_t, vsize_t); 372 373 void armv7_dcache_wbinv_all (void); 374 void armv7_dcache_wbinv_range (vaddr_t, vsize_t); 375 void armv7_dcache_inv_range (vaddr_t, vsize_t); 376 void armv7_dcache_wb_range (vaddr_t, vsize_t); 377 378 void armv7_idcache_wbinv_all (void); 379 void armv7_idcache_wbinv_range (vaddr_t, vsize_t); 380 381 extern unsigned armv7_dcache_sets_max; 382 extern unsigned armv7_dcache_sets_inc; 383 extern unsigned armv7_dcache_index_max; 384 extern unsigned armv7_dcache_index_inc; 385 #endif 386 387 388 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 389 defined(CPU_SA1100) || defined(CPU_SA1110) || \ 390 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 391 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 392 393 void armv4_tlb_flushID (void); 394 void armv4_tlb_flushI (void); 395 void armv4_tlb_flushD (void); 396 void armv4_tlb_flushD_SE (u_int va); 397 398 void armv4_drain_writebuf (void); 399 #endif 400 401 #if defined(CPU_IXP12X0) 402 void ixp12x0_drain_readbuf (void); 403 void ixp12x0_context_switch (u_int); 404 void ixp12x0_setup (void); 405 #endif 406 407 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 408 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 409 (ARM_MMU_XSCALE == 1) 410 void xscale_cpwait (void); 411 412 void xscale_cpu_sleep (int mode); 413 414 u_int xscale_control (u_int clear, u_int bic); 415 416 void xscale_setttb (u_int ttb); 417 418 void xscale_tlb_flushID_SE (u_int va); 419 420 void xscale_cache_flushID (void); 421 void xscale_cache_flushI (void); 422 void xscale_cache_flushD (void); 423 void xscale_cache_flushD_SE (u_int entry); 424 425 void xscale_cache_cleanID (void); 426 void xscale_cache_cleanD (void); 427 void xscale_cache_cleanD_E (u_int entry); 428 429 void xscale_cache_clean_minidata (void); 430 431 void xscale_cache_purgeID (void); 432 void xscale_cache_purgeID_E (u_int entry); 433 void xscale_cache_purgeD (void); 434 void xscale_cache_purgeD_E (u_int entry); 435 436 void xscale_cache_syncI (void); 437 void xscale_cache_cleanID_rng (vaddr_t start, vsize_t end); 438 void xscale_cache_cleanD_rng (vaddr_t start, vsize_t end); 439 void xscale_cache_purgeID_rng (vaddr_t start, vsize_t end); 440 void xscale_cache_purgeD_rng (vaddr_t start, vsize_t end); 441 void xscale_cache_syncI_rng (vaddr_t start, vsize_t end); 442 void xscale_cache_flushD_rng (vaddr_t start, vsize_t end); 443 444 void xscale_context_switch (u_int); 445 446 void xscale_setup (void); 447 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 448 449 #define tlb_flush cpu_tlb_flushID 450 #define setttb cpu_setttb 451 #define drain_writebuf cpu_drain_writebuf 452 453 /* 454 * Macros for manipulating CPU interrupts 455 */ 456 /* Functions to manipulate the CPSR. */ 457 static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor); 458 static __inline u_int32_t __get_cpsr(void); 459 460 static __inline u_int32_t 461 __set_cpsr_c(u_int bic, u_int eor) 462 { 463 u_int32_t tmp, ret; 464 465 __asm __volatile( 466 "mrs %0, cpsr\n\t" /* Get the CPSR */ 467 "bic %1, %0, %2\n\t" /* Clear bits */ 468 "eor %1, %1, %3\n\t" /* XOR bits */ 469 "msr cpsr_c, %1" /* Set CPSR control field */ 470 : "=&r" (ret), "=&r" (tmp) 471 : "r" (bic), "r" (eor)); 472 473 return ret; 474 } 475 476 static __inline u_int32_t 477 __get_cpsr() 478 { 479 u_int32_t ret; 480 481 __asm __volatile("mrs %0, cpsr" : "=&r" (ret)); 482 483 return ret; 484 } 485 486 #define disable_interrupts(mask) \ 487 (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ 488 (mask) & (I32_bit | F32_bit))) 489 490 #define enable_interrupts(mask) \ 491 (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) 492 493 #define restore_interrupts(old_cpsr) \ 494 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 495 496 /* 497 * Functions to manipulate cpu r13 498 * (in arm/arm/setstack.S) 499 */ 500 501 void set_stackptr (u_int mode, u_int address); 502 u_int get_stackptr (u_int mode); 503 504 /* 505 * Miscellany 506 */ 507 508 int get_pc_str_offset (void); 509 510 /* 511 * CPU functions from locore.S 512 */ 513 514 void cpu_reset (void) __attribute__((__noreturn__)); 515 516 /* 517 * Cache info variables. 518 */ 519 520 /* PRIMARY CACHE VARIABLES */ 521 extern int arm_picache_size; 522 extern int arm_picache_line_size; 523 extern int arm_picache_ways; 524 525 extern int arm_pdcache_size; /* and unified */ 526 extern int arm_pdcache_line_size; 527 extern int arm_pdcache_ways; 528 529 extern int arm_pcache_type; 530 extern int arm_pcache_unified; 531 532 extern int arm_dcache_align; 533 extern int arm_dcache_align_mask; 534 535 #endif /* _KERNEL */ 536 #endif /* _ARM_CPUFUNC_H_ */ 537 538 /* End of cpufunc.h */ 539