1 /* $OpenBSD: cpufunc.h,v 1.5 2008/09/11 02:38:14 kevlo Exp $ */ 2 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 3 4 /* 5 * Copyright (c) 1997 Mark Brinicombe. 6 * Copyright (c) 1997 Causality Limited 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Causality Limited. 20 * 4. The name of Causality Limited may not be used to endorse or promote 21 * products derived from this software without specific prior written 22 * permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 25 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * RiscBSD kernel project 37 * 38 * cpufunc.h 39 * 40 * Prototypes for cpu, mmu and tlb related functions. 41 */ 42 43 #ifndef _ARM32_CPUFUNC_H_ 44 #define _ARM32_CPUFUNC_H_ 45 46 #ifdef _KERNEL 47 48 #include <sys/types.h> 49 #include <arm/cpuconf.h> 50 51 struct cpu_functions { 52 53 /* CPU functions */ 54 55 u_int (*cf_id) (void); 56 void (*cf_cpwait) (void); 57 58 /* MMU functions */ 59 60 u_int (*cf_control) (u_int bic, u_int eor); 61 void (*cf_domains) (u_int domains); 62 void (*cf_setttb) (u_int ttb); 63 u_int (*cf_faultstatus) (void); 64 u_int (*cf_faultaddress) (void); 65 66 /* TLB functions */ 67 68 void (*cf_tlb_flushID) (void); 69 void (*cf_tlb_flushID_SE) (u_int va); 70 void (*cf_tlb_flushI) (void); 71 void (*cf_tlb_flushI_SE) (u_int va); 72 void (*cf_tlb_flushD) (void); 73 void (*cf_tlb_flushD_SE) (u_int va); 74 75 /* 76 * Cache operations: 77 * 78 * We define the following primitives: 79 * 80 * icache_sync_all Synchronize I-cache 81 * icache_sync_range Synchronize I-cache range 82 * 83 * dcache_wbinv_all Write-back and Invalidate D-cache 84 * dcache_wbinv_range Write-back and Invalidate D-cache range 85 * dcache_inv_range Invalidate D-cache range 86 * dcache_wb_range Write-back D-cache range 87 * 88 * idcache_wbinv_all Write-back and Invalidate D-cache, 89 * Invalidate I-cache 90 * idcache_wbinv_range Write-back and Invalidate D-cache, 91 * Invalidate I-cache range 92 * 93 * Note that the ARM term for "write-back" is "clean". We use 94 * the term "write-back" since it's a more common way to describe 95 * the operation. 96 * 97 * There are some rules that must be followed: 98 * 99 * I-cache Synch (all or range): 100 * The goal is to synchronize the instruction stream, 101 * so you may beed to write-back dirty D-cache blocks 102 * first. If a range is requested, and you can't 103 * synchronize just a range, you have to hit the whole 104 * thing. 105 * 106 * D-cache Write-Back and Invalidate range: 107 * If you can't WB-Inv a range, you must WB-Inv the 108 * entire D-cache. 109 * 110 * D-cache Invalidate: 111 * If you can't Inv the D-cache, you must Write-Back 112 * and Invalidate. Code that uses this operation 113 * MUST NOT assume that the D-cache will not be written 114 * back to memory. 115 * 116 * D-cache Write-Back: 117 * If you can't Write-back without doing an Inv, 118 * that's fine. Then treat this as a WB-Inv. 119 * Skipping the invalidate is merely an optimization. 120 * 121 * All operations: 122 * Valid virtual addresses must be passed to each 123 * cache operation. 124 */ 125 void (*cf_icache_sync_all) (void); 126 void (*cf_icache_sync_range) (vaddr_t, vsize_t); 127 128 void (*cf_dcache_wbinv_all) (void); 129 void (*cf_dcache_wbinv_range) (vaddr_t, vsize_t); 130 void (*cf_dcache_inv_range) (vaddr_t, vsize_t); 131 void (*cf_dcache_wb_range) (vaddr_t, vsize_t); 132 133 void (*cf_idcache_wbinv_all) (void); 134 void (*cf_idcache_wbinv_range) (vaddr_t, vsize_t); 135 136 /* Other functions */ 137 138 void (*cf_flush_prefetchbuf) (void); 139 void (*cf_drain_writebuf) (void); 140 void (*cf_flush_brnchtgt_C) (void); 141 void (*cf_flush_brnchtgt_E) (u_int va); 142 143 void (*cf_sleep) (int mode); 144 145 /* Soft functions */ 146 147 int (*cf_dataabt_fixup) (void *arg); 148 int (*cf_prefetchabt_fixup) (void *arg); 149 150 void (*cf_context_switch) (u_int); 151 152 void (*cf_setup) (char *string); 153 }; 154 155 extern struct cpu_functions cpufuncs; 156 extern u_int cputype; 157 158 #define cpu_id() cpufuncs.cf_id() 159 #define cpu_cpwait() cpufuncs.cf_cpwait() 160 161 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 162 #define cpu_domains(d) cpufuncs.cf_domains(d) 163 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 164 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 165 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 166 167 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 168 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 169 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 170 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 171 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 172 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 173 174 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 175 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 176 177 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 178 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 179 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 180 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 181 182 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 183 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 184 185 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 186 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 187 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 188 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 189 190 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 191 192 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 193 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 194 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 195 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 196 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 197 198 #define cpu_context_switch(a) cpufuncs.cf_context_switch(a) 199 #define cpu_setup(a) cpufuncs.cf_setup(a) 200 201 int set_cpufuncs (void); 202 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 203 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 204 205 void cpufunc_nullop (void); 206 int cpufunc_null_fixup (void *); 207 int early_abort_fixup (void *); 208 int late_abort_fixup (void *); 209 u_int cpufunc_id (void); 210 u_int cpufunc_control (u_int clear, u_int bic); 211 void cpufunc_domains (u_int domains); 212 u_int cpufunc_faultstatus (void); 213 u_int cpufunc_faultaddress (void); 214 215 #ifdef CPU_ARM3 216 u_int arm3_control (u_int clear, u_int bic); 217 void arm3_cache_flush (void); 218 #endif /* CPU_ARM3 */ 219 220 #if defined(CPU_ARM6) || defined(CPU_ARM7) 221 void arm67_setttb (u_int ttb); 222 void arm67_tlb_flush (void); 223 void arm67_tlb_purge (u_int va); 224 void arm67_cache_flush (void); 225 void arm67_context_switch (u_int); 226 #endif /* CPU_ARM6 || CPU_ARM7 */ 227 228 #ifdef CPU_ARM6 229 void arm6_setup (char *string); 230 #endif /* CPU_ARM6 */ 231 232 #ifdef CPU_ARM7 233 void arm7_setup (char *string); 234 #endif /* CPU_ARM7 */ 235 236 #ifdef CPU_ARM7TDMI 237 int arm7_dataabt_fixup (void *arg); 238 void arm7tdmi_setup (char *string); 239 void arm7tdmi_setttb (u_int ttb); 240 void arm7tdmi_tlb_flushID (void); 241 void arm7tdmi_tlb_flushID_SE (u_int va); 242 void arm7tdmi_cache_flushID (void); 243 void arm7tdmi_context_switch (u_int); 244 #endif /* CPU_ARM7TDMI */ 245 246 #ifdef CPU_ARM8 247 void arm8_setttb (u_int ttb); 248 void arm8_tlb_flushID (void); 249 void arm8_tlb_flushID_SE (u_int va); 250 void arm8_cache_flushID (void); 251 void arm8_cache_flushID_E (u_int entry); 252 void arm8_cache_cleanID (void); 253 void arm8_cache_cleanID_E (u_int entry); 254 void arm8_cache_purgeID (void); 255 void arm8_cache_purgeID_E (u_int entry); 256 257 void arm8_cache_syncI (void); 258 void arm8_cache_cleanID_rng (vaddr_t start, vsize_t end); 259 void arm8_cache_cleanD_rng (vaddr_t start, vsize_t end); 260 void arm8_cache_purgeID_rng (vaddr_t start, vsize_t end); 261 void arm8_cache_purgeD_rng (vaddr_t start, vsize_t end); 262 void arm8_cache_syncI_rng (vaddr_t start, vsize_t end); 263 264 void arm8_context_switch (u_int); 265 266 void arm8_setup (char *string); 267 268 u_int arm8_clock_config (u_int, u_int); 269 #endif 270 271 #ifdef CPU_SA110 272 void sa110_setup (char *string); 273 void sa110_context_switch (u_int); 274 #endif /* CPU_SA110 */ 275 276 #if defined(CPU_SA1100) || defined(CPU_SA1110) 277 void sa11x0_drain_readbuf (void); 278 279 void sa11x0_context_switch (u_int); 280 void sa11x0_cpu_sleep (int mode); 281 282 void sa11x0_setup (char *string); 283 #endif 284 285 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 286 void sa1_setttb (u_int ttb); 287 288 void sa1_tlb_flushID_SE (u_int va); 289 290 void sa1_cache_flushID (void); 291 void sa1_cache_flushI (void); 292 void sa1_cache_flushD (void); 293 void sa1_cache_flushD_SE (u_int entry); 294 295 void sa1_cache_cleanID (void); 296 void sa1_cache_cleanD (void); 297 void sa1_cache_cleanD_E (u_int entry); 298 299 void sa1_cache_purgeID (void); 300 void sa1_cache_purgeID_E (u_int entry); 301 void sa1_cache_purgeD (void); 302 void sa1_cache_purgeD_E (u_int entry); 303 304 void sa1_cache_syncI (void); 305 void sa1_cache_cleanID_rng (vaddr_t start, vsize_t end); 306 void sa1_cache_cleanD_rng (vaddr_t start, vsize_t end); 307 void sa1_cache_purgeID_rng (vaddr_t start, vsize_t end); 308 void sa1_cache_purgeD_rng (vaddr_t start, vsize_t end); 309 void sa1_cache_syncI_rng (vaddr_t start, vsize_t end); 310 311 #endif 312 313 #ifdef CPU_ARM9 314 void arm9_setttb (u_int); 315 316 void arm9_tlb_flushID_SE (u_int); 317 318 void arm9_icache_sync_all (void); 319 void arm9_icache_sync_range (vaddr_t, vsize_t); 320 321 void arm9_dcache_wbinv_all (void); 322 void arm9_dcache_wbinv_range (vaddr_t, vsize_t); 323 void arm9_dcache_inv_range (vaddr_t, vsize_t); 324 void arm9_dcache_wb_range (vaddr_t, vsize_t); 325 326 void arm9_idcache_wbinv_all (void); 327 void arm9_idcache_wbinv_range (vaddr_t, vsize_t); 328 329 void arm9_context_switch (u_int); 330 331 void arm9_setup (char *string); 332 333 extern unsigned arm9_dcache_sets_max; 334 extern unsigned arm9_dcache_sets_inc; 335 extern unsigned arm9_dcache_index_max; 336 extern unsigned arm9_dcache_index_inc; 337 #endif 338 339 #if defined(CPU_ARM9E) || defined(CPU_ARM10) 340 void arm10_tlb_flushID_SE (u_int); 341 void arm10_tlb_flushI_SE (u_int); 342 343 void arm10_context_switch (u_int); 344 345 void arm10_setup (char *string); 346 #endif 347 348 #if defined(CPU_ARM9E) || defined (CPU_ARM10) 349 void armv5_ec_setttb (u_int); 350 351 void armv5_ec_icache_sync_all (void); 352 void armv5_ec_icache_sync_range (vaddr_t, vsize_t); 353 354 void armv5_ec_dcache_wbinv_all (void); 355 void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t); 356 void armv5_ec_dcache_inv_range (vaddr_t, vsize_t); 357 void armv5_ec_dcache_wb_range (vaddr_t, vsize_t); 358 359 void armv5_ec_idcache_wbinv_all (void); 360 void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t); 361 #endif 362 363 #if defined (CPU_ARM10) 364 void armv5_setttb (u_int); 365 366 void armv5_icache_sync_all (void); 367 void armv5_icache_sync_range (vaddr_t, vsize_t); 368 369 void armv5_dcache_wbinv_all (void); 370 void armv5_dcache_wbinv_range (vaddr_t, vsize_t); 371 void armv5_dcache_inv_range (vaddr_t, vsize_t); 372 void armv5_dcache_wb_range (vaddr_t, vsize_t); 373 374 void armv5_idcache_wbinv_all (void); 375 void armv5_idcache_wbinv_range (vaddr_t, vsize_t); 376 377 extern unsigned armv5_dcache_sets_max; 378 extern unsigned armv5_dcache_sets_inc; 379 extern unsigned armv5_dcache_index_max; 380 extern unsigned armv5_dcache_index_inc; 381 #endif 382 383 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 384 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 385 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 386 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 387 388 void armv4_tlb_flushID (void); 389 void armv4_tlb_flushI (void); 390 void armv4_tlb_flushD (void); 391 void armv4_tlb_flushD_SE (u_int va); 392 393 void armv4_drain_writebuf (void); 394 #endif 395 396 #if defined(CPU_IXP12X0) 397 void ixp12x0_drain_readbuf (void); 398 void ixp12x0_context_switch (u_int); 399 void ixp12x0_setup (char *string); 400 #endif 401 402 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 403 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 404 (ARM_MMU_XSCALE == 1) 405 void xscale_cpwait (void); 406 407 void xscale_cpu_sleep (int mode); 408 409 u_int xscale_control (u_int clear, u_int bic); 410 411 void xscale_setttb (u_int ttb); 412 413 void xscale_tlb_flushID_SE (u_int va); 414 415 void xscale_cache_flushID (void); 416 void xscale_cache_flushI (void); 417 void xscale_cache_flushD (void); 418 void xscale_cache_flushD_SE (u_int entry); 419 420 void xscale_cache_cleanID (void); 421 void xscale_cache_cleanD (void); 422 void xscale_cache_cleanD_E (u_int entry); 423 424 void xscale_cache_clean_minidata (void); 425 426 void xscale_cache_purgeID (void); 427 void xscale_cache_purgeID_E (u_int entry); 428 void xscale_cache_purgeD (void); 429 void xscale_cache_purgeD_E (u_int entry); 430 431 void xscale_cache_syncI (void); 432 void xscale_cache_cleanID_rng (vaddr_t start, vsize_t end); 433 void xscale_cache_cleanD_rng (vaddr_t start, vsize_t end); 434 void xscale_cache_purgeID_rng (vaddr_t start, vsize_t end); 435 void xscale_cache_purgeD_rng (vaddr_t start, vsize_t end); 436 void xscale_cache_syncI_rng (vaddr_t start, vsize_t end); 437 void xscale_cache_flushD_rng (vaddr_t start, vsize_t end); 438 439 void xscale_context_switch (u_int); 440 441 void xscale_setup (char *string); 442 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 443 444 #define tlb_flush cpu_tlb_flushID 445 #define setttb cpu_setttb 446 #define drain_writebuf cpu_drain_writebuf 447 448 /* 449 * Macros for manipulating CPU interrupts 450 */ 451 #ifdef __PROG32 452 /* Functions to manipulate the CPSR. */ 453 static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor); 454 static __inline u_int32_t __get_cpsr(void); 455 456 static __inline u_int32_t 457 __set_cpsr_c(u_int bic, u_int eor) 458 { 459 u_int32_t tmp, ret; 460 461 __asm __volatile( 462 "mrs %0, cpsr\n" /* Get the CPSR */ 463 "bic %1, %0, %2\n" /* Clear bits */ 464 "eor %1, %1, %3\n" /* XOR bits */ 465 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 466 : "=&r" (ret), "=&r" (tmp) 467 : "r" (bic), "r" (eor)); 468 469 return ret; 470 } 471 472 static __inline u_int32_t 473 __get_cpsr() 474 { 475 u_int32_t ret; 476 477 __asm __volatile("mrs %0, cpsr" : "=&r" (ret)); 478 479 return ret; 480 } 481 482 #define disable_interrupts(mask) \ 483 (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ 484 (mask) & (I32_bit | F32_bit))) 485 486 #define enable_interrupts(mask) \ 487 (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) 488 489 #define restore_interrupts(old_cpsr) \ 490 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 491 #else /* ! __PROG32 */ 492 #define disable_interrupts(mask) \ 493 (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ 494 (mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) 495 496 #define enable_interrupts(mask) \ 497 (set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0)) 498 499 #define restore_interrupts(old_r15) \ 500 (set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \ 501 (old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE))) 502 503 /* Functions to manipulate the processor control bits in r15. */ 504 u_int set_r15(u_int bic, u_int eor); 505 u_int get_r15(void); 506 #endif /* __PROG32 */ 507 508 /* 509 * Functions to manipulate cpu r13 510 * (in arm/arm/setstack.S) 511 */ 512 513 void set_stackptr (u_int mode, u_int address); 514 u_int get_stackptr (u_int mode); 515 516 /* 517 * Miscellany 518 */ 519 520 int get_pc_str_offset (void); 521 522 /* 523 * CPU functions from locore.S 524 */ 525 526 void cpu_reset (void) __attribute__((__noreturn__)); 527 528 /* 529 * Cache info variables. 530 */ 531 532 /* PRIMARY CACHE VARIABLES */ 533 extern int arm_picache_size; 534 extern int arm_picache_line_size; 535 extern int arm_picache_ways; 536 537 extern int arm_pdcache_size; /* and unified */ 538 extern int arm_pdcache_line_size; 539 extern int arm_pdcache_ways; 540 541 extern int arm_pcache_type; 542 extern int arm_pcache_unified; 543 544 extern int arm_dcache_align; 545 extern int arm_dcache_align_mask; 546 547 #endif /* _KERNEL */ 548 #endif /* _ARM32_CPUFUNC_H_ */ 549 550 /* End of cpufunc.h */ 551